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DecaRange RTLS ARM Application
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Go to the source code of this file.
Macros | |
| #define | WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000)) |
| #define | WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004)) |
| #define | WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008)) |
| #define | WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C)) |
| #define | WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010)) |
| #define | WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014)) |
| #define | WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418)) |
| #define | WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00)) |
| #define | WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000)) |
| #define | WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004)) |
| #define | WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008)) |
| #define | WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C)) |
| #define | WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010)) |
| #define | WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014)) |
| #define | WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418)) |
| #define | WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00)) |
| #define | GPIO_DATA_R_OFF (0x3FCUL) |
| #define | GPIO_DIR_R_OFF (0x400UL) |
| #define | GPIO_IS_R_OFF (0x404UL) |
| #define | GPIO_IBE_R_OFF (0x408UL) |
| #define | GPIO_IEV_R_OFF (0x40CUL) |
| #define | GPIO_IM_R_OFF (0x410UL) |
| #define | GPIO_RIS_R_OFF (0x414UL) |
| #define | GPIO_MIS_R_OFF (0x418UL) |
| #define | GPIO_ICR_R_OFF (0x41CUL) |
| #define | GPIO_AFSEL_R_OFF (0x420UL) |
| #define | GPIO_DR2R_R_OFF (0x500UL) |
| #define | GPIO_DR4R_R_OFF (0x504UL) |
| #define | GPIO_DR8R_R_OFF (0x508UL) |
| #define | GPIO_ODR_R_OFF (0x50CUL) |
| #define | GPIO_PUR_R_OFF (0x510UL) |
| #define | GPIO_PDR_R_OFF (0x514UL) |
| #define | GPIO_SLR_R_OFF (0x518UL) |
| #define | GPIO_DEN_R_OFF (0x51CUL) |
| #define | GPIO_LOCK_R_OFF (0x520UL) |
| #define | GPIO_CR_R_OFF (0x524UL) |
| #define | GPIO_AMSEL_R_OFF (0x528UL) |
| #define | GPIO_PCTL_R_OFF (0x52CUL) |
| #define | GPIO_ADCCTL_R_OFF (0x530UL) |
| #define | GPIO_DMACTL_R_OFF (0x534UL) |
| #define | GPIO_SI_R_OFF (0x538UL) |
| #define | GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000) |
| #define | GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC)) |
| #define | GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400)) |
| #define | GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404)) |
| #define | GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408)) |
| #define | GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C)) |
| #define | GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410)) |
| #define | GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414)) |
| #define | GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418)) |
| #define | GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C)) |
| #define | GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420)) |
| #define | GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500)) |
| #define | GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504)) |
| #define | GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508)) |
| #define | GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C)) |
| #define | GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510)) |
| #define | GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514)) |
| #define | GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518)) |
| #define | GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C)) |
| #define | GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520)) |
| #define | GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524)) |
| #define | GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528)) |
| #define | GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C)) |
| #define | GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530)) |
| #define | GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534)) |
| #define | GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538)) |
| #define | GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000) |
| #define | GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC)) |
| #define | GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400)) |
| #define | GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404)) |
| #define | GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408)) |
| #define | GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C)) |
| #define | GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410)) |
| #define | GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414)) |
| #define | GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418)) |
| #define | GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C)) |
| #define | GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420)) |
| #define | GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500)) |
| #define | GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504)) |
| #define | GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508)) |
| #define | GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C)) |
| #define | GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510)) |
| #define | GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514)) |
| #define | GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518)) |
| #define | GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C)) |
| #define | GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520)) |
| #define | GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524)) |
| #define | GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528)) |
| #define | GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C)) |
| #define | GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530)) |
| #define | GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534)) |
| #define | GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538)) |
| #define | GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000) |
| #define | GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC)) |
| #define | GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400)) |
| #define | GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404)) |
| #define | GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408)) |
| #define | GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C)) |
| #define | GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410)) |
| #define | GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414)) |
| #define | GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418)) |
| #define | GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C)) |
| #define | GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420)) |
| #define | GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500)) |
| #define | GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504)) |
| #define | GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508)) |
| #define | GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C)) |
| #define | GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510)) |
| #define | GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514)) |
| #define | GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518)) |
| #define | GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C)) |
| #define | GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520)) |
| #define | GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524)) |
| #define | GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528)) |
| #define | GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C)) |
| #define | GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530)) |
| #define | GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534)) |
| #define | GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538)) |
| #define | GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000) |
| #define | GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC)) |
| #define | GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400)) |
| #define | GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404)) |
| #define | GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408)) |
| #define | GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C)) |
| #define | GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410)) |
| #define | GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414)) |
| #define | GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418)) |
| #define | GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C)) |
| #define | GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420)) |
| #define | GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500)) |
| #define | GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504)) |
| #define | GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508)) |
| #define | GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C)) |
| #define | GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510)) |
| #define | GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514)) |
| #define | GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518)) |
| #define | GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C)) |
| #define | GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520)) |
| #define | GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524)) |
| #define | GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528)) |
| #define | GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C)) |
| #define | GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530)) |
| #define | GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534)) |
| #define | GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538)) |
| #define | SSI0_CR0_R (*((volatile unsigned long *)0x40008000)) |
| #define | SSI0_CR1_R (*((volatile unsigned long *)0x40008004)) |
| #define | SSI0_DR_R (*((volatile unsigned long *)0x40008008)) |
| #define | SSI0_SR_R (*((volatile unsigned long *)0x4000800C)) |
| #define | SSI0_CPSR_R (*((volatile unsigned long *)0x40008010)) |
| #define | SSI0_IM_R (*((volatile unsigned long *)0x40008014)) |
| #define | SSI0_RIS_R (*((volatile unsigned long *)0x40008018)) |
| #define | SSI0_MIS_R (*((volatile unsigned long *)0x4000801C)) |
| #define | SSI0_ICR_R (*((volatile unsigned long *)0x40008020)) |
| #define | SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024)) |
| #define | SSI0_CC_R (*((volatile unsigned long *)0x40008FC8)) |
| #define | SSI1_CR0_R (*((volatile unsigned long *)0x40009000)) |
| #define | SSI1_CR1_R (*((volatile unsigned long *)0x40009004)) |
| #define | SSI1_DR_R (*((volatile unsigned long *)0x40009008)) |
| #define | SSI1_SR_R (*((volatile unsigned long *)0x4000900C)) |
| #define | SSI1_CPSR_R (*((volatile unsigned long *)0x40009010)) |
| #define | SSI1_IM_R (*((volatile unsigned long *)0x40009014)) |
| #define | SSI1_RIS_R (*((volatile unsigned long *)0x40009018)) |
| #define | SSI1_MIS_R (*((volatile unsigned long *)0x4000901C)) |
| #define | SSI1_ICR_R (*((volatile unsigned long *)0x40009020)) |
| #define | SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024)) |
| #define | SSI1_CC_R (*((volatile unsigned long *)0x40009FC8)) |
| #define | SSI2_CR0_R (*((volatile unsigned long *)0x4000A000)) |
| #define | SSI2_CR1_R (*((volatile unsigned long *)0x4000A004)) |
| #define | SSI2_DR_R (*((volatile unsigned long *)0x4000A008)) |
| #define | SSI2_SR_R (*((volatile unsigned long *)0x4000A00C)) |
| #define | SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010)) |
| #define | SSI2_IM_R (*((volatile unsigned long *)0x4000A014)) |
| #define | SSI2_RIS_R (*((volatile unsigned long *)0x4000A018)) |
| #define | SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C)) |
| #define | SSI2_ICR_R (*((volatile unsigned long *)0x4000A020)) |
| #define | SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024)) |
| #define | SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8)) |
| #define | SSI3_CR0_R (*((volatile unsigned long *)0x4000B000)) |
| #define | SSI3_CR1_R (*((volatile unsigned long *)0x4000B004)) |
| #define | SSI3_DR_R (*((volatile unsigned long *)0x4000B008)) |
| #define | SSI3_SR_R (*((volatile unsigned long *)0x4000B00C)) |
| #define | SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010)) |
| #define | SSI3_IM_R (*((volatile unsigned long *)0x4000B014)) |
| #define | SSI3_RIS_R (*((volatile unsigned long *)0x4000B018)) |
| #define | SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C)) |
| #define | SSI3_ICR_R (*((volatile unsigned long *)0x4000B020)) |
| #define | SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024)) |
| #define | SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8)) |
| #define | UART0_DR_R (*((volatile unsigned long *)0x4000C000)) |
| #define | UART0_RSR_R (*((volatile unsigned long *)0x4000C004)) |
| #define | UART0_ECR_R (*((volatile unsigned long *)0x4000C004)) |
| #define | UART0_FR_R (*((volatile unsigned long *)0x4000C018)) |
| #define | UART0_ILPR_R (*((volatile unsigned long *)0x4000C020)) |
| #define | UART0_IBRD_R (*((volatile unsigned long *)0x4000C024)) |
| #define | UART0_FBRD_R (*((volatile unsigned long *)0x4000C028)) |
| #define | UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C)) |
| #define | UART0_CTL_R (*((volatile unsigned long *)0x4000C030)) |
| #define | UART0_IFLS_R (*((volatile unsigned long *)0x4000C034)) |
| #define | UART0_IM_R (*((volatile unsigned long *)0x4000C038)) |
| #define | UART0_RIS_R (*((volatile unsigned long *)0x4000C03C)) |
| #define | UART0_MIS_R (*((volatile unsigned long *)0x4000C040)) |
| #define | UART0_ICR_R (*((volatile unsigned long *)0x4000C044)) |
| #define | UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048)) |
| #define | UART0_LCTL_R (*((volatile unsigned long *)0x4000C090)) |
| #define | UART0_LSS_R (*((volatile unsigned long *)0x4000C094)) |
| #define | UART0_LTIM_R (*((volatile unsigned long *)0x4000C098)) |
| #define | UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4)) |
| #define | UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8)) |
| #define | UART0_PP_R (*((volatile unsigned long *)0x4000CFC0)) |
| #define | UART0_CC_R (*((volatile unsigned long *)0x4000CFC8)) |
| #define | UART1_DR_R (*((volatile unsigned long *)0x4000D000)) |
| #define | UART1_RSR_R (*((volatile unsigned long *)0x4000D004)) |
| #define | UART1_ECR_R (*((volatile unsigned long *)0x4000D004)) |
| #define | UART1_FR_R (*((volatile unsigned long *)0x4000D018)) |
| #define | UART1_ILPR_R (*((volatile unsigned long *)0x4000D020)) |
| #define | UART1_IBRD_R (*((volatile unsigned long *)0x4000D024)) |
| #define | UART1_FBRD_R (*((volatile unsigned long *)0x4000D028)) |
| #define | UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C)) |
| #define | UART1_CTL_R (*((volatile unsigned long *)0x4000D030)) |
| #define | UART1_IFLS_R (*((volatile unsigned long *)0x4000D034)) |
| #define | UART1_IM_R (*((volatile unsigned long *)0x4000D038)) |
| #define | UART1_RIS_R (*((volatile unsigned long *)0x4000D03C)) |
| #define | UART1_MIS_R (*((volatile unsigned long *)0x4000D040)) |
| #define | UART1_ICR_R (*((volatile unsigned long *)0x4000D044)) |
| #define | UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048)) |
| #define | UART1_LCTL_R (*((volatile unsigned long *)0x4000D090)) |
| #define | UART1_LSS_R (*((volatile unsigned long *)0x4000D094)) |
| #define | UART1_LTIM_R (*((volatile unsigned long *)0x4000D098)) |
| #define | UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4)) |
| #define | UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8)) |
| #define | UART1_PP_R (*((volatile unsigned long *)0x4000DFC0)) |
| #define | UART1_CC_R (*((volatile unsigned long *)0x4000DFC8)) |
| #define | UART2_DR_R (*((volatile unsigned long *)0x4000E000)) |
| #define | UART2_RSR_R (*((volatile unsigned long *)0x4000E004)) |
| #define | UART2_ECR_R (*((volatile unsigned long *)0x4000E004)) |
| #define | UART2_FR_R (*((volatile unsigned long *)0x4000E018)) |
| #define | UART2_ILPR_R (*((volatile unsigned long *)0x4000E020)) |
| #define | UART2_IBRD_R (*((volatile unsigned long *)0x4000E024)) |
| #define | UART2_FBRD_R (*((volatile unsigned long *)0x4000E028)) |
| #define | UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C)) |
| #define | UART2_CTL_R (*((volatile unsigned long *)0x4000E030)) |
| #define | UART2_IFLS_R (*((volatile unsigned long *)0x4000E034)) |
| #define | UART2_IM_R (*((volatile unsigned long *)0x4000E038)) |
| #define | UART2_RIS_R (*((volatile unsigned long *)0x4000E03C)) |
| #define | UART2_MIS_R (*((volatile unsigned long *)0x4000E040)) |
| #define | UART2_ICR_R (*((volatile unsigned long *)0x4000E044)) |
| #define | UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048)) |
| #define | UART2_LCTL_R (*((volatile unsigned long *)0x4000E090)) |
| #define | UART2_LSS_R (*((volatile unsigned long *)0x4000E094)) |
| #define | UART2_LTIM_R (*((volatile unsigned long *)0x4000E098)) |
| #define | UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4)) |
| #define | UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8)) |
| #define | UART2_PP_R (*((volatile unsigned long *)0x4000EFC0)) |
| #define | UART2_CC_R (*((volatile unsigned long *)0x4000EFC8)) |
| #define | UART3_DR_R (*((volatile unsigned long *)0x4000F000)) |
| #define | UART3_RSR_R (*((volatile unsigned long *)0x4000F004)) |
| #define | UART3_ECR_R (*((volatile unsigned long *)0x4000F004)) |
| #define | UART3_FR_R (*((volatile unsigned long *)0x4000F018)) |
| #define | UART3_ILPR_R (*((volatile unsigned long *)0x4000F020)) |
| #define | UART3_IBRD_R (*((volatile unsigned long *)0x4000F024)) |
| #define | UART3_FBRD_R (*((volatile unsigned long *)0x4000F028)) |
| #define | UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C)) |
| #define | UART3_CTL_R (*((volatile unsigned long *)0x4000F030)) |
| #define | UART3_IFLS_R (*((volatile unsigned long *)0x4000F034)) |
| #define | UART3_IM_R (*((volatile unsigned long *)0x4000F038)) |
| #define | UART3_RIS_R (*((volatile unsigned long *)0x4000F03C)) |
| #define | UART3_MIS_R (*((volatile unsigned long *)0x4000F040)) |
| #define | UART3_ICR_R (*((volatile unsigned long *)0x4000F044)) |
| #define | UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048)) |
| #define | UART3_LCTL_R (*((volatile unsigned long *)0x4000F090)) |
| #define | UART3_LSS_R (*((volatile unsigned long *)0x4000F094)) |
| #define | UART3_LTIM_R (*((volatile unsigned long *)0x4000F098)) |
| #define | UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4)) |
| #define | UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8)) |
| #define | UART3_PP_R (*((volatile unsigned long *)0x4000FFC0)) |
| #define | UART3_CC_R (*((volatile unsigned long *)0x4000FFC8)) |
| #define | UART4_DR_R (*((volatile unsigned long *)0x40010000)) |
| #define | UART4_RSR_R (*((volatile unsigned long *)0x40010004)) |
| #define | UART4_ECR_R (*((volatile unsigned long *)0x40010004)) |
| #define | UART4_FR_R (*((volatile unsigned long *)0x40010018)) |
| #define | UART4_ILPR_R (*((volatile unsigned long *)0x40010020)) |
| #define | UART4_IBRD_R (*((volatile unsigned long *)0x40010024)) |
| #define | UART4_FBRD_R (*((volatile unsigned long *)0x40010028)) |
| #define | UART4_LCRH_R (*((volatile unsigned long *)0x4001002C)) |
| #define | UART4_CTL_R (*((volatile unsigned long *)0x40010030)) |
| #define | UART4_IFLS_R (*((volatile unsigned long *)0x40010034)) |
| #define | UART4_IM_R (*((volatile unsigned long *)0x40010038)) |
| #define | UART4_RIS_R (*((volatile unsigned long *)0x4001003C)) |
| #define | UART4_MIS_R (*((volatile unsigned long *)0x40010040)) |
| #define | UART4_ICR_R (*((volatile unsigned long *)0x40010044)) |
| #define | UART4_DMACTL_R (*((volatile unsigned long *)0x40010048)) |
| #define | UART4_LCTL_R (*((volatile unsigned long *)0x40010090)) |
| #define | UART4_LSS_R (*((volatile unsigned long *)0x40010094)) |
| #define | UART4_LTIM_R (*((volatile unsigned long *)0x40010098)) |
| #define | UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4)) |
| #define | UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8)) |
| #define | UART4_PP_R (*((volatile unsigned long *)0x40010FC0)) |
| #define | UART4_CC_R (*((volatile unsigned long *)0x40010FC8)) |
| #define | UART5_DR_R (*((volatile unsigned long *)0x40011000)) |
| #define | UART5_RSR_R (*((volatile unsigned long *)0x40011004)) |
| #define | UART5_ECR_R (*((volatile unsigned long *)0x40011004)) |
| #define | UART5_FR_R (*((volatile unsigned long *)0x40011018)) |
| #define | UART5_ILPR_R (*((volatile unsigned long *)0x40011020)) |
| #define | UART5_IBRD_R (*((volatile unsigned long *)0x40011024)) |
| #define | UART5_FBRD_R (*((volatile unsigned long *)0x40011028)) |
| #define | UART5_LCRH_R (*((volatile unsigned long *)0x4001102C)) |
| #define | UART5_CTL_R (*((volatile unsigned long *)0x40011030)) |
| #define | UART5_IFLS_R (*((volatile unsigned long *)0x40011034)) |
| #define | UART5_IM_R (*((volatile unsigned long *)0x40011038)) |
| #define | UART5_RIS_R (*((volatile unsigned long *)0x4001103C)) |
| #define | UART5_MIS_R (*((volatile unsigned long *)0x40011040)) |
| #define | UART5_ICR_R (*((volatile unsigned long *)0x40011044)) |
| #define | UART5_DMACTL_R (*((volatile unsigned long *)0x40011048)) |
| #define | UART5_LCTL_R (*((volatile unsigned long *)0x40011090)) |
| #define | UART5_LSS_R (*((volatile unsigned long *)0x40011094)) |
| #define | UART5_LTIM_R (*((volatile unsigned long *)0x40011098)) |
| #define | UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4)) |
| #define | UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8)) |
| #define | UART5_PP_R (*((volatile unsigned long *)0x40011FC0)) |
| #define | UART5_CC_R (*((volatile unsigned long *)0x40011FC8)) |
| #define | UART6_DR_R (*((volatile unsigned long *)0x40012000)) |
| #define | UART6_RSR_R (*((volatile unsigned long *)0x40012004)) |
| #define | UART6_ECR_R (*((volatile unsigned long *)0x40012004)) |
| #define | UART6_FR_R (*((volatile unsigned long *)0x40012018)) |
| #define | UART6_ILPR_R (*((volatile unsigned long *)0x40012020)) |
| #define | UART6_IBRD_R (*((volatile unsigned long *)0x40012024)) |
| #define | UART6_FBRD_R (*((volatile unsigned long *)0x40012028)) |
| #define | UART6_LCRH_R (*((volatile unsigned long *)0x4001202C)) |
| #define | UART6_CTL_R (*((volatile unsigned long *)0x40012030)) |
| #define | UART6_IFLS_R (*((volatile unsigned long *)0x40012034)) |
| #define | UART6_IM_R (*((volatile unsigned long *)0x40012038)) |
| #define | UART6_RIS_R (*((volatile unsigned long *)0x4001203C)) |
| #define | UART6_MIS_R (*((volatile unsigned long *)0x40012040)) |
| #define | UART6_ICR_R (*((volatile unsigned long *)0x40012044)) |
| #define | UART6_DMACTL_R (*((volatile unsigned long *)0x40012048)) |
| #define | UART6_LCTL_R (*((volatile unsigned long *)0x40012090)) |
| #define | UART6_LSS_R (*((volatile unsigned long *)0x40012094)) |
| #define | UART6_LTIM_R (*((volatile unsigned long *)0x40012098)) |
| #define | UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4)) |
| #define | UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8)) |
| #define | UART6_PP_R (*((volatile unsigned long *)0x40012FC0)) |
| #define | UART6_CC_R (*((volatile unsigned long *)0x40012FC8)) |
| #define | UART7_DR_R (*((volatile unsigned long *)0x40013000)) |
| #define | UART7_RSR_R (*((volatile unsigned long *)0x40013004)) |
| #define | UART7_ECR_R (*((volatile unsigned long *)0x40013004)) |
| #define | UART7_FR_R (*((volatile unsigned long *)0x40013018)) |
| #define | UART7_ILPR_R (*((volatile unsigned long *)0x40013020)) |
| #define | UART7_IBRD_R (*((volatile unsigned long *)0x40013024)) |
| #define | UART7_FBRD_R (*((volatile unsigned long *)0x40013028)) |
| #define | UART7_LCRH_R (*((volatile unsigned long *)0x4001302C)) |
| #define | UART7_CTL_R (*((volatile unsigned long *)0x40013030)) |
| #define | UART7_IFLS_R (*((volatile unsigned long *)0x40013034)) |
| #define | UART7_IM_R (*((volatile unsigned long *)0x40013038)) |
| #define | UART7_RIS_R (*((volatile unsigned long *)0x4001303C)) |
| #define | UART7_MIS_R (*((volatile unsigned long *)0x40013040)) |
| #define | UART7_ICR_R (*((volatile unsigned long *)0x40013044)) |
| #define | UART7_DMACTL_R (*((volatile unsigned long *)0x40013048)) |
| #define | UART7_LCTL_R (*((volatile unsigned long *)0x40013090)) |
| #define | UART7_LSS_R (*((volatile unsigned long *)0x40013094)) |
| #define | UART7_LTIM_R (*((volatile unsigned long *)0x40013098)) |
| #define | UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4)) |
| #define | UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8)) |
| #define | UART7_PP_R (*((volatile unsigned long *)0x40013FC0)) |
| #define | UART7_CC_R (*((volatile unsigned long *)0x40013FC8)) |
| #define | I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000)) |
| #define | I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004)) |
| #define | I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008)) |
| #define | I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C)) |
| #define | I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010)) |
| #define | I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014)) |
| #define | I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018)) |
| #define | I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C)) |
| #define | I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020)) |
| #define | I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024)) |
| #define | I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C)) |
| #define | I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800)) |
| #define | I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804)) |
| #define | I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808)) |
| #define | I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C)) |
| #define | I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810)) |
| #define | I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814)) |
| #define | I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818)) |
| #define | I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C)) |
| #define | I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820)) |
| #define | I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000)) |
| #define | I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004)) |
| #define | I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008)) |
| #define | I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C)) |
| #define | I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010)) |
| #define | I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014)) |
| #define | I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018)) |
| #define | I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C)) |
| #define | I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020)) |
| #define | I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024)) |
| #define | I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C)) |
| #define | I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800)) |
| #define | I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804)) |
| #define | I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808)) |
| #define | I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C)) |
| #define | I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810)) |
| #define | I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814)) |
| #define | I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818)) |
| #define | I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C)) |
| #define | I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820)) |
| #define | I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000)) |
| #define | I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004)) |
| #define | I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008)) |
| #define | I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C)) |
| #define | I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010)) |
| #define | I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014)) |
| #define | I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018)) |
| #define | I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C)) |
| #define | I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020)) |
| #define | I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024)) |
| #define | I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C)) |
| #define | I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800)) |
| #define | I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804)) |
| #define | I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808)) |
| #define | I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C)) |
| #define | I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810)) |
| #define | I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814)) |
| #define | I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818)) |
| #define | I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C)) |
| #define | I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820)) |
| #define | I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000)) |
| #define | I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004)) |
| #define | I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008)) |
| #define | I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C)) |
| #define | I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010)) |
| #define | I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014)) |
| #define | I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018)) |
| #define | I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C)) |
| #define | I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020)) |
| #define | I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024)) |
| #define | I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C)) |
| #define | I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800)) |
| #define | I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804)) |
| #define | I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808)) |
| #define | I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C)) |
| #define | I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810)) |
| #define | I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814)) |
| #define | I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818)) |
| #define | I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C)) |
| #define | I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820)) |
| #define | GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000) |
| #define | GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC)) |
| #define | GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400)) |
| #define | GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404)) |
| #define | GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408)) |
| #define | GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C)) |
| #define | GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410)) |
| #define | GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414)) |
| #define | GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418)) |
| #define | GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C)) |
| #define | GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420)) |
| #define | GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500)) |
| #define | GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504)) |
| #define | GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508)) |
| #define | GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C)) |
| #define | GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510)) |
| #define | GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514)) |
| #define | GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518)) |
| #define | GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C)) |
| #define | GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520)) |
| #define | GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524)) |
| #define | GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528)) |
| #define | GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C)) |
| #define | GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530)) |
| #define | GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534)) |
| #define | GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538)) |
| #define | GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000) |
| #define | GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC)) |
| #define | GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400)) |
| #define | GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404)) |
| #define | GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408)) |
| #define | GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C)) |
| #define | GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410)) |
| #define | GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414)) |
| #define | GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418)) |
| #define | GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C)) |
| #define | GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420)) |
| #define | GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500)) |
| #define | GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504)) |
| #define | GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508)) |
| #define | GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C)) |
| #define | GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510)) |
| #define | GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514)) |
| #define | GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518)) |
| #define | GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C)) |
| #define | GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520)) |
| #define | GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524)) |
| #define | GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528)) |
| #define | GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C)) |
| #define | GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530)) |
| #define | GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534)) |
| #define | GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538)) |
| #define | TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) |
| #define | TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) |
| #define | TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008)) |
| #define | TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) |
| #define | TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010)) |
| #define | TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) |
| #define | TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C)) |
| #define | TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) |
| #define | TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) |
| #define | TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) |
| #define | TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C)) |
| #define | TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030)) |
| #define | TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034)) |
| #define | TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) |
| #define | TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C)) |
| #define | TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040)) |
| #define | TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044)) |
| #define | TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) |
| #define | TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C)) |
| #define | TIMER0_TAV_R (*((volatile unsigned long *)0x40030050)) |
| #define | TIMER0_TBV_R (*((volatile unsigned long *)0x40030054)) |
| #define | TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058)) |
| #define | TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C)) |
| #define | TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060)) |
| #define | TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064)) |
| #define | TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068)) |
| #define | TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0)) |
| #define | TIMER1_CFG_R (*((volatile unsigned long *)0x40031000)) |
| #define | TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004)) |
| #define | TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008)) |
| #define | TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C)) |
| #define | TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010)) |
| #define | TIMER1_IMR_R (*((volatile unsigned long *)0x40031018)) |
| #define | TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C)) |
| #define | TIMER1_MIS_R (*((volatile unsigned long *)0x40031020)) |
| #define | TIMER1_ICR_R (*((volatile unsigned long *)0x40031024)) |
| #define | TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028)) |
| #define | TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C)) |
| #define | TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030)) |
| #define | TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034)) |
| #define | TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038)) |
| #define | TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C)) |
| #define | TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040)) |
| #define | TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044)) |
| #define | TIMER1_TAR_R (*((volatile unsigned long *)0x40031048)) |
| #define | TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C)) |
| #define | TIMER1_TAV_R (*((volatile unsigned long *)0x40031050)) |
| #define | TIMER1_TBV_R (*((volatile unsigned long *)0x40031054)) |
| #define | TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058)) |
| #define | TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C)) |
| #define | TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060)) |
| #define | TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064)) |
| #define | TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068)) |
| #define | TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0)) |
| #define | TIMER2_CFG_R (*((volatile unsigned long *)0x40032000)) |
| #define | TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004)) |
| #define | TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008)) |
| #define | TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C)) |
| #define | TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010)) |
| #define | TIMER2_IMR_R (*((volatile unsigned long *)0x40032018)) |
| #define | TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C)) |
| #define | TIMER2_MIS_R (*((volatile unsigned long *)0x40032020)) |
| #define | TIMER2_ICR_R (*((volatile unsigned long *)0x40032024)) |
| #define | TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028)) |
| #define | TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C)) |
| #define | TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030)) |
| #define | TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034)) |
| #define | TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038)) |
| #define | TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C)) |
| #define | TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040)) |
| #define | TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044)) |
| #define | TIMER2_TAR_R (*((volatile unsigned long *)0x40032048)) |
| #define | TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C)) |
| #define | TIMER2_TAV_R (*((volatile unsigned long *)0x40032050)) |
| #define | TIMER2_TBV_R (*((volatile unsigned long *)0x40032054)) |
| #define | TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058)) |
| #define | TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C)) |
| #define | TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060)) |
| #define | TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064)) |
| #define | TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068)) |
| #define | TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0)) |
| #define | TIMER3_CFG_R (*((volatile unsigned long *)0x40033000)) |
| #define | TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004)) |
| #define | TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008)) |
| #define | TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C)) |
| #define | TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010)) |
| #define | TIMER3_IMR_R (*((volatile unsigned long *)0x40033018)) |
| #define | TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C)) |
| #define | TIMER3_MIS_R (*((volatile unsigned long *)0x40033020)) |
| #define | TIMER3_ICR_R (*((volatile unsigned long *)0x40033024)) |
| #define | TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028)) |
| #define | TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C)) |
| #define | TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030)) |
| #define | TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034)) |
| #define | TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038)) |
| #define | TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C)) |
| #define | TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040)) |
| #define | TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044)) |
| #define | TIMER3_TAR_R (*((volatile unsigned long *)0x40033048)) |
| #define | TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C)) |
| #define | TIMER3_TAV_R (*((volatile unsigned long *)0x40033050)) |
| #define | TIMER3_TBV_R (*((volatile unsigned long *)0x40033054)) |
| #define | TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058)) |
| #define | TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C)) |
| #define | TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060)) |
| #define | TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064)) |
| #define | TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068)) |
| #define | TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0)) |
| #define | TIMER4_CFG_R (*((volatile unsigned long *)0x40034000)) |
| #define | TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004)) |
| #define | TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008)) |
| #define | TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C)) |
| #define | TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010)) |
| #define | TIMER4_IMR_R (*((volatile unsigned long *)0x40034018)) |
| #define | TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C)) |
| #define | TIMER4_MIS_R (*((volatile unsigned long *)0x40034020)) |
| #define | TIMER4_ICR_R (*((volatile unsigned long *)0x40034024)) |
| #define | TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028)) |
| #define | TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C)) |
| #define | TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030)) |
| #define | TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034)) |
| #define | TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038)) |
| #define | TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C)) |
| #define | TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040)) |
| #define | TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044)) |
| #define | TIMER4_TAR_R (*((volatile unsigned long *)0x40034048)) |
| #define | TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C)) |
| #define | TIMER4_TAV_R (*((volatile unsigned long *)0x40034050)) |
| #define | TIMER4_TBV_R (*((volatile unsigned long *)0x40034054)) |
| #define | TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058)) |
| #define | TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C)) |
| #define | TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060)) |
| #define | TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064)) |
| #define | TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068)) |
| #define | TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0)) |
| #define | TIMER5_CFG_R (*((volatile unsigned long *)0x40035000)) |
| #define | TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004)) |
| #define | TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008)) |
| #define | TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C)) |
| #define | TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010)) |
| #define | TIMER5_IMR_R (*((volatile unsigned long *)0x40035018)) |
| #define | TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C)) |
| #define | TIMER5_MIS_R (*((volatile unsigned long *)0x40035020)) |
| #define | TIMER5_ICR_R (*((volatile unsigned long *)0x40035024)) |
| #define | TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028)) |
| #define | TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C)) |
| #define | TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030)) |
| #define | TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034)) |
| #define | TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038)) |
| #define | TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C)) |
| #define | TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040)) |
| #define | TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044)) |
| #define | TIMER5_TAR_R (*((volatile unsigned long *)0x40035048)) |
| #define | TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C)) |
| #define | TIMER5_TAV_R (*((volatile unsigned long *)0x40035050)) |
| #define | TIMER5_TBV_R (*((volatile unsigned long *)0x40035054)) |
| #define | TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058)) |
| #define | TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C)) |
| #define | TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060)) |
| #define | TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064)) |
| #define | TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068)) |
| #define | TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0)) |
| #define | WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000)) |
| #define | WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004)) |
| #define | WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008)) |
| #define | WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C)) |
| #define | WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010)) |
| #define | WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018)) |
| #define | WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C)) |
| #define | WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020)) |
| #define | WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024)) |
| #define | WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028)) |
| #define | WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C)) |
| #define | WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030)) |
| #define | WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034)) |
| #define | WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038)) |
| #define | WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C)) |
| #define | WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040)) |
| #define | WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044)) |
| #define | WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048)) |
| #define | WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C)) |
| #define | WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050)) |
| #define | WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054)) |
| #define | WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058)) |
| #define | WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C)) |
| #define | WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060)) |
| #define | WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064)) |
| #define | WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068)) |
| #define | WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0)) |
| #define | WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000)) |
| #define | WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004)) |
| #define | WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008)) |
| #define | WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C)) |
| #define | WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010)) |
| #define | WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018)) |
| #define | WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C)) |
| #define | WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020)) |
| #define | WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024)) |
| #define | WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028)) |
| #define | WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C)) |
| #define | WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030)) |
| #define | WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034)) |
| #define | WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038)) |
| #define | WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C)) |
| #define | WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040)) |
| #define | WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044)) |
| #define | WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048)) |
| #define | WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C)) |
| #define | WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050)) |
| #define | WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054)) |
| #define | WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058)) |
| #define | WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C)) |
| #define | WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060)) |
| #define | WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064)) |
| #define | WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068)) |
| #define | WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0)) |
| #define | ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000)) |
| #define | ADC0_RIS_R (*((volatile unsigned long *)0x40038004)) |
| #define | ADC0_IM_R (*((volatile unsigned long *)0x40038008)) |
| #define | ADC0_ISC_R (*((volatile unsigned long *)0x4003800C)) |
| #define | ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010)) |
| #define | ADC0_EMUX_R (*((volatile unsigned long *)0x40038014)) |
| #define | ADC0_USTAT_R (*((volatile unsigned long *)0x40038018)) |
| #define | ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020)) |
| #define | ADC0_SPC_R (*((volatile unsigned long *)0x40038024)) |
| #define | ADC0_PSSI_R (*((volatile unsigned long *)0x40038028)) |
| #define | ADC0_SAC_R (*((volatile unsigned long *)0x40038030)) |
| #define | ADC0_DCISC_R (*((volatile unsigned long *)0x40038034)) |
| #define | ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040)) |
| #define | ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044)) |
| #define | ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) |
| #define | ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) |
| #define | ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050)) |
| #define | ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054)) |
| #define | ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060)) |
| #define | ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064)) |
| #define | ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) |
| #define | ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) |
| #define | ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070)) |
| #define | ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074)) |
| #define | ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080)) |
| #define | ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084)) |
| #define | ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) |
| #define | ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) |
| #define | ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090)) |
| #define | ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094)) |
| #define | ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) |
| #define | ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) |
| #define | ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) |
| #define | ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) |
| #define | ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0)) |
| #define | ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4)) |
| #define | ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00)) |
| #define | ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00)) |
| #define | ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04)) |
| #define | ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08)) |
| #define | ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C)) |
| #define | ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10)) |
| #define | ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14)) |
| #define | ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18)) |
| #define | ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C)) |
| #define | ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40)) |
| #define | ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44)) |
| #define | ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48)) |
| #define | ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C)) |
| #define | ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50)) |
| #define | ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54)) |
| #define | ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58)) |
| #define | ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C)) |
| #define | ADC0_PP_R (*((volatile unsigned long *)0x40038FC0)) |
| #define | ADC0_PC_R (*((volatile unsigned long *)0x40038FC4)) |
| #define | ADC0_CC_R (*((volatile unsigned long *)0x40038FC8)) |
| #define | ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000)) |
| #define | ADC1_RIS_R (*((volatile unsigned long *)0x40039004)) |
| #define | ADC1_IM_R (*((volatile unsigned long *)0x40039008)) |
| #define | ADC1_ISC_R (*((volatile unsigned long *)0x4003900C)) |
| #define | ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010)) |
| #define | ADC1_EMUX_R (*((volatile unsigned long *)0x40039014)) |
| #define | ADC1_USTAT_R (*((volatile unsigned long *)0x40039018)) |
| #define | ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020)) |
| #define | ADC1_SPC_R (*((volatile unsigned long *)0x40039024)) |
| #define | ADC1_PSSI_R (*((volatile unsigned long *)0x40039028)) |
| #define | ADC1_SAC_R (*((volatile unsigned long *)0x40039030)) |
| #define | ADC1_DCISC_R (*((volatile unsigned long *)0x40039034)) |
| #define | ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040)) |
| #define | ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044)) |
| #define | ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048)) |
| #define | ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C)) |
| #define | ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050)) |
| #define | ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054)) |
| #define | ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060)) |
| #define | ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064)) |
| #define | ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068)) |
| #define | ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C)) |
| #define | ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070)) |
| #define | ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074)) |
| #define | ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080)) |
| #define | ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084)) |
| #define | ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088)) |
| #define | ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C)) |
| #define | ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090)) |
| #define | ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094)) |
| #define | ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0)) |
| #define | ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4)) |
| #define | ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8)) |
| #define | ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC)) |
| #define | ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0)) |
| #define | ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4)) |
| #define | ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00)) |
| #define | ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00)) |
| #define | ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04)) |
| #define | ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08)) |
| #define | ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C)) |
| #define | ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10)) |
| #define | ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14)) |
| #define | ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18)) |
| #define | ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C)) |
| #define | ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40)) |
| #define | ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44)) |
| #define | ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48)) |
| #define | ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C)) |
| #define | ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50)) |
| #define | ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54)) |
| #define | ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58)) |
| #define | ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C)) |
| #define | ADC1_PP_R (*((volatile unsigned long *)0x40039FC0)) |
| #define | ADC1_PC_R (*((volatile unsigned long *)0x40039FC4)) |
| #define | ADC1_CC_R (*((volatile unsigned long *)0x40039FC8)) |
| #define | COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000)) |
| #define | COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004)) |
| #define | COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008)) |
| #define | COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010)) |
| #define | COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020)) |
| #define | COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024)) |
| #define | COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040)) |
| #define | COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044)) |
| #define | COMP_PP_R (*((volatile unsigned long *)0x4003CFC0)) |
| #define | CAN0_CTL_R (*((volatile unsigned long *)0x40040000)) |
| #define | CAN0_STS_R (*((volatile unsigned long *)0x40040004)) |
| #define | CAN0_ERR_R (*((volatile unsigned long *)0x40040008)) |
| #define | CAN0_BIT_R (*((volatile unsigned long *)0x4004000C)) |
| #define | CAN0_INT_R (*((volatile unsigned long *)0x40040010)) |
| #define | CAN0_TST_R (*((volatile unsigned long *)0x40040014)) |
| #define | CAN0_BRPE_R (*((volatile unsigned long *)0x40040018)) |
| #define | CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020)) |
| #define | CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024)) |
| #define | CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028)) |
| #define | CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C)) |
| #define | CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030)) |
| #define | CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034)) |
| #define | CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038)) |
| #define | CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C)) |
| #define | CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040)) |
| #define | CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044)) |
| #define | CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048)) |
| #define | CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080)) |
| #define | CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084)) |
| #define | CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088)) |
| #define | CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C)) |
| #define | CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090)) |
| #define | CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094)) |
| #define | CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098)) |
| #define | CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C)) |
| #define | CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0)) |
| #define | CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4)) |
| #define | CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8)) |
| #define | CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100)) |
| #define | CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104)) |
| #define | CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120)) |
| #define | CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124)) |
| #define | CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140)) |
| #define | CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144)) |
| #define | CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160)) |
| #define | CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164)) |
| #define | WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000)) |
| #define | WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004)) |
| #define | WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008)) |
| #define | WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C)) |
| #define | WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010)) |
| #define | WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018)) |
| #define | WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C)) |
| #define | WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020)) |
| #define | WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024)) |
| #define | WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028)) |
| #define | WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C)) |
| #define | WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030)) |
| #define | WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034)) |
| #define | WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038)) |
| #define | WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C)) |
| #define | WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040)) |
| #define | WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044)) |
| #define | WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048)) |
| #define | WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C)) |
| #define | WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050)) |
| #define | WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054)) |
| #define | WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058)) |
| #define | WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C)) |
| #define | WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060)) |
| #define | WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064)) |
| #define | WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068)) |
| #define | WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0)) |
| #define | WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000)) |
| #define | WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004)) |
| #define | WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008)) |
| #define | WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C)) |
| #define | WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010)) |
| #define | WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018)) |
| #define | WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C)) |
| #define | WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020)) |
| #define | WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024)) |
| #define | WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028)) |
| #define | WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C)) |
| #define | WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030)) |
| #define | WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034)) |
| #define | WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038)) |
| #define | WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C)) |
| #define | WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040)) |
| #define | WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044)) |
| #define | WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048)) |
| #define | WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C)) |
| #define | WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050)) |
| #define | WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054)) |
| #define | WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058)) |
| #define | WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C)) |
| #define | WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060)) |
| #define | WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064)) |
| #define | WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068)) |
| #define | WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0)) |
| #define | WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000)) |
| #define | WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004)) |
| #define | WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008)) |
| #define | WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C)) |
| #define | WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010)) |
| #define | WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018)) |
| #define | WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C)) |
| #define | WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020)) |
| #define | WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024)) |
| #define | WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028)) |
| #define | WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C)) |
| #define | WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030)) |
| #define | WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034)) |
| #define | WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038)) |
| #define | WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C)) |
| #define | WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040)) |
| #define | WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044)) |
| #define | WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048)) |
| #define | WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C)) |
| #define | WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050)) |
| #define | WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054)) |
| #define | WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058)) |
| #define | WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C)) |
| #define | WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060)) |
| #define | WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064)) |
| #define | WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068)) |
| #define | WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0)) |
| #define | WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000)) |
| #define | WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004)) |
| #define | WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008)) |
| #define | WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C)) |
| #define | WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010)) |
| #define | WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018)) |
| #define | WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C)) |
| #define | WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020)) |
| #define | WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024)) |
| #define | WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028)) |
| #define | WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C)) |
| #define | WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030)) |
| #define | WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034)) |
| #define | WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038)) |
| #define | WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C)) |
| #define | WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040)) |
| #define | WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044)) |
| #define | WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048)) |
| #define | WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C)) |
| #define | WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050)) |
| #define | WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054)) |
| #define | WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058)) |
| #define | WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C)) |
| #define | WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060)) |
| #define | WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064)) |
| #define | WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068)) |
| #define | WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0)) |
| #define | USB0_FADDR_R (*((volatile unsigned char *)0x40050000)) |
| #define | USB0_POWER_R (*((volatile unsigned char *)0x40050001)) |
| #define | USB0_TXIS_R (*((volatile unsigned short *)0x40050002)) |
| #define | USB0_RXIS_R (*((volatile unsigned short *)0x40050004)) |
| #define | USB0_TXIE_R (*((volatile unsigned short *)0x40050006)) |
| #define | USB0_RXIE_R (*((volatile unsigned short *)0x40050008)) |
| #define | USB0_IS_R (*((volatile unsigned char *)0x4005000A)) |
| #define | USB0_IE_R (*((volatile unsigned char *)0x4005000B)) |
| #define | USB0_FRAME_R (*((volatile unsigned short *)0x4005000C)) |
| #define | USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E)) |
| #define | USB0_TEST_R (*((volatile unsigned char *)0x4005000F)) |
| #define | USB0_FIFO0_R (*((volatile unsigned long *)0x40050020)) |
| #define | USB0_FIFO1_R (*((volatile unsigned long *)0x40050024)) |
| #define | USB0_FIFO2_R (*((volatile unsigned long *)0x40050028)) |
| #define | USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C)) |
| #define | USB0_FIFO4_R (*((volatile unsigned long *)0x40050030)) |
| #define | USB0_FIFO5_R (*((volatile unsigned long *)0x40050034)) |
| #define | USB0_FIFO6_R (*((volatile unsigned long *)0x40050038)) |
| #define | USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C)) |
| #define | USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062)) |
| #define | USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063)) |
| #define | USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064)) |
| #define | USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066)) |
| #define | USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A)) |
| #define | USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D)) |
| #define | USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E)) |
| #define | USB0_CSRL0_R (*((volatile unsigned char *)0x40050102)) |
| #define | USB0_CSRH0_R (*((volatile unsigned char *)0x40050103)) |
| #define | USB0_COUNT0_R (*((volatile unsigned char *)0x40050108)) |
| #define | USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110)) |
| #define | USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112)) |
| #define | USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113)) |
| #define | USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114)) |
| #define | USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116)) |
| #define | USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117)) |
| #define | USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118)) |
| #define | USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120)) |
| #define | USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122)) |
| #define | USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123)) |
| #define | USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124)) |
| #define | USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126)) |
| #define | USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127)) |
| #define | USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128)) |
| #define | USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130)) |
| #define | USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132)) |
| #define | USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133)) |
| #define | USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134)) |
| #define | USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136)) |
| #define | USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137)) |
| #define | USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138)) |
| #define | USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140)) |
| #define | USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142)) |
| #define | USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143)) |
| #define | USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144)) |
| #define | USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146)) |
| #define | USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147)) |
| #define | USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148)) |
| #define | USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150)) |
| #define | USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152)) |
| #define | USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153)) |
| #define | USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154)) |
| #define | USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156)) |
| #define | USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157)) |
| #define | USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158)) |
| #define | USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160)) |
| #define | USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162)) |
| #define | USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163)) |
| #define | USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164)) |
| #define | USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166)) |
| #define | USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167)) |
| #define | USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168)) |
| #define | USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170)) |
| #define | USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172)) |
| #define | USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173)) |
| #define | USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174)) |
| #define | USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176)) |
| #define | USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177)) |
| #define | USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178)) |
| #define | USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340)) |
| #define | USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342)) |
| #define | USB0_DRRIS_R (*((volatile unsigned long *)0x40050410)) |
| #define | USB0_DRIM_R (*((volatile unsigned long *)0x40050414)) |
| #define | USB0_DRISC_R (*((volatile unsigned long *)0x40050418)) |
| #define | USB0_DMASEL_R (*((volatile unsigned long *)0x40050450)) |
| #define | USB0_PP_R (*((volatile unsigned long *)0x40050FC0)) |
| #define | GPIO_PORTA_AHB_DATA_BITS_R ((volatile unsigned long *)0x40058000) |
| #define | GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC)) |
| #define | GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400)) |
| #define | GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404)) |
| #define | GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408)) |
| #define | GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C)) |
| #define | GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410)) |
| #define | GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414)) |
| #define | GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418)) |
| #define | GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C)) |
| #define | GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420)) |
| #define | GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500)) |
| #define | GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504)) |
| #define | GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508)) |
| #define | GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C)) |
| #define | GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510)) |
| #define | GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514)) |
| #define | GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518)) |
| #define | GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C)) |
| #define | GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520)) |
| #define | GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524)) |
| #define | GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528)) |
| #define | GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C)) |
| #define | GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530)) |
| #define | GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534)) |
| #define | GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538)) |
| #define | GPIO_PORTB_AHB_DATA_BITS_R ((volatile unsigned long *)0x40059000) |
| #define | GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC)) |
| #define | GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400)) |
| #define | GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404)) |
| #define | GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408)) |
| #define | GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C)) |
| #define | GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410)) |
| #define | GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414)) |
| #define | GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418)) |
| #define | GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C)) |
| #define | GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420)) |
| #define | GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500)) |
| #define | GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504)) |
| #define | GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508)) |
| #define | GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C)) |
| #define | GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510)) |
| #define | GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514)) |
| #define | GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518)) |
| #define | GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C)) |
| #define | GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520)) |
| #define | GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524)) |
| #define | GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528)) |
| #define | GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C)) |
| #define | GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530)) |
| #define | GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534)) |
| #define | GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538)) |
| #define | GPIO_PORTC_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005A000) |
| #define | GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC)) |
| #define | GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400)) |
| #define | GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404)) |
| #define | GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408)) |
| #define | GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C)) |
| #define | GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410)) |
| #define | GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414)) |
| #define | GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418)) |
| #define | GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C)) |
| #define | GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420)) |
| #define | GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500)) |
| #define | GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504)) |
| #define | GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508)) |
| #define | GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C)) |
| #define | GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510)) |
| #define | GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514)) |
| #define | GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518)) |
| #define | GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C)) |
| #define | GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520)) |
| #define | GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524)) |
| #define | GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528)) |
| #define | GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C)) |
| #define | GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530)) |
| #define | GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534)) |
| #define | GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538)) |
| #define | GPIO_PORTD_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005B000) |
| #define | GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC)) |
| #define | GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400)) |
| #define | GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404)) |
| #define | GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408)) |
| #define | GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C)) |
| #define | GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410)) |
| #define | GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414)) |
| #define | GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418)) |
| #define | GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C)) |
| #define | GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420)) |
| #define | GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500)) |
| #define | GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504)) |
| #define | GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508)) |
| #define | GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C)) |
| #define | GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510)) |
| #define | GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514)) |
| #define | GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518)) |
| #define | GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C)) |
| #define | GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520)) |
| #define | GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524)) |
| #define | GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528)) |
| #define | GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C)) |
| #define | GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530)) |
| #define | GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534)) |
| #define | GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538)) |
| #define | GPIO_PORTE_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005C000) |
| #define | GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC)) |
| #define | GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400)) |
| #define | GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404)) |
| #define | GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408)) |
| #define | GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C)) |
| #define | GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410)) |
| #define | GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414)) |
| #define | GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418)) |
| #define | GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C)) |
| #define | GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420)) |
| #define | GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500)) |
| #define | GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504)) |
| #define | GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508)) |
| #define | GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C)) |
| #define | GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510)) |
| #define | GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514)) |
| #define | GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518)) |
| #define | GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C)) |
| #define | GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520)) |
| #define | GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524)) |
| #define | GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528)) |
| #define | GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C)) |
| #define | GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530)) |
| #define | GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534)) |
| #define | GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538)) |
| #define | GPIO_PORTF_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005D000) |
| #define | GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC)) |
| #define | GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400)) |
| #define | GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404)) |
| #define | GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408)) |
| #define | GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C)) |
| #define | GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410)) |
| #define | GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414)) |
| #define | GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418)) |
| #define | GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C)) |
| #define | GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420)) |
| #define | GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500)) |
| #define | GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504)) |
| #define | GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508)) |
| #define | GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C)) |
| #define | GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510)) |
| #define | GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514)) |
| #define | GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518)) |
| #define | GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C)) |
| #define | GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520)) |
| #define | GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524)) |
| #define | GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528)) |
| #define | GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C)) |
| #define | GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530)) |
| #define | GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534)) |
| #define | GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538)) |
| #define | EEPROM_EESIZE_R (*((volatile unsigned long *)0x400AF000)) |
| #define | EEPROM_EEBLOCK_R (*((volatile unsigned long *)0x400AF004)) |
| #define | EEPROM_EEOFFSET_R (*((volatile unsigned long *)0x400AF008)) |
| #define | EEPROM_EERDWR_R (*((volatile unsigned long *)0x400AF010)) |
| #define | EEPROM_EERDWRINC_R (*((volatile unsigned long *)0x400AF014)) |
| #define | EEPROM_EEDONE_R (*((volatile unsigned long *)0x400AF018)) |
| #define | EEPROM_EESUPP_R (*((volatile unsigned long *)0x400AF01C)) |
| #define | EEPROM_EEUNLOCK_R (*((volatile unsigned long *)0x400AF020)) |
| #define | EEPROM_EEPROT_R (*((volatile unsigned long *)0x400AF030)) |
| #define | EEPROM_EEPASS0_R (*((volatile unsigned long *)0x400AF034)) |
| #define | EEPROM_EEPASS1_R (*((volatile unsigned long *)0x400AF038)) |
| #define | EEPROM_EEPASS2_R (*((volatile unsigned long *)0x400AF03C)) |
| #define | EEPROM_EEINT_R (*((volatile unsigned long *)0x400AF040)) |
| #define | EEPROM_EEHIDE_R (*((volatile unsigned long *)0x400AF050)) |
| #define | EEPROM_EEDBGME_R (*((volatile unsigned long *)0x400AF080)) |
| #define | EEPROM_PP_R (*((volatile unsigned long *)0x400AFFC0)) |
| #define | SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000)) |
| #define | SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004)) |
| #define | SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008)) |
| #define | SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C)) |
| #define | HIB_RTCC_R (*((volatile unsigned long *)0x400FC000)) |
| #define | HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004)) |
| #define | HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C)) |
| #define | HIB_CTL_R (*((volatile unsigned long *)0x400FC010)) |
| #define | HIB_IM_R (*((volatile unsigned long *)0x400FC014)) |
| #define | HIB_RIS_R (*((volatile unsigned long *)0x400FC018)) |
| #define | HIB_MIS_R (*((volatile unsigned long *)0x400FC01C)) |
| #define | HIB_IC_R (*((volatile unsigned long *)0x400FC020)) |
| #define | HIB_RTCT_R (*((volatile unsigned long *)0x400FC024)) |
| #define | HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028)) |
| #define | HIB_DATA_R (*((volatile unsigned long *)0x400FC030)) |
| #define | FLASH_FMA_R (*((volatile unsigned long *)0x400FD000)) |
| #define | FLASH_FMD_R (*((volatile unsigned long *)0x400FD004)) |
| #define | FLASH_FMC_R (*((volatile unsigned long *)0x400FD008)) |
| #define | FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C)) |
| #define | FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010)) |
| #define | FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014)) |
| #define | FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020)) |
| #define | FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030)) |
| #define | FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100)) |
| #define | FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0)) |
| #define | FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4)) |
| #define | FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC)) |
| #define | FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0)) |
| #define | FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0)) |
| #define | FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0)) |
| #define | FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4)) |
| #define | FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8)) |
| #define | FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC)) |
| #define | FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200)) |
| #define | FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204)) |
| #define | FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208)) |
| #define | FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C)) |
| #define | FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400)) |
| #define | FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404)) |
| #define | FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408)) |
| #define | FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C)) |
| #define | SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000)) |
| #define | SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004)) |
| #define | SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008)) |
| #define | SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010)) |
| #define | SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014)) |
| #define | SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018)) |
| #define | SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C)) |
| #define | SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020)) |
| #define | SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024)) |
| #define | SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028)) |
| #define | SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C)) |
| #define | SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030)) |
| #define | SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040)) |
| #define | SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044)) |
| #define | SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048)) |
| #define | SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050)) |
| #define | SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054)) |
| #define | SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058)) |
| #define | SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C)) |
| #define | SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060)) |
| #define | SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C)) |
| #define | SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070)) |
| #define | SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C)) |
| #define | SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100)) |
| #define | SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) |
| #define | SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108)) |
| #define | SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110)) |
| #define | SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114)) |
| #define | SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118)) |
| #define | SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120)) |
| #define | SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124)) |
| #define | SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128)) |
| #define | SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144)) |
| #define | SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C)) |
| #define | SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150)) |
| #define | SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154)) |
| #define | SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160)) |
| #define | SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164)) |
| #define | SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168)) |
| #define | SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190)) |
| #define | SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0)) |
| #define | SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300)) |
| #define | SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304)) |
| #define | SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308)) |
| #define | SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C)) |
| #define | SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314)) |
| #define | SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318)) |
| #define | SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C)) |
| #define | SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320)) |
| #define | SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328)) |
| #define | SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334)) |
| #define | SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338)) |
| #define | SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C)) |
| #define | SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340)) |
| #define | SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344)) |
| #define | SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358)) |
| #define | SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C)) |
| #define | SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500)) |
| #define | SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504)) |
| #define | SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508)) |
| #define | SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C)) |
| #define | SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514)) |
| #define | SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518)) |
| #define | SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C)) |
| #define | SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520)) |
| #define | SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528)) |
| #define | SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534)) |
| #define | SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538)) |
| #define | SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C)) |
| #define | SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558)) |
| #define | SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C)) |
| #define | SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600)) |
| #define | SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604)) |
| #define | SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608)) |
| #define | SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C)) |
| #define | SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614)) |
| #define | SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618)) |
| #define | SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C)) |
| #define | SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620)) |
| #define | SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628)) |
| #define | SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634)) |
| #define | SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638)) |
| #define | SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C)) |
| #define | SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658)) |
| #define | SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C)) |
| #define | SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700)) |
| #define | SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704)) |
| #define | SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708)) |
| #define | SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C)) |
| #define | SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714)) |
| #define | SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718)) |
| #define | SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C)) |
| #define | SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720)) |
| #define | SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728)) |
| #define | SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734)) |
| #define | SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738)) |
| #define | SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C)) |
| #define | SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758)) |
| #define | SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C)) |
| #define | SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800)) |
| #define | SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804)) |
| #define | SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808)) |
| #define | SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C)) |
| #define | SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814)) |
| #define | SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818)) |
| #define | SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C)) |
| #define | SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820)) |
| #define | SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828)) |
| #define | SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834)) |
| #define | SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838)) |
| #define | SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C)) |
| #define | SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858)) |
| #define | SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C)) |
| #define | SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900)) |
| #define | SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904)) |
| #define | SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908)) |
| #define | SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C)) |
| #define | SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914)) |
| #define | SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918)) |
| #define | SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C)) |
| #define | SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920)) |
| #define | SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928)) |
| #define | SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934)) |
| #define | SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938)) |
| #define | SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C)) |
| #define | SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958)) |
| #define | SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C)) |
| #define | SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00)) |
| #define | SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04)) |
| #define | SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08)) |
| #define | SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C)) |
| #define | SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14)) |
| #define | SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18)) |
| #define | SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C)) |
| #define | SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20)) |
| #define | SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28)) |
| #define | SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34)) |
| #define | SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38)) |
| #define | SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C)) |
| #define | SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58)) |
| #define | SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C)) |
| #define | UDMA_STAT_R (*((volatile unsigned long *)0x400FF000)) |
| #define | UDMA_CFG_R (*((volatile unsigned long *)0x400FF004)) |
| #define | UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008)) |
| #define | UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C)) |
| #define | UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010)) |
| #define | UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014)) |
| #define | UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018)) |
| #define | UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C)) |
| #define | UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020)) |
| #define | UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024)) |
| #define | UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028)) |
| #define | UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C)) |
| #define | UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030)) |
| #define | UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034)) |
| #define | UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038)) |
| #define | UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C)) |
| #define | UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C)) |
| #define | UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500)) |
| #define | UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504)) |
| #define | UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510)) |
| #define | UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514)) |
| #define | UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518)) |
| #define | UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C)) |
| #define | UDMA_SRCENDP 0x00000000 |
| #define | UDMA_DSTENDP 0x00000004 |
| #define | UDMA_CHCTL 0x00000008 |
| #define | NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004)) |
| #define | NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008)) |
| #define | NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010)) |
| #define | NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014)) |
| #define | NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018)) |
| #define | NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C)) |
| #define | NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) |
| #define | NVIC_EN1_R (*((volatile unsigned long *)0xE000E104)) |
| #define | NVIC_EN2_R (*((volatile unsigned long *)0xE000E108)) |
| #define | NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C)) |
| #define | NVIC_EN4_R (*((volatile unsigned long *)0xE000E110)) |
| #define | NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180)) |
| #define | NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184)) |
| #define | NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188)) |
| #define | NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C)) |
| #define | NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190)) |
| #define | NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200)) |
| #define | NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204)) |
| #define | NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208)) |
| #define | NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C)) |
| #define | NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210)) |
| #define | NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280)) |
| #define | NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284)) |
| #define | NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288)) |
| #define | NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C)) |
| #define | NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290)) |
| #define | NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300)) |
| #define | NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304)) |
| #define | NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308)) |
| #define | NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C)) |
| #define | NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310)) |
| #define | NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) |
| #define | NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404)) |
| #define | NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408)) |
| #define | NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C)) |
| #define | NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) |
| #define | NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414)) |
| #define | NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418)) |
| #define | NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C)) |
| #define | NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420)) |
| #define | NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424)) |
| #define | NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428)) |
| #define | NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C)) |
| #define | NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430)) |
| #define | NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434)) |
| #define | NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438)) |
| #define | NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C)) |
| #define | NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440)) |
| #define | NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444)) |
| #define | NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448)) |
| #define | NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C)) |
| #define | NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450)) |
| #define | NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454)) |
| #define | NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458)) |
| #define | NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C)) |
| #define | NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460)) |
| #define | NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464)) |
| #define | NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468)) |
| #define | NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C)) |
| #define | NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470)) |
| #define | NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474)) |
| #define | NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478)) |
| #define | NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C)) |
| #define | NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480)) |
| #define | NVIC_PRI33_R (*((volatile unsigned long *)0xE000E484)) |
| #define | NVIC_PRI34_R (*((volatile unsigned long *)0xE000E488)) |
| #define | NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00)) |
| #define | NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04)) |
| #define | NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08)) |
| #define | NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C)) |
| #define | NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10)) |
| #define | NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14)) |
| #define | NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18)) |
| #define | NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C)) |
| #define | NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20)) |
| #define | NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24)) |
| #define | NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28)) |
| #define | NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C)) |
| #define | NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30)) |
| #define | NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34)) |
| #define | NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38)) |
| #define | NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88)) |
| #define | NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90)) |
| #define | NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94)) |
| #define | NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98)) |
| #define | NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C)) |
| #define | NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0)) |
| #define | NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4)) |
| #define | NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8)) |
| #define | NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC)) |
| #define | NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0)) |
| #define | NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4)) |
| #define | NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8)) |
| #define | NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0)) |
| #define | NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4)) |
| #define | NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8)) |
| #define | NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC)) |
| #define | NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00)) |
| #define | NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34)) |
| #define | NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38)) |
| #define | NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C)) |
| #define | WDT_LOAD_M 0xFFFFFFFF |
| #define | WDT_LOAD_S 0 |
| #define | WDT_VALUE_M 0xFFFFFFFF |
| #define | WDT_VALUE_S 0 |
| #define | WDT_CTL_WRC 0x80000000 |
| #define | WDT_CTL_INTTYPE 0x00000004 |
| #define | WDT_CTL_RESEN 0x00000002 |
| #define | WDT_CTL_INTEN 0x00000001 |
| #define | WDT_ICR_M 0xFFFFFFFF |
| #define | WDT_ICR_S 0 |
| #define | WDT_RIS_WDTRIS 0x00000001 |
| #define | WDT_MIS_WDTMIS 0x00000001 |
| #define | WDT_TEST_STALL 0x00000100 |
| #define | WDT_LOCK_M 0xFFFFFFFF |
| #define | WDT_LOCK_UNLOCKED 0x00000000 |
| #define | WDT_LOCK_LOCKED 0x00000001 |
| #define | GPIO_IM_GPIO_M 0x000000FF |
| #define | GPIO_IM_GPIO_S 0 |
| #define | GPIO_RIS_GPIO_M 0x000000FF |
| #define | GPIO_RIS_GPIO_S 0 |
| #define | GPIO_MIS_GPIO_M 0x000000FF |
| #define | GPIO_MIS_GPIO_S 0 |
| #define | GPIO_ICR_GPIO_M 0x000000FF |
| #define | GPIO_ICR_GPIO_S 0 |
| #define | GPIO_LOCK_M 0xFFFFFFFF |
| #define | GPIO_LOCK_UNLOCKED 0x00000000 |
| #define | GPIO_LOCK_LOCKED 0x00000001 |
| #define | GPIO_LOCK_KEY 0x4C4F434B |
| #define | GPIO_SI_SUM 0x00000001 |
| #define | GPIO_PCTL_PA7_M 0xF0000000 |
| #define | GPIO_PCTL_PA7_I2C1SDA 0x30000000 |
| #define | GPIO_PCTL_PA6_M 0x0F000000 |
| #define | GPIO_PCTL_PA6_I2C1SCL 0x03000000 |
| #define | GPIO_PCTL_PA5_M 0x00F00000 |
| #define | GPIO_PCTL_PA5_SSI0TX 0x00200000 |
| #define | GPIO_PCTL_PA4_M 0x000F0000 |
| #define | GPIO_PCTL_PA4_SSI0RX 0x00020000 |
| #define | GPIO_PCTL_PA3_M 0x0000F000 |
| #define | GPIO_PCTL_PA3_SSI0FSS 0x00002000 |
| #define | GPIO_PCTL_PA2_M 0x00000F00 |
| #define | GPIO_PCTL_PA2_SSI0CLK 0x00000200 |
| #define | GPIO_PCTL_PA1_M 0x000000F0 |
| #define | GPIO_PCTL_PA1_U0TX 0x00000010 |
| #define | GPIO_PCTL_PA0_M 0x0000000F |
| #define | GPIO_PCTL_PA0_U0RX 0x00000001 |
| #define | GPIO_PCTL_PB7_M 0xF0000000 |
| #define | GPIO_PCTL_PB7_SSI2TX 0x20000000 |
| #define | GPIO_PCTL_PB7_T0CCP1 0x70000000 |
| #define | GPIO_PCTL_PB6_M 0x0F000000 |
| #define | GPIO_PCTL_PB6_SSI2RX 0x02000000 |
| #define | GPIO_PCTL_PB6_T0CCP0 0x07000000 |
| #define | GPIO_PCTL_PB5_M 0x00F00000 |
| #define | GPIO_PCTL_PB5_SSI2FSS 0x00200000 |
| #define | GPIO_PCTL_PB5_T1CCP1 0x00700000 |
| #define | GPIO_PCTL_PB5_CAN0TX 0x00800000 |
| #define | GPIO_PCTL_PB4_M 0x000F0000 |
| #define | GPIO_PCTL_PB4_SSI2CLK 0x00020000 |
| #define | GPIO_PCTL_PB4_T1CCP0 0x00070000 |
| #define | GPIO_PCTL_PB4_CAN0RX 0x00080000 |
| #define | GPIO_PCTL_PB3_M 0x0000F000 |
| #define | GPIO_PCTL_PB3_I2C0SDA 0x00003000 |
| #define | GPIO_PCTL_PB3_T3CCP1 0x00007000 |
| #define | GPIO_PCTL_PB2_M 0x00000F00 |
| #define | GPIO_PCTL_PB2_I2C0SCL 0x00000300 |
| #define | GPIO_PCTL_PB2_T3CCP0 0x00000700 |
| #define | GPIO_PCTL_PB1_M 0x000000F0 |
| #define | GPIO_PCTL_PB1_U1TX 0x00000010 |
| #define | GPIO_PCTL_PB1_T2CCP1 0x00000070 |
| #define | GPIO_PCTL_PB0_M 0x0000000F |
| #define | GPIO_PCTL_PB0_U1RX 0x00000001 |
| #define | GPIO_PCTL_PB0_T2CCP0 0x00000007 |
| #define | GPIO_PCTL_PC7_M 0xF0000000 |
| #define | GPIO_PCTL_PC7_U3TX 0x10000000 |
| #define | GPIO_PCTL_PC7_WT1CCP1 0x70000000 |
| #define | GPIO_PCTL_PC6_M 0x0F000000 |
| #define | GPIO_PCTL_PC6_U3RX 0x01000000 |
| #define | GPIO_PCTL_PC6_WT1CCP0 0x07000000 |
| #define | GPIO_PCTL_PC5_M 0x00F00000 |
| #define | GPIO_PCTL_PC5_U4TX 0x00100000 |
| #define | GPIO_PCTL_PC5_U1TX 0x00200000 |
| #define | GPIO_PCTL_PC5_WT0CCP1 0x00700000 |
| #define | GPIO_PCTL_PC5_U1CTS 0x00800000 |
| #define | GPIO_PCTL_PC4_M 0x000F0000 |
| #define | GPIO_PCTL_PC4_U4RX 0x00010000 |
| #define | GPIO_PCTL_PC4_U1RX 0x00020000 |
| #define | GPIO_PCTL_PC4_WT0CCP0 0x00070000 |
| #define | GPIO_PCTL_PC4_U1RTS 0x00080000 |
| #define | GPIO_PCTL_PC3_M 0x0000F000 |
| #define | GPIO_PCTL_PC3_TDO 0x00001000 |
| #define | GPIO_PCTL_PC3_T5CCP1 0x00007000 |
| #define | GPIO_PCTL_PC2_M 0x00000F00 |
| #define | GPIO_PCTL_PC2_TDI 0x00000100 |
| #define | GPIO_PCTL_PC2_T5CCP0 0x00000700 |
| #define | GPIO_PCTL_PC1_M 0x000000F0 |
| #define | GPIO_PCTL_PC1_TMS 0x00000010 |
| #define | GPIO_PCTL_PC1_T4CCP1 0x00000070 |
| #define | GPIO_PCTL_PC0_M 0x0000000F |
| #define | GPIO_PCTL_PC0_TCK 0x00000001 |
| #define | GPIO_PCTL_PC0_T4CCP0 0x00000007 |
| #define | GPIO_PCTL_PD7_M 0xF0000000 |
| #define | GPIO_PCTL_PD7_U2TX 0x10000000 |
| #define | GPIO_PCTL_PD7_WT5CCP1 0x70000000 |
| #define | GPIO_PCTL_PD7_NMI 0x80000000 |
| #define | GPIO_PCTL_PD6_M 0x0F000000 |
| #define | GPIO_PCTL_PD6_U2RX 0x01000000 |
| #define | GPIO_PCTL_PD6_WT5CCP0 0x07000000 |
| #define | GPIO_PCTL_PD5_M 0x00F00000 |
| #define | GPIO_PCTL_PD5_U6TX 0x00100000 |
| #define | GPIO_PCTL_PD5_WT4CCP1 0x00700000 |
| #define | GPIO_PCTL_PD4_M 0x000F0000 |
| #define | GPIO_PCTL_PD4_U6RX 0x00010000 |
| #define | GPIO_PCTL_PD4_WT4CCP0 0x00070000 |
| #define | GPIO_PCTL_PD3_M 0x0000F000 |
| #define | GPIO_PCTL_PD3_SSI3TX 0x00001000 |
| #define | GPIO_PCTL_PD3_SSI1TX 0x00002000 |
| #define | GPIO_PCTL_PD3_WT3CCP1 0x00007000 |
| #define | GPIO_PCTL_PD2_M 0x00000F00 |
| #define | GPIO_PCTL_PD2_SSI3RX 0x00000100 |
| #define | GPIO_PCTL_PD2_SSI1RX 0x00000200 |
| #define | GPIO_PCTL_PD2_WT3CCP0 0x00000700 |
| #define | GPIO_PCTL_PD1_M 0x000000F0 |
| #define | GPIO_PCTL_PD1_SSI3FSS 0x00000010 |
| #define | GPIO_PCTL_PD1_SSI1FSS 0x00000020 |
| #define | GPIO_PCTL_PD1_I2C3SDA 0x00000030 |
| #define | GPIO_PCTL_PD1_WT2CCP1 0x00000070 |
| #define | GPIO_PCTL_PD0_M 0x0000000F |
| #define | GPIO_PCTL_PD0_SSI3CLK 0x00000001 |
| #define | GPIO_PCTL_PD0_SSI1CLK 0x00000002 |
| #define | GPIO_PCTL_PD0_I2C3SCL 0x00000003 |
| #define | GPIO_PCTL_PD0_WT2CCP0 0x00000007 |
| #define | GPIO_PCTL_PE5_M 0x00F00000 |
| #define | GPIO_PCTL_PE5_U5TX 0x00100000 |
| #define | GPIO_PCTL_PE5_I2C2SDA 0x00300000 |
| #define | GPIO_PCTL_PE5_CAN0TX 0x00800000 |
| #define | GPIO_PCTL_PE4_M 0x000F0000 |
| #define | GPIO_PCTL_PE4_U5RX 0x00010000 |
| #define | GPIO_PCTL_PE4_I2C2SCL 0x00030000 |
| #define | GPIO_PCTL_PE4_CAN0RX 0x00080000 |
| #define | GPIO_PCTL_PE3_M 0x0000F000 |
| #define | GPIO_PCTL_PE2_M 0x00000F00 |
| #define | GPIO_PCTL_PE1_M 0x000000F0 |
| #define | GPIO_PCTL_PE1_U7TX 0x00000010 |
| #define | GPIO_PCTL_PE0_M 0x0000000F |
| #define | GPIO_PCTL_PE0_U7RX 0x00000001 |
| #define | GPIO_PCTL_PF4_M 0x000F0000 |
| #define | GPIO_PCTL_PF4_T2CCP0 0x00070000 |
| #define | GPIO_PCTL_PF3_M 0x0000F000 |
| #define | GPIO_PCTL_PF3_SSI1FSS 0x00002000 |
| #define | GPIO_PCTL_PF3_CAN0TX 0x00003000 |
| #define | GPIO_PCTL_PF3_T1CCP1 0x00007000 |
| #define | GPIO_PCTL_PF3_TRCLK 0x0000E000 |
| #define | GPIO_PCTL_PF2_M 0x00000F00 |
| #define | GPIO_PCTL_PF2_SSI1CLK 0x00000200 |
| #define | GPIO_PCTL_PF2_T1CCP0 0x00000700 |
| #define | GPIO_PCTL_PF2_TRD0 0x00000E00 |
| #define | GPIO_PCTL_PF1_M 0x000000F0 |
| #define | GPIO_PCTL_PF1_U1CTS 0x00000010 |
| #define | GPIO_PCTL_PF1_SSI1TX 0x00000020 |
| #define | GPIO_PCTL_PF1_T0CCP1 0x00000070 |
| #define | GPIO_PCTL_PF1_C1O 0x00000090 |
| #define | GPIO_PCTL_PF1_TRD1 0x000000E0 |
| #define | GPIO_PCTL_PF0_M 0x0000000F |
| #define | GPIO_PCTL_PF0_U1RTS 0x00000001 |
| #define | GPIO_PCTL_PF0_SSI1RX 0x00000002 |
| #define | GPIO_PCTL_PF0_CAN0RX 0x00000003 |
| #define | GPIO_PCTL_PF0_T0CCP0 0x00000007 |
| #define | GPIO_PCTL_PF0_NMI 0x00000008 |
| #define | GPIO_PCTL_PF0_C0O 0x00000009 |
| #define | GPIO_PCTL_PF0_TRD2 0x0000000E |
| #define | SSI_CR0_SCR_M 0x0000FF00 |
| #define | SSI_CR0_SPH 0x00000080 |
| #define | SSI_CR0_SPO 0x00000040 |
| #define | SSI_CR0_FRF_M 0x00000030 |
| #define | SSI_CR0_FRF_MOTO 0x00000000 |
| #define | SSI_CR0_FRF_TI 0x00000010 |
| #define | SSI_CR0_FRF_NMW 0x00000020 |
| #define | SSI_CR0_DSS_M 0x0000000F |
| #define | SSI_CR0_DSS_4 0x00000003 |
| #define | SSI_CR0_DSS_5 0x00000004 |
| #define | SSI_CR0_DSS_6 0x00000005 |
| #define | SSI_CR0_DSS_7 0x00000006 |
| #define | SSI_CR0_DSS_8 0x00000007 |
| #define | SSI_CR0_DSS_9 0x00000008 |
| #define | SSI_CR0_DSS_10 0x00000009 |
| #define | SSI_CR0_DSS_11 0x0000000A |
| #define | SSI_CR0_DSS_12 0x0000000B |
| #define | SSI_CR0_DSS_13 0x0000000C |
| #define | SSI_CR0_DSS_14 0x0000000D |
| #define | SSI_CR0_DSS_15 0x0000000E |
| #define | SSI_CR0_DSS_16 0x0000000F |
| #define | SSI_CR0_SCR_S 8 |
| #define | SSI_CR1_EOT 0x00000010 |
| #define | SSI_CR1_SOD 0x00000008 |
| #define | SSI_CR1_MS 0x00000004 |
| #define | SSI_CR1_SSE 0x00000002 |
| #define | SSI_CR1_LBM 0x00000001 |
| #define | SSI_DR_DATA_M 0x0000FFFF |
| #define | SSI_DR_DATA_S 0 |
| #define | SSI_SR_BSY 0x00000010 |
| #define | SSI_SR_RFF 0x00000008 |
| #define | SSI_SR_RNE 0x00000004 |
| #define | SSI_SR_TNF 0x00000002 |
| #define | SSI_SR_TFE 0x00000001 |
| #define | SSI_CPSR_CPSDVSR_M 0x000000FF |
| #define | SSI_CPSR_CPSDVSR_S 0 |
| #define | SSI_IM_TXIM 0x00000008 |
| #define | SSI_IM_RXIM 0x00000004 |
| #define | SSI_IM_RTIM 0x00000002 |
| #define | SSI_IM_RORIM 0x00000001 |
| #define | SSI_RIS_TXRIS 0x00000008 |
| #define | SSI_RIS_RXRIS 0x00000004 |
| #define | SSI_RIS_RTRIS 0x00000002 |
| #define | SSI_RIS_RORRIS 0x00000001 |
| #define | SSI_MIS_TXMIS 0x00000008 |
| #define | SSI_MIS_RXMIS 0x00000004 |
| #define | SSI_MIS_RTMIS 0x00000002 |
| #define | SSI_MIS_RORMIS 0x00000001 |
| #define | SSI_ICR_RTIC 0x00000002 |
| #define | SSI_ICR_RORIC 0x00000001 |
| #define | SSI_DMACTL_TXDMAE 0x00000002 |
| #define | SSI_DMACTL_RXDMAE 0x00000001 |
| #define | SSI_CC_CS_M 0x0000000F |
| #define | SSI_CC_CS_SYSPLL 0x00000000 |
| #define | SSI_CC_CS_PIOSC 0x00000005 |
| #define | UART_DR_OE 0x00000800 |
| #define | UART_DR_BE 0x00000400 |
| #define | UART_DR_PE 0x00000200 |
| #define | UART_DR_FE 0x00000100 |
| #define | UART_DR_DATA_M 0x000000FF |
| #define | UART_DR_DATA_S 0 |
| #define | UART_RSR_OE 0x00000008 |
| #define | UART_RSR_BE 0x00000004 |
| #define | UART_RSR_PE 0x00000002 |
| #define | UART_RSR_FE 0x00000001 |
| #define | UART_ECR_DATA_M 0x000000FF |
| #define | UART_ECR_DATA_S 0 |
| #define | UART_FR_TXFE 0x00000080 |
| #define | UART_FR_RXFF 0x00000040 |
| #define | UART_FR_TXFF 0x00000020 |
| #define | UART_FR_RXFE 0x00000010 |
| #define | UART_FR_BUSY 0x00000008 |
| #define | UART_FR_CTS 0x00000001 |
| #define | UART_ILPR_ILPDVSR_M 0x000000FF |
| #define | UART_ILPR_ILPDVSR_S 0 |
| #define | UART_IBRD_DIVINT_M 0x0000FFFF |
| #define | UART_IBRD_DIVINT_S 0 |
| #define | UART_FBRD_DIVFRAC_M 0x0000003F |
| #define | UART_FBRD_DIVFRAC_S 0 |
| #define | UART_LCRH_SPS 0x00000080 |
| #define | UART_LCRH_WLEN_M 0x00000060 |
| #define | UART_LCRH_WLEN_5 0x00000000 |
| #define | UART_LCRH_WLEN_6 0x00000020 |
| #define | UART_LCRH_WLEN_7 0x00000040 |
| #define | UART_LCRH_WLEN_8 0x00000060 |
| #define | UART_LCRH_FEN 0x00000010 |
| #define | UART_LCRH_STP2 0x00000008 |
| #define | UART_LCRH_EPS 0x00000004 |
| #define | UART_LCRH_PEN 0x00000002 |
| #define | UART_LCRH_BRK 0x00000001 |
| #define | UART_CTL_RXE 0x00000200 |
| #define | UART_CTL_TXE 0x00000100 |
| #define | UART_CTL_LBE 0x00000080 |
| #define | UART_CTL_LIN 0x00000040 |
| #define | UART_CTL_HSE 0x00000020 |
| #define | UART_CTL_EOT 0x00000010 |
| #define | UART_CTL_SMART 0x00000008 |
| #define | UART_CTL_SIRLP 0x00000004 |
| #define | UART_CTL_SIREN 0x00000002 |
| #define | UART_CTL_UARTEN 0x00000001 |
| #define | UART_IFLS_RX_M 0x00000038 |
| #define | UART_IFLS_RX1_8 0x00000000 |
| #define | UART_IFLS_RX2_8 0x00000008 |
| #define | UART_IFLS_RX4_8 0x00000010 |
| #define | UART_IFLS_RX6_8 0x00000018 |
| #define | UART_IFLS_RX7_8 0x00000020 |
| #define | UART_IFLS_TX_M 0x00000007 |
| #define | UART_IFLS_TX1_8 0x00000000 |
| #define | UART_IFLS_TX2_8 0x00000001 |
| #define | UART_IFLS_TX4_8 0x00000002 |
| #define | UART_IFLS_TX6_8 0x00000003 |
| #define | UART_IFLS_TX7_8 0x00000004 |
| #define | UART_IM_LME5IM 0x00008000 |
| #define | UART_IM_LME1IM 0x00004000 |
| #define | UART_IM_LMSBIM 0x00002000 |
| #define | UART_IM_9BITIM 0x00001000 |
| #define | UART_IM_OEIM 0x00000400 |
| #define | UART_IM_BEIM 0x00000200 |
| #define | UART_IM_PEIM 0x00000100 |
| #define | UART_IM_FEIM 0x00000080 |
| #define | UART_IM_RTIM 0x00000040 |
| #define | UART_IM_TXIM 0x00000020 |
| #define | UART_IM_RXIM 0x00000010 |
| #define | UART_IM_CTSMIM 0x00000002 |
| #define | UART_RIS_LME5RIS 0x00008000 |
| #define | UART_RIS_LME1RIS 0x00004000 |
| #define | UART_RIS_LMSBRIS 0x00002000 |
| #define | UART_RIS_9BITRIS 0x00001000 |
| #define | UART_RIS_OERIS 0x00000400 |
| #define | UART_RIS_BERIS 0x00000200 |
| #define | UART_RIS_PERIS 0x00000100 |
| #define | UART_RIS_FERIS 0x00000080 |
| #define | UART_RIS_RTRIS 0x00000040 |
| #define | UART_RIS_TXRIS 0x00000020 |
| #define | UART_RIS_RXRIS 0x00000010 |
| #define | UART_RIS_CTSRIS 0x00000002 |
| #define | UART_MIS_LME5MIS 0x00008000 |
| #define | UART_MIS_LME1MIS 0x00004000 |
| #define | UART_MIS_LMSBMIS 0x00002000 |
| #define | UART_MIS_9BITMIS 0x00001000 |
| #define | UART_MIS_OEMIS 0x00000400 |
| #define | UART_MIS_BEMIS 0x00000200 |
| #define | UART_MIS_PEMIS 0x00000100 |
| #define | UART_MIS_FEMIS 0x00000080 |
| #define | UART_MIS_RTMIS 0x00000040 |
| #define | UART_MIS_TXMIS 0x00000020 |
| #define | UART_MIS_RXMIS 0x00000010 |
| #define | UART_MIS_CTSMIS 0x00000002 |
| #define | UART_ICR_LME5IC 0x00008000 |
| #define | UART_ICR_LME1IC 0x00004000 |
| #define | UART_ICR_LMSBIC 0x00002000 |
| #define | UART_ICR_9BITIC 0x00001000 |
| #define | UART_ICR_OEIC 0x00000400 |
| #define | UART_ICR_BEIC 0x00000200 |
| #define | UART_ICR_PEIC 0x00000100 |
| #define | UART_ICR_FEIC 0x00000080 |
| #define | UART_ICR_RTIC 0x00000040 |
| #define | UART_ICR_TXIC 0x00000020 |
| #define | UART_ICR_RXIC 0x00000010 |
| #define | UART_ICR_CTSMIC 0x00000002 |
| #define | UART_DMACTL_DMAERR 0x00000004 |
| #define | UART_DMACTL_TXDMAE 0x00000002 |
| #define | UART_DMACTL_RXDMAE 0x00000001 |
| #define | UART_LCTL_BLEN_M 0x00000030 |
| #define | UART_LCTL_BLEN_13T 0x00000000 |
| #define | UART_LCTL_BLEN_14T 0x00000010 |
| #define | UART_LCTL_BLEN_15T 0x00000020 |
| #define | UART_LCTL_BLEN_16T 0x00000030 |
| #define | UART_LCTL_MASTER 0x00000001 |
| #define | UART_LSS_TSS_M 0x0000FFFF |
| #define | UART_LSS_TSS_S 0 |
| #define | UART_LTIM_TIMER_M 0x0000FFFF |
| #define | UART_LTIM_TIMER_S 0 |
| #define | UART_9BITADDR_9BITEN 0x00008000 |
| #define | UART_9BITADDR_ADDR_M 0x000000FF |
| #define | UART_9BITADDR_ADDR_S 0 |
| #define | UART_9BITAMASK_MASK_M 0x000000FF |
| #define | UART_9BITAMASK_MASK_S 0 |
| #define | UART_PP_NB 0x00000002 |
| #define | UART_PP_SC 0x00000001 |
| #define | UART_CC_CS_M 0x0000000F |
| #define | UART_CC_CS_SYSCLK 0x00000000 |
| #define | UART_CC_CS_PIOSC 0x00000005 |
| #define | I2C_MSA_SA_M 0x000000FE |
| #define | I2C_MSA_RS 0x00000001 |
| #define | I2C_MSA_SA_S 1 |
| #define | I2C_SOAR_OAR_M 0x0000007F |
| #define | I2C_SOAR_OAR_S 0 |
| #define | I2C_SCSR_OAR2SEL 0x00000008 |
| #define | I2C_SCSR_FBR 0x00000004 |
| #define | I2C_SCSR_TREQ 0x00000002 |
| #define | I2C_SCSR_DA 0x00000001 |
| #define | I2C_SCSR_RREQ 0x00000001 |
| #define | I2C_MCS_CLKTO 0x00000080 |
| #define | I2C_MCS_BUSBSY 0x00000040 |
| #define | I2C_MCS_IDLE 0x00000020 |
| #define | I2C_MCS_ARBLST 0x00000010 |
| #define | I2C_MCS_HS 0x00000010 |
| #define | I2C_MCS_ACK 0x00000008 |
| #define | I2C_MCS_DATACK 0x00000008 |
| #define | I2C_MCS_ADRACK 0x00000004 |
| #define | I2C_MCS_STOP 0x00000004 |
| #define | I2C_MCS_ERROR 0x00000002 |
| #define | I2C_MCS_START 0x00000002 |
| #define | I2C_MCS_RUN 0x00000001 |
| #define | I2C_MCS_BUSY 0x00000001 |
| #define | I2C_SDR_DATA_M 0x000000FF |
| #define | I2C_SDR_DATA_S 0 |
| #define | I2C_MDR_DATA_M 0x000000FF |
| #define | I2C_MDR_DATA_S 0 |
| #define | I2C_MTPR_HS 0x00000080 |
| #define | I2C_MTPR_TPR_M 0x0000007F |
| #define | I2C_MTPR_TPR_S 0 |
| #define | I2C_SIMR_STOPIM 0x00000004 |
| #define | I2C_SIMR_STARTIM 0x00000002 |
| #define | I2C_SIMR_DATAIM 0x00000001 |
| #define | I2C_SRIS_STOPRIS 0x00000004 |
| #define | I2C_SRIS_STARTRIS 0x00000002 |
| #define | I2C_SRIS_DATARIS 0x00000001 |
| #define | I2C_MIMR_CLKIM 0x00000002 |
| #define | I2C_MIMR_IM 0x00000001 |
| #define | I2C_MRIS_CLKRIS 0x00000002 |
| #define | I2C_MRIS_RIS 0x00000001 |
| #define | I2C_SMIS_STOPMIS 0x00000004 |
| #define | I2C_SMIS_STARTMIS 0x00000002 |
| #define | I2C_SMIS_DATAMIS 0x00000001 |
| #define | I2C_SICR_STOPIC 0x00000004 |
| #define | I2C_SICR_STARTIC 0x00000002 |
| #define | I2C_SICR_DATAIC 0x00000001 |
| #define | I2C_MMIS_CLKMIS 0x00000002 |
| #define | I2C_MMIS_MIS 0x00000001 |
| #define | I2C_MICR_CLKIC 0x00000002 |
| #define | I2C_MICR_IC 0x00000001 |
| #define | I2C_SOAR2_OAR2EN 0x00000080 |
| #define | I2C_SOAR2_OAR2_M 0x0000007F |
| #define | I2C_SOAR2_OAR2_S 0 |
| #define | I2C_MCR_SFE 0x00000020 |
| #define | I2C_MCR_MFE 0x00000010 |
| #define | I2C_MCR_LPBK 0x00000001 |
| #define | I2C_SACKCTL_ACKOVAL 0x00000002 |
| #define | I2C_SACKCTL_ACKOEN 0x00000001 |
| #define | I2C_MCLKOCNT_CNTL_M 0x000000FF |
| #define | I2C_MCLKOCNT_CNTL_S 0 |
| #define | I2C_MBMON_SDA 0x00000002 |
| #define | I2C_MBMON_SCL 0x00000001 |
| #define | I2C_PP_HS 0x00000001 |
| #define | I2C_PC_HS 0x00000001 |
| #define | TIMER_CFG_M 0x00000007 |
| #define | TIMER_CFG_32_BIT_TIMER 0x00000000 |
| #define | TIMER_CFG_32_BIT_RTC 0x00000001 |
| #define | TIMER_CFG_16_BIT 0x00000004 |
| #define | TIMER_TAMR_TAPLO 0x00000800 |
| #define | TIMER_TAMR_TAMRSU 0x00000400 |
| #define | TIMER_TAMR_TAPWMIE 0x00000200 |
| #define | TIMER_TAMR_TAILD 0x00000100 |
| #define | TIMER_TAMR_TASNAPS 0x00000080 |
| #define | TIMER_TAMR_TAWOT 0x00000040 |
| #define | TIMER_TAMR_TAMIE 0x00000020 |
| #define | TIMER_TAMR_TACDIR 0x00000010 |
| #define | TIMER_TAMR_TAAMS 0x00000008 |
| #define | TIMER_TAMR_TACMR 0x00000004 |
| #define | TIMER_TAMR_TAMR_M 0x00000003 |
| #define | TIMER_TAMR_TAMR_1_SHOT 0x00000001 |
| #define | TIMER_TAMR_TAMR_PERIOD 0x00000002 |
| #define | TIMER_TAMR_TAMR_CAP 0x00000003 |
| #define | TIMER_TBMR_TBPLO 0x00000800 |
| #define | TIMER_TBMR_TBMRSU 0x00000400 |
| #define | TIMER_TBMR_TBPWMIE 0x00000200 |
| #define | TIMER_TBMR_TBILD 0x00000100 |
| #define | TIMER_TBMR_TBSNAPS 0x00000080 |
| #define | TIMER_TBMR_TBWOT 0x00000040 |
| #define | TIMER_TBMR_TBMIE 0x00000020 |
| #define | TIMER_TBMR_TBCDIR 0x00000010 |
| #define | TIMER_TBMR_TBAMS 0x00000008 |
| #define | TIMER_TBMR_TBCMR 0x00000004 |
| #define | TIMER_TBMR_TBMR_M 0x00000003 |
| #define | TIMER_TBMR_TBMR_1_SHOT 0x00000001 |
| #define | TIMER_TBMR_TBMR_PERIOD 0x00000002 |
| #define | TIMER_TBMR_TBMR_CAP 0x00000003 |
| #define | TIMER_CTL_TBPWML 0x00004000 |
| #define | TIMER_CTL_TBOTE 0x00002000 |
| #define | TIMER_CTL_TBEVENT_M 0x00000C00 |
| #define | TIMER_CTL_TBEVENT_POS 0x00000000 |
| #define | TIMER_CTL_TBEVENT_NEG 0x00000400 |
| #define | TIMER_CTL_TBEVENT_BOTH 0x00000C00 |
| #define | TIMER_CTL_TBSTALL 0x00000200 |
| #define | TIMER_CTL_TBEN 0x00000100 |
| #define | TIMER_CTL_TAPWML 0x00000040 |
| #define | TIMER_CTL_TAOTE 0x00000020 |
| #define | TIMER_CTL_RTCEN 0x00000010 |
| #define | TIMER_CTL_TAEVENT_M 0x0000000C |
| #define | TIMER_CTL_TAEVENT_POS 0x00000000 |
| #define | TIMER_CTL_TAEVENT_NEG 0x00000004 |
| #define | TIMER_CTL_TAEVENT_BOTH 0x0000000C |
| #define | TIMER_CTL_TASTALL 0x00000002 |
| #define | TIMER_CTL_TAEN 0x00000001 |
| #define | TIMER_SYNC_SYNCWT5_M 0x00C00000 |
| #define | TIMER_SYNC_SYNCWT5_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT5_TA 0x00400000 |
| #define | TIMER_SYNC_SYNCWT5_TB 0x00800000 |
| #define | TIMER_SYNC_SYNCWT5_TATB 0x00C00000 |
| #define | TIMER_SYNC_SYNCWT4_M 0x00300000 |
| #define | TIMER_SYNC_SYNCWT4_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT4_TA 0x00100000 |
| #define | TIMER_SYNC_SYNCWT4_TB 0x00200000 |
| #define | TIMER_SYNC_SYNCWT4_TATB 0x00300000 |
| #define | TIMER_SYNC_SYNCWT3_M 0x000C0000 |
| #define | TIMER_SYNC_SYNCWT3_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT3_TA 0x00040000 |
| #define | TIMER_SYNC_SYNCWT3_TB 0x00080000 |
| #define | TIMER_SYNC_SYNCWT3_TATB 0x000C0000 |
| #define | TIMER_SYNC_SYNCWT2_M 0x00030000 |
| #define | TIMER_SYNC_SYNCWT2_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT2_TA 0x00010000 |
| #define | TIMER_SYNC_SYNCWT2_TB 0x00020000 |
| #define | TIMER_SYNC_SYNCWT2_TATB 0x00030000 |
| #define | TIMER_SYNC_SYNCWT1_M 0x0000C000 |
| #define | TIMER_SYNC_SYNCWT1_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT1_TA 0x00004000 |
| #define | TIMER_SYNC_SYNCWT1_TB 0x00008000 |
| #define | TIMER_SYNC_SYNCWT1_TATB 0x0000C000 |
| #define | TIMER_SYNC_SYNCWT0_M 0x00003000 |
| #define | TIMER_SYNC_SYNCWT0_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT0_TA 0x00001000 |
| #define | TIMER_SYNC_SYNCWT0_TB 0x00002000 |
| #define | TIMER_SYNC_SYNCWT0_TATB 0x00003000 |
| #define | TIMER_SYNC_SYNCT5_M 0x00000C00 |
| #define | TIMER_SYNC_SYNCT5_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT5_TA 0x00000400 |
| #define | TIMER_SYNC_SYNCT5_TB 0x00000800 |
| #define | TIMER_SYNC_SYNCT5_TATB 0x00000C00 |
| #define | TIMER_SYNC_SYNCT4_M 0x00000300 |
| #define | TIMER_SYNC_SYNCT4_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT4_TA 0x00000100 |
| #define | TIMER_SYNC_SYNCT4_TB 0x00000200 |
| #define | TIMER_SYNC_SYNCT4_TATB 0x00000300 |
| #define | TIMER_SYNC_SYNCT3_M 0x000000C0 |
| #define | TIMER_SYNC_SYNCT3_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT3_TA 0x00000040 |
| #define | TIMER_SYNC_SYNCT3_TB 0x00000080 |
| #define | TIMER_SYNC_SYNCT3_TATB 0x000000C0 |
| #define | TIMER_SYNC_SYNCT2_M 0x00000030 |
| #define | TIMER_SYNC_SYNCT2_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT2_TA 0x00000010 |
| #define | TIMER_SYNC_SYNCT2_TB 0x00000020 |
| #define | TIMER_SYNC_SYNCT2_TATB 0x00000030 |
| #define | TIMER_SYNC_SYNCT1_M 0x0000000C |
| #define | TIMER_SYNC_SYNCT1_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT1_TA 0x00000004 |
| #define | TIMER_SYNC_SYNCT1_TB 0x00000008 |
| #define | TIMER_SYNC_SYNCT1_TATB 0x0000000C |
| #define | TIMER_SYNC_SYNCT0_M 0x00000003 |
| #define | TIMER_SYNC_SYNCT0_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT0_TA 0x00000001 |
| #define | TIMER_SYNC_SYNCT0_TB 0x00000002 |
| #define | TIMER_SYNC_SYNCT0_TATB 0x00000003 |
| #define | TIMER_IMR_WUEIM 0x00010000 |
| #define | TIMER_IMR_TBMIM 0x00000800 |
| #define | TIMER_IMR_CBEIM 0x00000400 |
| #define | TIMER_IMR_CBMIM 0x00000200 |
| #define | TIMER_IMR_TBTOIM 0x00000100 |
| #define | TIMER_IMR_TAMIM 0x00000010 |
| #define | TIMER_IMR_RTCIM 0x00000008 |
| #define | TIMER_IMR_CAEIM 0x00000004 |
| #define | TIMER_IMR_CAMIM 0x00000002 |
| #define | TIMER_IMR_TATOIM 0x00000001 |
| #define | TIMER_RIS_WUERIS 0x00010000 |
| #define | TIMER_RIS_TBMRIS 0x00000800 |
| #define | TIMER_RIS_CBERIS 0x00000400 |
| #define | TIMER_RIS_CBMRIS 0x00000200 |
| #define | TIMER_RIS_TBTORIS 0x00000100 |
| #define | TIMER_RIS_TAMRIS 0x00000010 |
| #define | TIMER_RIS_RTCRIS 0x00000008 |
| #define | TIMER_RIS_CAERIS 0x00000004 |
| #define | TIMER_RIS_CAMRIS 0x00000002 |
| #define | TIMER_RIS_TATORIS 0x00000001 |
| #define | TIMER_MIS_WUEMIS 0x00010000 |
| #define | TIMER_MIS_TBMMIS 0x00000800 |
| #define | TIMER_MIS_CBEMIS 0x00000400 |
| #define | TIMER_MIS_CBMMIS 0x00000200 |
| #define | TIMER_MIS_TBTOMIS 0x00000100 |
| #define | TIMER_MIS_TAMMIS 0x00000010 |
| #define | TIMER_MIS_RTCMIS 0x00000008 |
| #define | TIMER_MIS_CAEMIS 0x00000004 |
| #define | TIMER_MIS_CAMMIS 0x00000002 |
| #define | TIMER_MIS_TATOMIS 0x00000001 |
| #define | TIMER_ICR_WUECINT 0x00010000 |
| #define | TIMER_ICR_TBMCINT 0x00000800 |
| #define | TIMER_ICR_CBECINT 0x00000400 |
| #define | TIMER_ICR_CBMCINT 0x00000200 |
| #define | TIMER_ICR_TBTOCINT 0x00000100 |
| #define | TIMER_ICR_TAMCINT 0x00000010 |
| #define | TIMER_ICR_RTCCINT 0x00000008 |
| #define | TIMER_ICR_CAECINT 0x00000004 |
| #define | TIMER_ICR_CAMCINT 0x00000002 |
| #define | TIMER_ICR_TATOCINT 0x00000001 |
| #define | TIMER_TAILR_M 0xFFFFFFFF |
| #define | TIMER_TAILR_S 0 |
| #define | TIMER_TBILR_M 0xFFFFFFFF |
| #define | TIMER_TBILR_S 0 |
| #define | TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF |
| #define | TIMER_TAMATCHR_TAMR_S 0 |
| #define | TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF |
| #define | TIMER_TBMATCHR_TBMR_S 0 |
| #define | TIMER_TAPR_TAPSRH_M 0x0000FF00 |
| #define | TIMER_TAPR_TAPSR_M 0x000000FF |
| #define | TIMER_TAPR_TAPSRH_S 8 |
| #define | TIMER_TAPR_TAPSR_S 0 |
| #define | TIMER_TBPR_TBPSRH_M 0x0000FF00 |
| #define | TIMER_TBPR_TBPSR_M 0x000000FF |
| #define | TIMER_TBPR_TBPSRH_S 8 |
| #define | TIMER_TBPR_TBPSR_S 0 |
| #define | TIMER_TAPMR_TAPSMRH_M 0x0000FF00 |
| #define | TIMER_TAPMR_TAPSMR_M 0x000000FF |
| #define | TIMER_TAPMR_TAPSMRH_S 8 |
| #define | TIMER_TAPMR_TAPSMR_S 0 |
| #define | TIMER_TBPMR_TBPSMRH_M 0x0000FF00 |
| #define | TIMER_TBPMR_TBPSMR_M 0x000000FF |
| #define | TIMER_TBPMR_TBPSMRH_S 8 |
| #define | TIMER_TBPMR_TBPSMR_S 0 |
| #define | TIMER_TAR_M 0xFFFFFFFF |
| #define | TIMER_TAR_S 0 |
| #define | TIMER_TBR_M 0xFFFFFFFF |
| #define | TIMER_TBR_S 0 |
| #define | TIMER_TAV_M 0xFFFFFFFF |
| #define | TIMER_TAV_S 0 |
| #define | TIMER_TBV_M 0xFFFFFFFF |
| #define | TIMER_TBV_S 0 |
| #define | TIMER_RTCPD_RTCPD_M 0x0000FFFF |
| #define | TIMER_RTCPD_RTCPD_S 0 |
| #define | TIMER_TAPS_PSS_M 0x0000FFFF |
| #define | TIMER_TAPS_PSS_S 0 |
| #define | TIMER_TBPS_PSS_M 0x0000FFFF |
| #define | TIMER_TBPS_PSS_S 0 |
| #define | TIMER_TAPV_PSV_M 0x0000FFFF |
| #define | TIMER_TAPV_PSV_S 0 |
| #define | TIMER_TBPV_PSV_M 0x0000FFFF |
| #define | TIMER_TBPV_PSV_S 0 |
| #define | TIMER_PP_SIZE_M 0x0000000F |
| #define | TIMER_PP_SIZE_16 0x00000000 |
| #define | TIMER_PP_SIZE_32 0x00000001 |
| #define | ADC_ACTSS_ASEN3 0x00000008 |
| #define | ADC_ACTSS_ASEN2 0x00000004 |
| #define | ADC_ACTSS_ASEN1 0x00000002 |
| #define | ADC_ACTSS_ASEN0 0x00000001 |
| #define | ADC_RIS_INRDC 0x00010000 |
| #define | ADC_RIS_INR3 0x00000008 |
| #define | ADC_RIS_INR2 0x00000004 |
| #define | ADC_RIS_INR1 0x00000002 |
| #define | ADC_RIS_INR0 0x00000001 |
| #define | ADC_IM_DCONSS3 0x00080000 |
| #define | ADC_IM_DCONSS2 0x00040000 |
| #define | ADC_IM_DCONSS1 0x00020000 |
| #define | ADC_IM_DCONSS0 0x00010000 |
| #define | ADC_IM_MASK3 0x00000008 |
| #define | ADC_IM_MASK2 0x00000004 |
| #define | ADC_IM_MASK1 0x00000002 |
| #define | ADC_IM_MASK0 0x00000001 |
| #define | ADC_ISC_DCINSS3 0x00080000 |
| #define | ADC_ISC_DCINSS2 0x00040000 |
| #define | ADC_ISC_DCINSS1 0x00020000 |
| #define | ADC_ISC_DCINSS0 0x00010000 |
| #define | ADC_ISC_IN3 0x00000008 |
| #define | ADC_ISC_IN2 0x00000004 |
| #define | ADC_ISC_IN1 0x00000002 |
| #define | ADC_ISC_IN0 0x00000001 |
| #define | ADC_OSTAT_OV3 0x00000008 |
| #define | ADC_OSTAT_OV2 0x00000004 |
| #define | ADC_OSTAT_OV1 0x00000002 |
| #define | ADC_OSTAT_OV0 0x00000001 |
| #define | ADC_EMUX_EM3_M 0x0000F000 |
| #define | ADC_EMUX_EM3_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM3_COMP0 0x00001000 |
| #define | ADC_EMUX_EM3_COMP1 0x00002000 |
| #define | ADC_EMUX_EM3_EXTERNAL 0x00004000 |
| #define | ADC_EMUX_EM3_TIMER 0x00005000 |
| #define | ADC_EMUX_EM3_ALWAYS 0x0000F000 |
| #define | ADC_EMUX_EM2_M 0x00000F00 |
| #define | ADC_EMUX_EM2_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM2_COMP0 0x00000100 |
| #define | ADC_EMUX_EM2_COMP1 0x00000200 |
| #define | ADC_EMUX_EM2_EXTERNAL 0x00000400 |
| #define | ADC_EMUX_EM2_TIMER 0x00000500 |
| #define | ADC_EMUX_EM2_ALWAYS 0x00000F00 |
| #define | ADC_EMUX_EM1_M 0x000000F0 |
| #define | ADC_EMUX_EM1_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM1_COMP0 0x00000010 |
| #define | ADC_EMUX_EM1_COMP1 0x00000020 |
| #define | ADC_EMUX_EM1_EXTERNAL 0x00000040 |
| #define | ADC_EMUX_EM1_TIMER 0x00000050 |
| #define | ADC_EMUX_EM1_ALWAYS 0x000000F0 |
| #define | ADC_EMUX_EM0_M 0x0000000F |
| #define | ADC_EMUX_EM0_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM0_COMP0 0x00000001 |
| #define | ADC_EMUX_EM0_COMP1 0x00000002 |
| #define | ADC_EMUX_EM0_EXTERNAL 0x00000004 |
| #define | ADC_EMUX_EM0_TIMER 0x00000005 |
| #define | ADC_EMUX_EM0_ALWAYS 0x0000000F |
| #define | ADC_USTAT_UV3 0x00000008 |
| #define | ADC_USTAT_UV2 0x00000004 |
| #define | ADC_USTAT_UV1 0x00000002 |
| #define | ADC_USTAT_UV0 0x00000001 |
| #define | ADC_SSPRI_SS3_M 0x00003000 |
| #define | ADC_SSPRI_SS3_1ST 0x00000000 |
| #define | ADC_SSPRI_SS3_2ND 0x00001000 |
| #define | ADC_SSPRI_SS3_3RD 0x00002000 |
| #define | ADC_SSPRI_SS3_4TH 0x00003000 |
| #define | ADC_SSPRI_SS2_M 0x00000300 |
| #define | ADC_SSPRI_SS2_1ST 0x00000000 |
| #define | ADC_SSPRI_SS2_2ND 0x00000100 |
| #define | ADC_SSPRI_SS2_3RD 0x00000200 |
| #define | ADC_SSPRI_SS2_4TH 0x00000300 |
| #define | ADC_SSPRI_SS1_M 0x00000030 |
| #define | ADC_SSPRI_SS1_1ST 0x00000000 |
| #define | ADC_SSPRI_SS1_2ND 0x00000010 |
| #define | ADC_SSPRI_SS1_3RD 0x00000020 |
| #define | ADC_SSPRI_SS1_4TH 0x00000030 |
| #define | ADC_SSPRI_SS0_M 0x00000003 |
| #define | ADC_SSPRI_SS0_1ST 0x00000000 |
| #define | ADC_SSPRI_SS0_2ND 0x00000001 |
| #define | ADC_SSPRI_SS0_3RD 0x00000002 |
| #define | ADC_SSPRI_SS0_4TH 0x00000003 |
| #define | ADC_SPC_PHASE_M 0x0000000F |
| #define | ADC_SPC_PHASE_0 0x00000000 |
| #define | ADC_SPC_PHASE_22_5 0x00000001 |
| #define | ADC_SPC_PHASE_45 0x00000002 |
| #define | ADC_SPC_PHASE_67_5 0x00000003 |
| #define | ADC_SPC_PHASE_90 0x00000004 |
| #define | ADC_SPC_PHASE_112_5 0x00000005 |
| #define | ADC_SPC_PHASE_135 0x00000006 |
| #define | ADC_SPC_PHASE_157_5 0x00000007 |
| #define | ADC_SPC_PHASE_180 0x00000008 |
| #define | ADC_SPC_PHASE_202_5 0x00000009 |
| #define | ADC_SPC_PHASE_225 0x0000000A |
| #define | ADC_SPC_PHASE_247_5 0x0000000B |
| #define | ADC_SPC_PHASE_270 0x0000000C |
| #define | ADC_SPC_PHASE_292_5 0x0000000D |
| #define | ADC_SPC_PHASE_315 0x0000000E |
| #define | ADC_SPC_PHASE_337_5 0x0000000F |
| #define | ADC_PSSI_GSYNC 0x80000000 |
| #define | ADC_PSSI_SYNCWAIT 0x08000000 |
| #define | ADC_PSSI_SS3 0x00000008 |
| #define | ADC_PSSI_SS2 0x00000004 |
| #define | ADC_PSSI_SS1 0x00000002 |
| #define | ADC_PSSI_SS0 0x00000001 |
| #define | ADC_SAC_AVG_M 0x00000007 |
| #define | ADC_SAC_AVG_OFF 0x00000000 |
| #define | ADC_SAC_AVG_2X 0x00000001 |
| #define | ADC_SAC_AVG_4X 0x00000002 |
| #define | ADC_SAC_AVG_8X 0x00000003 |
| #define | ADC_SAC_AVG_16X 0x00000004 |
| #define | ADC_SAC_AVG_32X 0x00000005 |
| #define | ADC_SAC_AVG_64X 0x00000006 |
| #define | ADC_DCISC_DCINT7 0x00000080 |
| #define | ADC_DCISC_DCINT6 0x00000040 |
| #define | ADC_DCISC_DCINT5 0x00000020 |
| #define | ADC_DCISC_DCINT4 0x00000010 |
| #define | ADC_DCISC_DCINT3 0x00000008 |
| #define | ADC_DCISC_DCINT2 0x00000004 |
| #define | ADC_DCISC_DCINT1 0x00000002 |
| #define | ADC_DCISC_DCINT0 0x00000001 |
| #define | ADC_SSMUX0_MUX7_M 0xF0000000 |
| #define | ADC_SSMUX0_MUX6_M 0x0F000000 |
| #define | ADC_SSMUX0_MUX5_M 0x00F00000 |
| #define | ADC_SSMUX0_MUX4_M 0x000F0000 |
| #define | ADC_SSMUX0_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX0_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX0_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX0_MUX0_M 0x0000000F |
| #define | ADC_SSMUX0_MUX7_S 28 |
| #define | ADC_SSMUX0_MUX6_S 24 |
| #define | ADC_SSMUX0_MUX5_S 20 |
| #define | ADC_SSMUX0_MUX4_S 16 |
| #define | ADC_SSMUX0_MUX3_S 12 |
| #define | ADC_SSMUX0_MUX2_S 8 |
| #define | ADC_SSMUX0_MUX1_S 4 |
| #define | ADC_SSMUX0_MUX0_S 0 |
| #define | ADC_SSCTL0_TS7 0x80000000 |
| #define | ADC_SSCTL0_IE7 0x40000000 |
| #define | ADC_SSCTL0_END7 0x20000000 |
| #define | ADC_SSCTL0_D7 0x10000000 |
| #define | ADC_SSCTL0_TS6 0x08000000 |
| #define | ADC_SSCTL0_IE6 0x04000000 |
| #define | ADC_SSCTL0_END6 0x02000000 |
| #define | ADC_SSCTL0_D6 0x01000000 |
| #define | ADC_SSCTL0_TS5 0x00800000 |
| #define | ADC_SSCTL0_IE5 0x00400000 |
| #define | ADC_SSCTL0_END5 0x00200000 |
| #define | ADC_SSCTL0_D5 0x00100000 |
| #define | ADC_SSCTL0_TS4 0x00080000 |
| #define | ADC_SSCTL0_IE4 0x00040000 |
| #define | ADC_SSCTL0_END4 0x00020000 |
| #define | ADC_SSCTL0_D4 0x00010000 |
| #define | ADC_SSCTL0_TS3 0x00008000 |
| #define | ADC_SSCTL0_IE3 0x00004000 |
| #define | ADC_SSCTL0_END3 0x00002000 |
| #define | ADC_SSCTL0_D3 0x00001000 |
| #define | ADC_SSCTL0_TS2 0x00000800 |
| #define | ADC_SSCTL0_IE2 0x00000400 |
| #define | ADC_SSCTL0_END2 0x00000200 |
| #define | ADC_SSCTL0_D2 0x00000100 |
| #define | ADC_SSCTL0_TS1 0x00000080 |
| #define | ADC_SSCTL0_IE1 0x00000040 |
| #define | ADC_SSCTL0_END1 0x00000020 |
| #define | ADC_SSCTL0_D1 0x00000010 |
| #define | ADC_SSCTL0_TS0 0x00000008 |
| #define | ADC_SSCTL0_IE0 0x00000004 |
| #define | ADC_SSCTL0_END0 0x00000002 |
| #define | ADC_SSCTL0_D0 0x00000001 |
| #define | ADC_SSFIFO0_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO0_DATA_S 0 |
| #define | ADC_SSFSTAT0_FULL 0x00001000 |
| #define | ADC_SSFSTAT0_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT0_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT0_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT0_HPTR_S 4 |
| #define | ADC_SSFSTAT0_TPTR_S 0 |
| #define | ADC_SSOP0_S7DCOP 0x10000000 |
| #define | ADC_SSOP0_S6DCOP 0x01000000 |
| #define | ADC_SSOP0_S5DCOP 0x00100000 |
| #define | ADC_SSOP0_S4DCOP 0x00010000 |
| #define | ADC_SSOP0_S3DCOP 0x00001000 |
| #define | ADC_SSOP0_S2DCOP 0x00000100 |
| #define | ADC_SSOP0_S1DCOP 0x00000010 |
| #define | ADC_SSOP0_S0DCOP 0x00000001 |
| #define | ADC_SSDC0_S7DCSEL_M 0xF0000000 |
| #define | ADC_SSDC0_S6DCSEL_M 0x0F000000 |
| #define | ADC_SSDC0_S5DCSEL_M 0x00F00000 |
| #define | ADC_SSDC0_S4DCSEL_M 0x000F0000 |
| #define | ADC_SSDC0_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC0_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC0_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC0_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC0_S6DCSEL_S 24 |
| #define | ADC_SSDC0_S5DCSEL_S 20 |
| #define | ADC_SSDC0_S4DCSEL_S 16 |
| #define | ADC_SSDC0_S3DCSEL_S 12 |
| #define | ADC_SSDC0_S2DCSEL_S 8 |
| #define | ADC_SSDC0_S1DCSEL_S 4 |
| #define | ADC_SSDC0_S0DCSEL_S 0 |
| #define | ADC_SSMUX1_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX1_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX1_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX1_MUX0_M 0x0000000F |
| #define | ADC_SSMUX1_MUX3_S 12 |
| #define | ADC_SSMUX1_MUX2_S 8 |
| #define | ADC_SSMUX1_MUX1_S 4 |
| #define | ADC_SSMUX1_MUX0_S 0 |
| #define | ADC_SSCTL1_TS3 0x00008000 |
| #define | ADC_SSCTL1_IE3 0x00004000 |
| #define | ADC_SSCTL1_END3 0x00002000 |
| #define | ADC_SSCTL1_D3 0x00001000 |
| #define | ADC_SSCTL1_TS2 0x00000800 |
| #define | ADC_SSCTL1_IE2 0x00000400 |
| #define | ADC_SSCTL1_END2 0x00000200 |
| #define | ADC_SSCTL1_D2 0x00000100 |
| #define | ADC_SSCTL1_TS1 0x00000080 |
| #define | ADC_SSCTL1_IE1 0x00000040 |
| #define | ADC_SSCTL1_END1 0x00000020 |
| #define | ADC_SSCTL1_D1 0x00000010 |
| #define | ADC_SSCTL1_TS0 0x00000008 |
| #define | ADC_SSCTL1_IE0 0x00000004 |
| #define | ADC_SSCTL1_END0 0x00000002 |
| #define | ADC_SSCTL1_D0 0x00000001 |
| #define | ADC_SSFIFO1_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO1_DATA_S 0 |
| #define | ADC_SSFSTAT1_FULL 0x00001000 |
| #define | ADC_SSFSTAT1_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT1_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT1_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT1_HPTR_S 4 |
| #define | ADC_SSFSTAT1_TPTR_S 0 |
| #define | ADC_SSOP1_S3DCOP 0x00001000 |
| #define | ADC_SSOP1_S2DCOP 0x00000100 |
| #define | ADC_SSOP1_S1DCOP 0x00000010 |
| #define | ADC_SSOP1_S0DCOP 0x00000001 |
| #define | ADC_SSDC1_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC1_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC1_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC1_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC1_S2DCSEL_S 8 |
| #define | ADC_SSDC1_S1DCSEL_S 4 |
| #define | ADC_SSDC1_S0DCSEL_S 0 |
| #define | ADC_SSMUX2_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX2_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX2_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX2_MUX0_M 0x0000000F |
| #define | ADC_SSMUX2_MUX3_S 12 |
| #define | ADC_SSMUX2_MUX2_S 8 |
| #define | ADC_SSMUX2_MUX1_S 4 |
| #define | ADC_SSMUX2_MUX0_S 0 |
| #define | ADC_SSCTL2_TS3 0x00008000 |
| #define | ADC_SSCTL2_IE3 0x00004000 |
| #define | ADC_SSCTL2_END3 0x00002000 |
| #define | ADC_SSCTL2_D3 0x00001000 |
| #define | ADC_SSCTL2_TS2 0x00000800 |
| #define | ADC_SSCTL2_IE2 0x00000400 |
| #define | ADC_SSCTL2_END2 0x00000200 |
| #define | ADC_SSCTL2_D2 0x00000100 |
| #define | ADC_SSCTL2_TS1 0x00000080 |
| #define | ADC_SSCTL2_IE1 0x00000040 |
| #define | ADC_SSCTL2_END1 0x00000020 |
| #define | ADC_SSCTL2_D1 0x00000010 |
| #define | ADC_SSCTL2_TS0 0x00000008 |
| #define | ADC_SSCTL2_IE0 0x00000004 |
| #define | ADC_SSCTL2_END0 0x00000002 |
| #define | ADC_SSCTL2_D0 0x00000001 |
| #define | ADC_SSFIFO2_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO2_DATA_S 0 |
| #define | ADC_SSFSTAT2_FULL 0x00001000 |
| #define | ADC_SSFSTAT2_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT2_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT2_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT2_HPTR_S 4 |
| #define | ADC_SSFSTAT2_TPTR_S 0 |
| #define | ADC_SSOP2_S3DCOP 0x00001000 |
| #define | ADC_SSOP2_S2DCOP 0x00000100 |
| #define | ADC_SSOP2_S1DCOP 0x00000010 |
| #define | ADC_SSOP2_S0DCOP 0x00000001 |
| #define | ADC_SSDC2_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC2_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC2_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC2_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC2_S2DCSEL_S 8 |
| #define | ADC_SSDC2_S1DCSEL_S 4 |
| #define | ADC_SSDC2_S0DCSEL_S 0 |
| #define | ADC_SSMUX3_MUX0_M 0x0000000F |
| #define | ADC_SSMUX3_MUX0_S 0 |
| #define | ADC_SSCTL3_TS0 0x00000008 |
| #define | ADC_SSCTL3_IE0 0x00000004 |
| #define | ADC_SSCTL3_END0 0x00000002 |
| #define | ADC_SSCTL3_D0 0x00000001 |
| #define | ADC_SSFIFO3_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO3_DATA_S 0 |
| #define | ADC_SSFSTAT3_FULL 0x00001000 |
| #define | ADC_SSFSTAT3_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT3_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT3_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT3_HPTR_S 4 |
| #define | ADC_SSFSTAT3_TPTR_S 0 |
| #define | ADC_SSOP3_S0DCOP 0x00000001 |
| #define | ADC_SSDC3_S0DCSEL_M 0x0000000F |
| #define | ADC_DCRIC_DCTRIG7 0x00800000 |
| #define | ADC_DCRIC_DCTRIG6 0x00400000 |
| #define | ADC_DCRIC_DCTRIG5 0x00200000 |
| #define | ADC_DCRIC_DCTRIG4 0x00100000 |
| #define | ADC_DCRIC_DCTRIG3 0x00080000 |
| #define | ADC_DCRIC_DCTRIG2 0x00040000 |
| #define | ADC_DCRIC_DCTRIG1 0x00020000 |
| #define | ADC_DCRIC_DCTRIG0 0x00010000 |
| #define | ADC_DCRIC_DCINT7 0x00000080 |
| #define | ADC_DCRIC_DCINT6 0x00000040 |
| #define | ADC_DCRIC_DCINT5 0x00000020 |
| #define | ADC_DCRIC_DCINT4 0x00000010 |
| #define | ADC_DCRIC_DCINT3 0x00000008 |
| #define | ADC_DCRIC_DCINT2 0x00000004 |
| #define | ADC_DCRIC_DCINT1 0x00000002 |
| #define | ADC_DCRIC_DCINT0 0x00000001 |
| #define | ADC_DCCTL0_CIE 0x00000010 |
| #define | ADC_DCCTL0_CIC_M 0x0000000C |
| #define | ADC_DCCTL0_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL0_CIC_MID 0x00000004 |
| #define | ADC_DCCTL0_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL0_CIM_M 0x00000003 |
| #define | ADC_DCCTL0_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL0_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL0_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL0_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL1_CIE 0x00000010 |
| #define | ADC_DCCTL1_CIC_M 0x0000000C |
| #define | ADC_DCCTL1_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL1_CIC_MID 0x00000004 |
| #define | ADC_DCCTL1_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL1_CIM_M 0x00000003 |
| #define | ADC_DCCTL1_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL1_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL1_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL1_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL2_CIE 0x00000010 |
| #define | ADC_DCCTL2_CIC_M 0x0000000C |
| #define | ADC_DCCTL2_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL2_CIC_MID 0x00000004 |
| #define | ADC_DCCTL2_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL2_CIM_M 0x00000003 |
| #define | ADC_DCCTL2_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL2_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL2_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL2_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL3_CIE 0x00000010 |
| #define | ADC_DCCTL3_CIC_M 0x0000000C |
| #define | ADC_DCCTL3_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL3_CIC_MID 0x00000004 |
| #define | ADC_DCCTL3_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL3_CIM_M 0x00000003 |
| #define | ADC_DCCTL3_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL3_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL3_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL3_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL4_CIE 0x00000010 |
| #define | ADC_DCCTL4_CIC_M 0x0000000C |
| #define | ADC_DCCTL4_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL4_CIC_MID 0x00000004 |
| #define | ADC_DCCTL4_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL4_CIM_M 0x00000003 |
| #define | ADC_DCCTL4_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL4_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL4_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL4_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL5_CIE 0x00000010 |
| #define | ADC_DCCTL5_CIC_M 0x0000000C |
| #define | ADC_DCCTL5_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL5_CIC_MID 0x00000004 |
| #define | ADC_DCCTL5_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL5_CIM_M 0x00000003 |
| #define | ADC_DCCTL5_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL5_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL5_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL5_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL6_CIE 0x00000010 |
| #define | ADC_DCCTL6_CIC_M 0x0000000C |
| #define | ADC_DCCTL6_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL6_CIC_MID 0x00000004 |
| #define | ADC_DCCTL6_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL6_CIM_M 0x00000003 |
| #define | ADC_DCCTL6_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL6_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL6_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL6_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL7_CIE 0x00000010 |
| #define | ADC_DCCTL7_CIC_M 0x0000000C |
| #define | ADC_DCCTL7_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL7_CIC_MID 0x00000004 |
| #define | ADC_DCCTL7_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL7_CIM_M 0x00000003 |
| #define | ADC_DCCTL7_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL7_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL7_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL7_CIM_HONCE 0x00000003 |
| #define | ADC_DCCMP0_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP0_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP0_COMP1_S 16 |
| #define | ADC_DCCMP0_COMP0_S 0 |
| #define | ADC_DCCMP1_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP1_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP1_COMP1_S 16 |
| #define | ADC_DCCMP1_COMP0_S 0 |
| #define | ADC_DCCMP2_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP2_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP2_COMP1_S 16 |
| #define | ADC_DCCMP2_COMP0_S 0 |
| #define | ADC_DCCMP3_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP3_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP3_COMP1_S 16 |
| #define | ADC_DCCMP3_COMP0_S 0 |
| #define | ADC_DCCMP4_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP4_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP4_COMP1_S 16 |
| #define | ADC_DCCMP4_COMP0_S 0 |
| #define | ADC_DCCMP5_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP5_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP5_COMP1_S 16 |
| #define | ADC_DCCMP5_COMP0_S 0 |
| #define | ADC_DCCMP6_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP6_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP6_COMP1_S 16 |
| #define | ADC_DCCMP6_COMP0_S 0 |
| #define | ADC_DCCMP7_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP7_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP7_COMP1_S 16 |
| #define | ADC_DCCMP7_COMP0_S 0 |
| #define | ADC_PP_TS 0x00800000 |
| #define | ADC_PP_RSL_M 0x007C0000 |
| #define | ADC_PP_TYPE_M 0x00030000 |
| #define | ADC_PP_TYPE_SAR 0x00000000 |
| #define | ADC_PP_DC_M 0x0000FC00 |
| #define | ADC_PP_CH_M 0x000003F0 |
| #define | ADC_PP_MSR_M 0x0000000F |
| #define | ADC_PP_MSR_125K 0x00000001 |
| #define | ADC_PP_MSR_250K 0x00000003 |
| #define | ADC_PP_MSR_500K 0x00000005 |
| #define | ADC_PP_MSR_1M 0x00000007 |
| #define | ADC_PP_RSL_S 18 |
| #define | ADC_PP_DC_S 10 |
| #define | ADC_PP_CH_S 4 |
| #define | ADC_PC_SR_M 0x0000000F |
| #define | ADC_PC_SR_125K 0x00000001 |
| #define | ADC_PC_SR_250K 0x00000003 |
| #define | ADC_PC_SR_500K 0x00000005 |
| #define | ADC_PC_SR_1M 0x00000007 |
| #define | ADC_CC_CS_M 0x0000000F |
| #define | ADC_CC_CS_SYSPLL 0x00000000 |
| #define | ADC_CC_CS_PIOSC 0x00000001 |
| #define | COMP_ACMIS_IN1 0x00000002 |
| #define | COMP_ACMIS_IN0 0x00000001 |
| #define | COMP_ACRIS_IN1 0x00000002 |
| #define | COMP_ACRIS_IN0 0x00000001 |
| #define | COMP_ACINTEN_IN1 0x00000002 |
| #define | COMP_ACINTEN_IN0 0x00000001 |
| #define | COMP_ACREFCTL_EN 0x00000200 |
| #define | COMP_ACREFCTL_RNG 0x00000100 |
| #define | COMP_ACREFCTL_VREF_M 0x0000000F |
| #define | COMP_ACREFCTL_VREF_S 0 |
| #define | COMP_ACSTAT0_OVAL 0x00000002 |
| #define | COMP_ACCTL0_TOEN 0x00000800 |
| #define | COMP_ACCTL0_ASRCP_M 0x00000600 |
| #define | COMP_ACCTL0_ASRCP_PIN 0x00000000 |
| #define | COMP_ACCTL0_ASRCP_PIN0 0x00000200 |
| #define | COMP_ACCTL0_ASRCP_REF 0x00000400 |
| #define | COMP_ACCTL0_TSLVAL 0x00000080 |
| #define | COMP_ACCTL0_TSEN_M 0x00000060 |
| #define | COMP_ACCTL0_TSEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL0_TSEN_FALL 0x00000020 |
| #define | COMP_ACCTL0_TSEN_RISE 0x00000040 |
| #define | COMP_ACCTL0_TSEN_BOTH 0x00000060 |
| #define | COMP_ACCTL0_ISLVAL 0x00000010 |
| #define | COMP_ACCTL0_ISEN_M 0x0000000C |
| #define | COMP_ACCTL0_ISEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL0_ISEN_FALL 0x00000004 |
| #define | COMP_ACCTL0_ISEN_RISE 0x00000008 |
| #define | COMP_ACCTL0_ISEN_BOTH 0x0000000C |
| #define | COMP_ACCTL0_CINV 0x00000002 |
| #define | COMP_ACSTAT1_OVAL 0x00000002 |
| #define | COMP_ACCTL1_TOEN 0x00000800 |
| #define | COMP_ACCTL1_ASRCP_M 0x00000600 |
| #define | COMP_ACCTL1_ASRCP_PIN 0x00000000 |
| #define | COMP_ACCTL1_ASRCP_PIN0 0x00000200 |
| #define | COMP_ACCTL1_ASRCP_REF 0x00000400 |
| #define | COMP_ACCTL1_TSLVAL 0x00000080 |
| #define | COMP_ACCTL1_TSEN_M 0x00000060 |
| #define | COMP_ACCTL1_TSEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL1_TSEN_FALL 0x00000020 |
| #define | COMP_ACCTL1_TSEN_RISE 0x00000040 |
| #define | COMP_ACCTL1_TSEN_BOTH 0x00000060 |
| #define | COMP_ACCTL1_ISLVAL 0x00000010 |
| #define | COMP_ACCTL1_ISEN_M 0x0000000C |
| #define | COMP_ACCTL1_ISEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL1_ISEN_FALL 0x00000004 |
| #define | COMP_ACCTL1_ISEN_RISE 0x00000008 |
| #define | COMP_ACCTL1_ISEN_BOTH 0x0000000C |
| #define | COMP_ACCTL1_CINV 0x00000002 |
| #define | COMP_PP_C2O 0x00040000 |
| #define | COMP_PP_C1O 0x00020000 |
| #define | COMP_PP_C0O 0x00010000 |
| #define | COMP_PP_CMP2 0x00000004 |
| #define | COMP_PP_CMP1 0x00000002 |
| #define | COMP_PP_CMP0 0x00000001 |
| #define | CAN_CTL_TEST 0x00000080 |
| #define | CAN_CTL_CCE 0x00000040 |
| #define | CAN_CTL_DAR 0x00000020 |
| #define | CAN_CTL_EIE 0x00000008 |
| #define | CAN_CTL_SIE 0x00000004 |
| #define | CAN_CTL_IE 0x00000002 |
| #define | CAN_CTL_INIT 0x00000001 |
| #define | CAN_STS_BOFF 0x00000080 |
| #define | CAN_STS_EWARN 0x00000040 |
| #define | CAN_STS_EPASS 0x00000020 |
| #define | CAN_STS_RXOK 0x00000010 |
| #define | CAN_STS_TXOK 0x00000008 |
| #define | CAN_STS_LEC_M 0x00000007 |
| #define | CAN_STS_LEC_NONE 0x00000000 |
| #define | CAN_STS_LEC_STUFF 0x00000001 |
| #define | CAN_STS_LEC_FORM 0x00000002 |
| #define | CAN_STS_LEC_ACK 0x00000003 |
| #define | CAN_STS_LEC_BIT1 0x00000004 |
| #define | CAN_STS_LEC_BIT0 0x00000005 |
| #define | CAN_STS_LEC_CRC 0x00000006 |
| #define | CAN_STS_LEC_NOEVENT 0x00000007 |
| #define | CAN_ERR_RP 0x00008000 |
| #define | CAN_ERR_REC_M 0x00007F00 |
| #define | CAN_ERR_TEC_M 0x000000FF |
| #define | CAN_ERR_REC_S 8 |
| #define | CAN_ERR_TEC_S 0 |
| #define | CAN_BIT_TSEG2_M 0x00007000 |
| #define | CAN_BIT_TSEG1_M 0x00000F00 |
| #define | CAN_BIT_SJW_M 0x000000C0 |
| #define | CAN_BIT_BRP_M 0x0000003F |
| #define | CAN_BIT_TSEG2_S 12 |
| #define | CAN_BIT_TSEG1_S 8 |
| #define | CAN_BIT_SJW_S 6 |
| #define | CAN_BIT_BRP_S 0 |
| #define | CAN_INT_INTID_M 0x0000FFFF |
| #define | CAN_INT_INTID_NONE 0x00000000 |
| #define | CAN_INT_INTID_STATUS 0x00008000 |
| #define | CAN_TST_RX 0x00000080 |
| #define | CAN_TST_TX_M 0x00000060 |
| #define | CAN_TST_TX_CANCTL 0x00000000 |
| #define | CAN_TST_TX_SAMPLE 0x00000020 |
| #define | CAN_TST_TX_DOMINANT 0x00000040 |
| #define | CAN_TST_TX_RECESSIVE 0x00000060 |
| #define | CAN_TST_LBACK 0x00000010 |
| #define | CAN_TST_SILENT 0x00000008 |
| #define | CAN_TST_BASIC 0x00000004 |
| #define | CAN_BRPE_BRPE_M 0x0000000F |
| #define | CAN_BRPE_BRPE_S 0 |
| #define | CAN_IF1CRQ_BUSY 0x00008000 |
| #define | CAN_IF1CRQ_MNUM_M 0x0000003F |
| #define | CAN_IF1CRQ_MNUM_S 0 |
| #define | CAN_IF1CMSK_WRNRD 0x00000080 |
| #define | CAN_IF1CMSK_MASK 0x00000040 |
| #define | CAN_IF1CMSK_ARB 0x00000020 |
| #define | CAN_IF1CMSK_CONTROL 0x00000010 |
| #define | CAN_IF1CMSK_CLRINTPND 0x00000008 |
| #define | CAN_IF1CMSK_NEWDAT 0x00000004 |
| #define | CAN_IF1CMSK_TXRQST 0x00000004 |
| #define | CAN_IF1CMSK_DATAA 0x00000002 |
| #define | CAN_IF1CMSK_DATAB 0x00000001 |
| #define | CAN_IF1MSK1_IDMSK_M 0x0000FFFF |
| #define | CAN_IF1MSK1_IDMSK_S 0 |
| #define | CAN_IF1MSK2_MXTD 0x00008000 |
| #define | CAN_IF1MSK2_MDIR 0x00004000 |
| #define | CAN_IF1MSK2_IDMSK_M 0x00001FFF |
| #define | CAN_IF1MSK2_IDMSK_S 0 |
| #define | CAN_IF1ARB1_ID_M 0x0000FFFF |
| #define | CAN_IF1ARB1_ID_S 0 |
| #define | CAN_IF1ARB2_MSGVAL 0x00008000 |
| #define | CAN_IF1ARB2_XTD 0x00004000 |
| #define | CAN_IF1ARB2_DIR 0x00002000 |
| #define | CAN_IF1ARB2_ID_M 0x00001FFF |
| #define | CAN_IF1ARB2_ID_S 0 |
| #define | CAN_IF1MCTL_NEWDAT 0x00008000 |
| #define | CAN_IF1MCTL_MSGLST 0x00004000 |
| #define | CAN_IF1MCTL_INTPND 0x00002000 |
| #define | CAN_IF1MCTL_UMASK 0x00001000 |
| #define | CAN_IF1MCTL_TXIE 0x00000800 |
| #define | CAN_IF1MCTL_RXIE 0x00000400 |
| #define | CAN_IF1MCTL_RMTEN 0x00000200 |
| #define | CAN_IF1MCTL_TXRQST 0x00000100 |
| #define | CAN_IF1MCTL_EOB 0x00000080 |
| #define | CAN_IF1MCTL_DLC_M 0x0000000F |
| #define | CAN_IF1MCTL_DLC_S 0 |
| #define | CAN_IF1DA1_DATA_M 0x0000FFFF |
| #define | CAN_IF1DA1_DATA_S 0 |
| #define | CAN_IF1DA2_DATA_M 0x0000FFFF |
| #define | CAN_IF1DA2_DATA_S 0 |
| #define | CAN_IF1DB1_DATA_M 0x0000FFFF |
| #define | CAN_IF1DB1_DATA_S 0 |
| #define | CAN_IF1DB2_DATA_M 0x0000FFFF |
| #define | CAN_IF1DB2_DATA_S 0 |
| #define | CAN_IF2CRQ_BUSY 0x00008000 |
| #define | CAN_IF2CRQ_MNUM_M 0x0000003F |
| #define | CAN_IF2CRQ_MNUM_S 0 |
| #define | CAN_IF2CMSK_WRNRD 0x00000080 |
| #define | CAN_IF2CMSK_MASK 0x00000040 |
| #define | CAN_IF2CMSK_ARB 0x00000020 |
| #define | CAN_IF2CMSK_CONTROL 0x00000010 |
| #define | CAN_IF2CMSK_CLRINTPND 0x00000008 |
| #define | CAN_IF2CMSK_NEWDAT 0x00000004 |
| #define | CAN_IF2CMSK_TXRQST 0x00000004 |
| #define | CAN_IF2CMSK_DATAA 0x00000002 |
| #define | CAN_IF2CMSK_DATAB 0x00000001 |
| #define | CAN_IF2MSK1_IDMSK_M 0x0000FFFF |
| #define | CAN_IF2MSK1_IDMSK_S 0 |
| #define | CAN_IF2MSK2_MXTD 0x00008000 |
| #define | CAN_IF2MSK2_MDIR 0x00004000 |
| #define | CAN_IF2MSK2_IDMSK_M 0x00001FFF |
| #define | CAN_IF2MSK2_IDMSK_S 0 |
| #define | CAN_IF2ARB1_ID_M 0x0000FFFF |
| #define | CAN_IF2ARB1_ID_S 0 |
| #define | CAN_IF2ARB2_MSGVAL 0x00008000 |
| #define | CAN_IF2ARB2_XTD 0x00004000 |
| #define | CAN_IF2ARB2_DIR 0x00002000 |
| #define | CAN_IF2ARB2_ID_M 0x00001FFF |
| #define | CAN_IF2ARB2_ID_S 0 |
| #define | CAN_IF2MCTL_NEWDAT 0x00008000 |
| #define | CAN_IF2MCTL_MSGLST 0x00004000 |
| #define | CAN_IF2MCTL_INTPND 0x00002000 |
| #define | CAN_IF2MCTL_UMASK 0x00001000 |
| #define | CAN_IF2MCTL_TXIE 0x00000800 |
| #define | CAN_IF2MCTL_RXIE 0x00000400 |
| #define | CAN_IF2MCTL_RMTEN 0x00000200 |
| #define | CAN_IF2MCTL_TXRQST 0x00000100 |
| #define | CAN_IF2MCTL_EOB 0x00000080 |
| #define | CAN_IF2MCTL_DLC_M 0x0000000F |
| #define | CAN_IF2MCTL_DLC_S 0 |
| #define | CAN_IF2DA1_DATA_M 0x0000FFFF |
| #define | CAN_IF2DA1_DATA_S 0 |
| #define | CAN_IF2DA2_DATA_M 0x0000FFFF |
| #define | CAN_IF2DA2_DATA_S 0 |
| #define | CAN_IF2DB1_DATA_M 0x0000FFFF |
| #define | CAN_IF2DB1_DATA_S 0 |
| #define | CAN_IF2DB2_DATA_M 0x0000FFFF |
| #define | CAN_IF2DB2_DATA_S 0 |
| #define | CAN_TXRQ1_TXRQST_M 0x0000FFFF |
| #define | CAN_TXRQ1_TXRQST_S 0 |
| #define | CAN_TXRQ2_TXRQST_M 0x0000FFFF |
| #define | CAN_TXRQ2_TXRQST_S 0 |
| #define | CAN_NWDA1_NEWDAT_M 0x0000FFFF |
| #define | CAN_NWDA1_NEWDAT_S 0 |
| #define | CAN_NWDA2_NEWDAT_M 0x0000FFFF |
| #define | CAN_NWDA2_NEWDAT_S 0 |
| #define | CAN_MSG1INT_INTPND_M 0x0000FFFF |
| #define | CAN_MSG1INT_INTPND_S 0 |
| #define | CAN_MSG2INT_INTPND_M 0x0000FFFF |
| #define | CAN_MSG2INT_INTPND_S 0 |
| #define | CAN_MSG1VAL_MSGVAL_M 0x0000FFFF |
| #define | CAN_MSG1VAL_MSGVAL_S 0 |
| #define | CAN_MSG2VAL_MSGVAL_M 0x0000FFFF |
| #define | CAN_MSG2VAL_MSGVAL_S 0 |
| #define | USB_FADDR_M 0x0000007F |
| #define | USB_FADDR_S 0 |
| #define | USB_POWER_ISOUP 0x00000080 |
| #define | USB_POWER_SOFTCONN 0x00000040 |
| #define | USB_POWER_RESET 0x00000008 |
| #define | USB_POWER_RESUME 0x00000004 |
| #define | USB_POWER_SUSPEND 0x00000002 |
| #define | USB_POWER_PWRDNPHY 0x00000001 |
| #define | USB_TXIS_EP7 0x00000080 |
| #define | USB_TXIS_EP6 0x00000040 |
| #define | USB_TXIS_EP5 0x00000020 |
| #define | USB_TXIS_EP4 0x00000010 |
| #define | USB_TXIS_EP3 0x00000008 |
| #define | USB_TXIS_EP2 0x00000004 |
| #define | USB_TXIS_EP1 0x00000002 |
| #define | USB_TXIS_EP0 0x00000001 |
| #define | USB_RXIS_EP7 0x00000080 |
| #define | USB_RXIS_EP6 0x00000040 |
| #define | USB_RXIS_EP5 0x00000020 |
| #define | USB_RXIS_EP4 0x00000010 |
| #define | USB_RXIS_EP3 0x00000008 |
| #define | USB_RXIS_EP2 0x00000004 |
| #define | USB_RXIS_EP1 0x00000002 |
| #define | USB_TXIE_EP7 0x00000080 |
| #define | USB_TXIE_EP6 0x00000040 |
| #define | USB_TXIE_EP5 0x00000020 |
| #define | USB_TXIE_EP4 0x00000010 |
| #define | USB_TXIE_EP3 0x00000008 |
| #define | USB_TXIE_EP2 0x00000004 |
| #define | USB_TXIE_EP1 0x00000002 |
| #define | USB_TXIE_EP0 0x00000001 |
| #define | USB_RXIE_EP7 0x00000080 |
| #define | USB_RXIE_EP6 0x00000040 |
| #define | USB_RXIE_EP5 0x00000020 |
| #define | USB_RXIE_EP4 0x00000010 |
| #define | USB_RXIE_EP3 0x00000008 |
| #define | USB_RXIE_EP2 0x00000004 |
| #define | USB_RXIE_EP1 0x00000002 |
| #define | USB_IS_DISCON 0x00000020 |
| #define | USB_IS_SOF 0x00000008 |
| #define | USB_IS_RESET 0x00000004 |
| #define | USB_IS_RESUME 0x00000002 |
| #define | USB_IS_SUSPEND 0x00000001 |
| #define | USB_IE_DISCON 0x00000020 |
| #define | USB_IE_SOF 0x00000008 |
| #define | USB_IE_RESET 0x00000004 |
| #define | USB_IE_RESUME 0x00000002 |
| #define | USB_IE_SUSPND 0x00000001 |
| #define | USB_FRAME_M 0x000007FF |
| #define | USB_FRAME_S 0 |
| #define | USB_EPIDX_EPIDX_M 0x0000000F |
| #define | USB_EPIDX_EPIDX_S 0 |
| #define | USB_TEST_FIFOACC 0x00000040 |
| #define | USB_TEST_FORCEFS 0x00000020 |
| #define | USB_FIFO0_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO0_EPDATA_S 0 |
| #define | USB_FIFO1_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO1_EPDATA_S 0 |
| #define | USB_FIFO2_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO2_EPDATA_S 0 |
| #define | USB_FIFO3_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO3_EPDATA_S 0 |
| #define | USB_FIFO4_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO4_EPDATA_S 0 |
| #define | USB_FIFO5_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO5_EPDATA_S 0 |
| #define | USB_FIFO6_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO6_EPDATA_S 0 |
| #define | USB_FIFO7_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO7_EPDATA_S 0 |
| #define | USB_TXFIFOSZ_DPB 0x00000010 |
| #define | USB_TXFIFOSZ_SIZE_M 0x0000000F |
| #define | USB_TXFIFOSZ_SIZE_8 0x00000000 |
| #define | USB_TXFIFOSZ_SIZE_16 0x00000001 |
| #define | USB_TXFIFOSZ_SIZE_32 0x00000002 |
| #define | USB_TXFIFOSZ_SIZE_64 0x00000003 |
| #define | USB_TXFIFOSZ_SIZE_128 0x00000004 |
| #define | USB_TXFIFOSZ_SIZE_256 0x00000005 |
| #define | USB_TXFIFOSZ_SIZE_512 0x00000006 |
| #define | USB_TXFIFOSZ_SIZE_1024 0x00000007 |
| #define | USB_TXFIFOSZ_SIZE_2048 0x00000008 |
| #define | USB_RXFIFOSZ_DPB 0x00000010 |
| #define | USB_RXFIFOSZ_SIZE_M 0x0000000F |
| #define | USB_RXFIFOSZ_SIZE_8 0x00000000 |
| #define | USB_RXFIFOSZ_SIZE_16 0x00000001 |
| #define | USB_RXFIFOSZ_SIZE_32 0x00000002 |
| #define | USB_RXFIFOSZ_SIZE_64 0x00000003 |
| #define | USB_RXFIFOSZ_SIZE_128 0x00000004 |
| #define | USB_RXFIFOSZ_SIZE_256 0x00000005 |
| #define | USB_RXFIFOSZ_SIZE_512 0x00000006 |
| #define | USB_RXFIFOSZ_SIZE_1024 0x00000007 |
| #define | USB_RXFIFOSZ_SIZE_2048 0x00000008 |
| #define | USB_TXFIFOADD_ADDR_M 0x000001FF |
| #define | USB_TXFIFOADD_ADDR_S 0 |
| #define | USB_RXFIFOADD_ADDR_M 0x000001FF |
| #define | USB_RXFIFOADD_ADDR_S 0 |
| #define | USB_CONTIM_WTCON_M 0x000000F0 |
| #define | USB_CONTIM_WTID_M 0x0000000F |
| #define | USB_CONTIM_WTCON_S 4 |
| #define | USB_CONTIM_WTID_S 0 |
| #define | USB_FSEOF_FSEOFG_M 0x000000FF |
| #define | USB_FSEOF_FSEOFG_S 0 |
| #define | USB_LSEOF_LSEOFG_M 0x000000FF |
| #define | USB_LSEOF_LSEOFG_S 0 |
| #define | USB_CSRL0_SETENDC 0x00000080 |
| #define | USB_CSRL0_RXRDYC 0x00000040 |
| #define | USB_CSRL0_STALL 0x00000020 |
| #define | USB_CSRL0_SETEND 0x00000010 |
| #define | USB_CSRL0_DATAEND 0x00000008 |
| #define | USB_CSRL0_STALLED 0x00000004 |
| #define | USB_CSRL0_TXRDY 0x00000002 |
| #define | USB_CSRL0_RXRDY 0x00000001 |
| #define | USB_CSRH0_FLUSH 0x00000001 |
| #define | USB_COUNT0_COUNT_M 0x0000007F |
| #define | USB_COUNT0_COUNT_S 0 |
| #define | USB_TXMAXP1_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP1_MAXLOAD_S 0 |
| #define | USB_TXCSRL1_CLRDT 0x00000040 |
| #define | USB_TXCSRL1_STALLED 0x00000020 |
| #define | USB_TXCSRL1_STALL 0x00000010 |
| #define | USB_TXCSRL1_FLUSH 0x00000008 |
| #define | USB_TXCSRL1_UNDRN 0x00000004 |
| #define | USB_TXCSRL1_FIFONE 0x00000002 |
| #define | USB_TXCSRL1_TXRDY 0x00000001 |
| #define | USB_TXCSRH1_AUTOSET 0x00000080 |
| #define | USB_TXCSRH1_ISO 0x00000040 |
| #define | USB_TXCSRH1_MODE 0x00000020 |
| #define | USB_TXCSRH1_DMAEN 0x00000010 |
| #define | USB_TXCSRH1_FDT 0x00000008 |
| #define | USB_TXCSRH1_DMAMOD 0x00000004 |
| #define | USB_RXMAXP1_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP1_MAXLOAD_S 0 |
| #define | USB_RXCSRL1_CLRDT 0x00000080 |
| #define | USB_RXCSRL1_STALLED 0x00000040 |
| #define | USB_RXCSRL1_STALL 0x00000020 |
| #define | USB_RXCSRL1_FLUSH 0x00000010 |
| #define | USB_RXCSRL1_DATAERR 0x00000008 |
| #define | USB_RXCSRL1_OVER 0x00000004 |
| #define | USB_RXCSRL1_FULL 0x00000002 |
| #define | USB_RXCSRL1_RXRDY 0x00000001 |
| #define | USB_RXCSRH1_AUTOCL 0x00000080 |
| #define | USB_RXCSRH1_ISO 0x00000040 |
| #define | USB_RXCSRH1_DMAEN 0x00000020 |
| #define | USB_RXCSRH1_DISNYET 0x00000010 |
| #define | USB_RXCSRH1_PIDERR 0x00000010 |
| #define | USB_RXCSRH1_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT1_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT1_COUNT_S 0 |
| #define | USB_TXMAXP2_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP2_MAXLOAD_S 0 |
| #define | USB_TXCSRL2_CLRDT 0x00000040 |
| #define | USB_TXCSRL2_STALLED 0x00000020 |
| #define | USB_TXCSRL2_STALL 0x00000010 |
| #define | USB_TXCSRL2_FLUSH 0x00000008 |
| #define | USB_TXCSRL2_UNDRN 0x00000004 |
| #define | USB_TXCSRL2_FIFONE 0x00000002 |
| #define | USB_TXCSRL2_TXRDY 0x00000001 |
| #define | USB_TXCSRH2_AUTOSET 0x00000080 |
| #define | USB_TXCSRH2_ISO 0x00000040 |
| #define | USB_TXCSRH2_MODE 0x00000020 |
| #define | USB_TXCSRH2_DMAEN 0x00000010 |
| #define | USB_TXCSRH2_FDT 0x00000008 |
| #define | USB_TXCSRH2_DMAMOD 0x00000004 |
| #define | USB_RXMAXP2_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP2_MAXLOAD_S 0 |
| #define | USB_RXCSRL2_CLRDT 0x00000080 |
| #define | USB_RXCSRL2_STALLED 0x00000040 |
| #define | USB_RXCSRL2_STALL 0x00000020 |
| #define | USB_RXCSRL2_FLUSH 0x00000010 |
| #define | USB_RXCSRL2_DATAERR 0x00000008 |
| #define | USB_RXCSRL2_OVER 0x00000004 |
| #define | USB_RXCSRL2_FULL 0x00000002 |
| #define | USB_RXCSRL2_RXRDY 0x00000001 |
| #define | USB_RXCSRH2_AUTOCL 0x00000080 |
| #define | USB_RXCSRH2_ISO 0x00000040 |
| #define | USB_RXCSRH2_DMAEN 0x00000020 |
| #define | USB_RXCSRH2_DISNYET 0x00000010 |
| #define | USB_RXCSRH2_PIDERR 0x00000010 |
| #define | USB_RXCSRH2_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT2_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT2_COUNT_S 0 |
| #define | USB_TXMAXP3_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP3_MAXLOAD_S 0 |
| #define | USB_TXCSRL3_CLRDT 0x00000040 |
| #define | USB_TXCSRL3_STALLED 0x00000020 |
| #define | USB_TXCSRL3_STALL 0x00000010 |
| #define | USB_TXCSRL3_FLUSH 0x00000008 |
| #define | USB_TXCSRL3_UNDRN 0x00000004 |
| #define | USB_TXCSRL3_FIFONE 0x00000002 |
| #define | USB_TXCSRL3_TXRDY 0x00000001 |
| #define | USB_TXCSRH3_AUTOSET 0x00000080 |
| #define | USB_TXCSRH3_ISO 0x00000040 |
| #define | USB_TXCSRH3_MODE 0x00000020 |
| #define | USB_TXCSRH3_DMAEN 0x00000010 |
| #define | USB_TXCSRH3_FDT 0x00000008 |
| #define | USB_TXCSRH3_DMAMOD 0x00000004 |
| #define | USB_RXMAXP3_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP3_MAXLOAD_S 0 |
| #define | USB_RXCSRL3_CLRDT 0x00000080 |
| #define | USB_RXCSRL3_STALLED 0x00000040 |
| #define | USB_RXCSRL3_STALL 0x00000020 |
| #define | USB_RXCSRL3_FLUSH 0x00000010 |
| #define | USB_RXCSRL3_DATAERR 0x00000008 |
| #define | USB_RXCSRL3_OVER 0x00000004 |
| #define | USB_RXCSRL3_FULL 0x00000002 |
| #define | USB_RXCSRL3_RXRDY 0x00000001 |
| #define | USB_RXCSRH3_AUTOCL 0x00000080 |
| #define | USB_RXCSRH3_ISO 0x00000040 |
| #define | USB_RXCSRH3_DMAEN 0x00000020 |
| #define | USB_RXCSRH3_DISNYET 0x00000010 |
| #define | USB_RXCSRH3_PIDERR 0x00000010 |
| #define | USB_RXCSRH3_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT3_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT3_COUNT_S 0 |
| #define | USB_TXMAXP4_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP4_MAXLOAD_S 0 |
| #define | USB_TXCSRL4_CLRDT 0x00000040 |
| #define | USB_TXCSRL4_STALLED 0x00000020 |
| #define | USB_TXCSRL4_STALL 0x00000010 |
| #define | USB_TXCSRL4_FLUSH 0x00000008 |
| #define | USB_TXCSRL4_UNDRN 0x00000004 |
| #define | USB_TXCSRL4_FIFONE 0x00000002 |
| #define | USB_TXCSRL4_TXRDY 0x00000001 |
| #define | USB_TXCSRH4_AUTOSET 0x00000080 |
| #define | USB_TXCSRH4_ISO 0x00000040 |
| #define | USB_TXCSRH4_MODE 0x00000020 |
| #define | USB_TXCSRH4_DMAEN 0x00000010 |
| #define | USB_TXCSRH4_FDT 0x00000008 |
| #define | USB_TXCSRH4_DMAMOD 0x00000004 |
| #define | USB_RXMAXP4_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP4_MAXLOAD_S 0 |
| #define | USB_RXCSRL4_CLRDT 0x00000080 |
| #define | USB_RXCSRL4_STALLED 0x00000040 |
| #define | USB_RXCSRL4_STALL 0x00000020 |
| #define | USB_RXCSRL4_FLUSH 0x00000010 |
| #define | USB_RXCSRL4_DATAERR 0x00000008 |
| #define | USB_RXCSRL4_OVER 0x00000004 |
| #define | USB_RXCSRL4_FULL 0x00000002 |
| #define | USB_RXCSRL4_RXRDY 0x00000001 |
| #define | USB_RXCSRH4_AUTOCL 0x00000080 |
| #define | USB_RXCSRH4_ISO 0x00000040 |
| #define | USB_RXCSRH4_DMAEN 0x00000020 |
| #define | USB_RXCSRH4_DISNYET 0x00000010 |
| #define | USB_RXCSRH4_PIDERR 0x00000010 |
| #define | USB_RXCSRH4_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT4_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT4_COUNT_S 0 |
| #define | USB_TXMAXP5_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP5_MAXLOAD_S 0 |
| #define | USB_TXCSRL5_CLRDT 0x00000040 |
| #define | USB_TXCSRL5_STALLED 0x00000020 |
| #define | USB_TXCSRL5_STALL 0x00000010 |
| #define | USB_TXCSRL5_FLUSH 0x00000008 |
| #define | USB_TXCSRL5_UNDRN 0x00000004 |
| #define | USB_TXCSRL5_FIFONE 0x00000002 |
| #define | USB_TXCSRL5_TXRDY 0x00000001 |
| #define | USB_TXCSRH5_AUTOSET 0x00000080 |
| #define | USB_TXCSRH5_ISO 0x00000040 |
| #define | USB_TXCSRH5_MODE 0x00000020 |
| #define | USB_TXCSRH5_DMAEN 0x00000010 |
| #define | USB_TXCSRH5_FDT 0x00000008 |
| #define | USB_TXCSRH5_DMAMOD 0x00000004 |
| #define | USB_RXMAXP5_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP5_MAXLOAD_S 0 |
| #define | USB_RXCSRL5_CLRDT 0x00000080 |
| #define | USB_RXCSRL5_STALLED 0x00000040 |
| #define | USB_RXCSRL5_STALL 0x00000020 |
| #define | USB_RXCSRL5_FLUSH 0x00000010 |
| #define | USB_RXCSRL5_DATAERR 0x00000008 |
| #define | USB_RXCSRL5_OVER 0x00000004 |
| #define | USB_RXCSRL5_FULL 0x00000002 |
| #define | USB_RXCSRL5_RXRDY 0x00000001 |
| #define | USB_RXCSRH5_AUTOCL 0x00000080 |
| #define | USB_RXCSRH5_ISO 0x00000040 |
| #define | USB_RXCSRH5_DMAEN 0x00000020 |
| #define | USB_RXCSRH5_DISNYET 0x00000010 |
| #define | USB_RXCSRH5_PIDERR 0x00000010 |
| #define | USB_RXCSRH5_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT5_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT5_COUNT_S 0 |
| #define | USB_TXMAXP6_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP6_MAXLOAD_S 0 |
| #define | USB_TXCSRL6_CLRDT 0x00000040 |
| #define | USB_TXCSRL6_STALLED 0x00000020 |
| #define | USB_TXCSRL6_STALL 0x00000010 |
| #define | USB_TXCSRL6_FLUSH 0x00000008 |
| #define | USB_TXCSRL6_UNDRN 0x00000004 |
| #define | USB_TXCSRL6_FIFONE 0x00000002 |
| #define | USB_TXCSRL6_TXRDY 0x00000001 |
| #define | USB_TXCSRH6_AUTOSET 0x00000080 |
| #define | USB_TXCSRH6_ISO 0x00000040 |
| #define | USB_TXCSRH6_MODE 0x00000020 |
| #define | USB_TXCSRH6_DMAEN 0x00000010 |
| #define | USB_TXCSRH6_FDT 0x00000008 |
| #define | USB_TXCSRH6_DMAMOD 0x00000004 |
| #define | USB_RXMAXP6_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP6_MAXLOAD_S 0 |
| #define | USB_RXCSRL6_CLRDT 0x00000080 |
| #define | USB_RXCSRL6_STALLED 0x00000040 |
| #define | USB_RXCSRL6_STALL 0x00000020 |
| #define | USB_RXCSRL6_FLUSH 0x00000010 |
| #define | USB_RXCSRL6_DATAERR 0x00000008 |
| #define | USB_RXCSRL6_OVER 0x00000004 |
| #define | USB_RXCSRL6_FULL 0x00000002 |
| #define | USB_RXCSRL6_RXRDY 0x00000001 |
| #define | USB_RXCSRH6_AUTOCL 0x00000080 |
| #define | USB_RXCSRH6_ISO 0x00000040 |
| #define | USB_RXCSRH6_DMAEN 0x00000020 |
| #define | USB_RXCSRH6_DISNYET 0x00000010 |
| #define | USB_RXCSRH6_PIDERR 0x00000010 |
| #define | USB_RXCSRH6_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT6_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT6_COUNT_S 0 |
| #define | USB_TXMAXP7_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP7_MAXLOAD_S 0 |
| #define | USB_TXCSRL7_CLRDT 0x00000040 |
| #define | USB_TXCSRL7_STALLED 0x00000020 |
| #define | USB_TXCSRL7_STALL 0x00000010 |
| #define | USB_TXCSRL7_FLUSH 0x00000008 |
| #define | USB_TXCSRL7_UNDRN 0x00000004 |
| #define | USB_TXCSRL7_FIFONE 0x00000002 |
| #define | USB_TXCSRL7_TXRDY 0x00000001 |
| #define | USB_TXCSRH7_AUTOSET 0x00000080 |
| #define | USB_TXCSRH7_ISO 0x00000040 |
| #define | USB_TXCSRH7_MODE 0x00000020 |
| #define | USB_TXCSRH7_DMAEN 0x00000010 |
| #define | USB_TXCSRH7_FDT 0x00000008 |
| #define | USB_TXCSRH7_DMAMOD 0x00000004 |
| #define | USB_RXMAXP7_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP7_MAXLOAD_S 0 |
| #define | USB_RXCSRL7_CLRDT 0x00000080 |
| #define | USB_RXCSRL7_STALLED 0x00000040 |
| #define | USB_RXCSRL7_STALL 0x00000020 |
| #define | USB_RXCSRL7_FLUSH 0x00000010 |
| #define | USB_RXCSRL7_DATAERR 0x00000008 |
| #define | USB_RXCSRL7_OVER 0x00000004 |
| #define | USB_RXCSRL7_FULL 0x00000002 |
| #define | USB_RXCSRL7_RXRDY 0x00000001 |
| #define | USB_RXCSRH7_AUTOCL 0x00000080 |
| #define | USB_RXCSRH7_ISO 0x00000040 |
| #define | USB_RXCSRH7_DMAEN 0x00000020 |
| #define | USB_RXCSRH7_PIDERR 0x00000010 |
| #define | USB_RXCSRH7_DISNYET 0x00000010 |
| #define | USB_RXCSRH7_DMAMOD 0x00000008 |
| #define | USB_RXCOUNT7_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT7_COUNT_S 0 |
| #define | USB_RXDPKTBUFDIS_EP7 0x00000080 |
| #define | USB_RXDPKTBUFDIS_EP6 0x00000040 |
| #define | USB_RXDPKTBUFDIS_EP5 0x00000020 |
| #define | USB_RXDPKTBUFDIS_EP4 0x00000010 |
| #define | USB_RXDPKTBUFDIS_EP3 0x00000008 |
| #define | USB_RXDPKTBUFDIS_EP2 0x00000004 |
| #define | USB_RXDPKTBUFDIS_EP1 0x00000002 |
| #define | USB_TXDPKTBUFDIS_EP7 0x00000080 |
| #define | USB_TXDPKTBUFDIS_EP6 0x00000040 |
| #define | USB_TXDPKTBUFDIS_EP5 0x00000020 |
| #define | USB_TXDPKTBUFDIS_EP4 0x00000010 |
| #define | USB_TXDPKTBUFDIS_EP3 0x00000008 |
| #define | USB_TXDPKTBUFDIS_EP2 0x00000004 |
| #define | USB_TXDPKTBUFDIS_EP1 0x00000002 |
| #define | USB_DRRIS_RESUME 0x00000001 |
| #define | USB_DRIM_RESUME 0x00000001 |
| #define | USB_DRISC_RESUME 0x00000001 |
| #define | USB_DMASEL_DMACTX_M 0x00F00000 |
| #define | USB_DMASEL_DMACRX_M 0x000F0000 |
| #define | USB_DMASEL_DMABTX_M 0x0000F000 |
| #define | USB_DMASEL_DMABRX_M 0x00000F00 |
| #define | USB_DMASEL_DMAATX_M 0x000000F0 |
| #define | USB_DMASEL_DMAARX_M 0x0000000F |
| #define | USB_DMASEL_DMACTX_S 20 |
| #define | USB_DMASEL_DMACRX_S 16 |
| #define | USB_DMASEL_DMABTX_S 12 |
| #define | USB_DMASEL_DMABRX_S 8 |
| #define | USB_DMASEL_DMAATX_S 4 |
| #define | USB_DMASEL_DMAARX_S 0 |
| #define | USB_PP_ECNT_M 0x0000FF00 |
| #define | USB_PP_USB_M 0x000000C0 |
| #define | USB_PP_USB_DEVICE 0x00000040 |
| #define | USB_PP_USB_HOSTDEVICE 0x00000080 |
| #define | USB_PP_USB_OTG 0x000000C0 |
| #define | USB_PP_PHY 0x00000010 |
| #define | USB_PP_TYPE_M 0x0000000F |
| #define | USB_PP_TYPE_0 0x00000000 |
| #define | USB_PP_ECNT_S 8 |
| #define | EEPROM_EESIZE_BLKCNT_M 0x07FF0000 |
| #define | EEPROM_EESIZE_WORDCNT_M 0x0000FFFF |
| #define | EEPROM_EESIZE_BLKCNT_S 16 |
| #define | EEPROM_EESIZE_WORDCNT_S 0 |
| #define | EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF |
| #define | EEPROM_EEBLOCK_BLOCK_S 0 |
| #define | EEPROM_EEOFFSET_OFFSET_M 0x0000000F |
| #define | EEPROM_EEOFFSET_OFFSET_S 0 |
| #define | EEPROM_EERDWR_VALUE_M 0xFFFFFFFF |
| #define | EEPROM_EERDWR_VALUE_S 0 |
| #define | EEPROM_EERDWRINC_VALUE_M 0xFFFFFFFF |
| #define | EEPROM_EERDWRINC_VALUE_S 0 |
| #define | EEPROM_EEDONE_INVPL 0x00000100 |
| #define | EEPROM_EEDONE_WRBUSY 0x00000020 |
| #define | EEPROM_EEDONE_NOPERM 0x00000010 |
| #define | EEPROM_EEDONE_WKCOPY 0x00000008 |
| #define | EEPROM_EEDONE_WKERASE 0x00000004 |
| #define | EEPROM_EEDONE_WORKING 0x00000001 |
| #define | EEPROM_EESUPP_PRETRY 0x00000008 |
| #define | EEPROM_EESUPP_ERETRY 0x00000004 |
| #define | EEPROM_EESUPP_EREQ 0x00000002 |
| #define | EEPROM_EESUPP_START 0x00000001 |
| #define | EEPROM_EEUNLOCK_UNLOCK_M 0xFFFFFFFF |
| #define | EEPROM_EEPROT_ACC 0x00000008 |
| #define | EEPROM_EEPROT_PROT_M 0x00000007 |
| #define | EEPROM_EEPROT_PROT_RWNPW 0x00000000 |
| #define | EEPROM_EEPROT_PROT_RWPW 0x00000001 |
| #define | EEPROM_EEPROT_PROT_RONPW 0x00000002 |
| #define | EEPROM_EEPASS0_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS0_PASS_S 0 |
| #define | EEPROM_EEPASS1_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS1_PASS_S 0 |
| #define | EEPROM_EEPASS2_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS2_PASS_S 0 |
| #define | EEPROM_EEINT_INT 0x00000001 |
| #define | EEPROM_EEHIDE_HN_M 0xFFFFFFFE |
| #define | EEPROM_EEDBGME_KEY_M 0xFFFF0000 |
| #define | EEPROM_EEDBGME_ME 0x00000001 |
| #define | EEPROM_EEDBGME_KEY_S 16 |
| #define | EEPROM_PP_SIZE_M 0x0000001F |
| #define | EEPROM_PP_SIZE_S 0 |
| #define | SYSEXC_RIS_FPIXCRIS 0x00000020 |
| #define | SYSEXC_RIS_FPOFCRIS 0x00000010 |
| #define | SYSEXC_RIS_FPUFCRIS 0x00000008 |
| #define | SYSEXC_RIS_FPIOCRIS 0x00000004 |
| #define | SYSEXC_RIS_FPDZCRIS 0x00000002 |
| #define | SYSEXC_RIS_FPIDCRIS 0x00000001 |
| #define | SYSEXC_IM_FPIXCIM 0x00000020 |
| #define | SYSEXC_IM_FPOFCIM 0x00000010 |
| #define | SYSEXC_IM_FPUFCIM 0x00000008 |
| #define | SYSEXC_IM_FPIOCIM 0x00000004 |
| #define | SYSEXC_IM_FPDZCIM 0x00000002 |
| #define | SYSEXC_IM_FPIDCIM 0x00000001 |
| #define | SYSEXC_MIS_FPIXCMIS 0x00000020 |
| #define | SYSEXC_MIS_FPOFCMIS 0x00000010 |
| #define | SYSEXC_MIS_FPUFCMIS 0x00000008 |
| #define | SYSEXC_MIS_FPIOCMIS 0x00000004 |
| #define | SYSEXC_MIS_FPDZCMIS 0x00000002 |
| #define | SYSEXC_MIS_FPIDCMIS 0x00000001 |
| #define | SYSEXC_IC_FPIXCIC 0x00000020 |
| #define | SYSEXC_IC_FPOFCIC 0x00000010 |
| #define | SYSEXC_IC_FPUFCIC 0x00000008 |
| #define | SYSEXC_IC_FPIOCIC 0x00000004 |
| #define | SYSEXC_IC_FPDZCIC 0x00000002 |
| #define | SYSEXC_IC_FPIDCIC 0x00000001 |
| #define | HIB_RTCC_M 0xFFFFFFFF |
| #define | HIB_RTCC_S 0 |
| #define | HIB_RTCM0_M 0xFFFFFFFF |
| #define | HIB_RTCM0_S 0 |
| #define | HIB_RTCLD_M 0xFFFFFFFF |
| #define | HIB_RTCLD_S 0 |
| #define | HIB_CTL_WRC 0x80000000 |
| #define | HIB_CTL_OSCDRV 0x00020000 |
| #define | HIB_CTL_OSCBYP 0x00010000 |
| #define | HIB_CTL_VBATSEL_M 0x00006000 |
| #define | HIB_CTL_VBATSEL_1_9V 0x00000000 |
| #define | HIB_CTL_VBATSEL_2_1V 0x00002000 |
| #define | HIB_CTL_VBATSEL_2_3V 0x00004000 |
| #define | HIB_CTL_VBATSEL_2_5V 0x00006000 |
| #define | HIB_CTL_BATCHK 0x00000400 |
| #define | HIB_CTL_BATWKEN 0x00000200 |
| #define | HIB_CTL_VDD3ON 0x00000100 |
| #define | HIB_CTL_VABORT 0x00000080 |
| #define | HIB_CTL_CLK32EN 0x00000040 |
| #define | HIB_CTL_LOWBATEN 0x00000020 |
| #define | HIB_CTL_PINWEN 0x00000010 |
| #define | HIB_CTL_RTCWEN 0x00000008 |
| #define | HIB_CTL_HIBREQ 0x00000002 |
| #define | HIB_CTL_RTCEN 0x00000001 |
| #define | HIB_IM_WC 0x00000010 |
| #define | HIB_IM_EXTW 0x00000008 |
| #define | HIB_IM_LOWBAT 0x00000004 |
| #define | HIB_IM_RTCALT0 0x00000001 |
| #define | HIB_RIS_WC 0x00000010 |
| #define | HIB_RIS_EXTW 0x00000008 |
| #define | HIB_RIS_LOWBAT 0x00000004 |
| #define | HIB_RIS_RTCALT0 0x00000001 |
| #define | HIB_MIS_WC 0x00000010 |
| #define | HIB_MIS_EXTW 0x00000008 |
| #define | HIB_MIS_LOWBAT 0x00000004 |
| #define | HIB_MIS_RTCALT0 0x00000001 |
| #define | HIB_IC_WC 0x00000010 |
| #define | HIB_IC_EXTW 0x00000008 |
| #define | HIB_IC_LOWBAT 0x00000004 |
| #define | HIB_IC_RTCALT0 0x00000001 |
| #define | HIB_RTCT_TRIM_M 0x0000FFFF |
| #define | HIB_RTCT_TRIM_S 0 |
| #define | HIB_RTCSS_RTCSSM_M 0x7FFF0000 |
| #define | HIB_RTCSS_RTCSSC_M 0x00007FFF |
| #define | HIB_RTCSS_RTCSSM_S 16 |
| #define | HIB_RTCSS_RTCSSC_S 0 |
| #define | HIB_DATA_RTD_M 0xFFFFFFFF |
| #define | HIB_DATA_RTD_S 0 |
| #define | FLASH_FMA_OFFSET_M 0x0003FFFF |
| #define | FLASH_FMA_OFFSET_S 0 |
| #define | FLASH_FMD_DATA_M 0xFFFFFFFF |
| #define | FLASH_FMD_DATA_S 0 |
| #define | FLASH_FMC_WRKEY 0xA4420000 |
| #define | FLASH_FMC_COMT 0x00000008 |
| #define | FLASH_FMC_MERASE 0x00000004 |
| #define | FLASH_FMC_ERASE 0x00000002 |
| #define | FLASH_FMC_WRITE 0x00000001 |
| #define | FLASH_FCRIS_PROGRIS 0x00002000 |
| #define | FLASH_FCRIS_ERRIS 0x00000800 |
| #define | FLASH_FCRIS_INVDRIS 0x00000400 |
| #define | FLASH_FCRIS_VOLTRIS 0x00000200 |
| #define | FLASH_FCRIS_ERIS 0x00000004 |
| #define | FLASH_FCRIS_PRIS 0x00000002 |
| #define | FLASH_FCRIS_ARIS 0x00000001 |
| #define | FLASH_FCIM_PROGMASK 0x00002000 |
| #define | FLASH_FCIM_ERMASK 0x00000800 |
| #define | FLASH_FCIM_INVDMASK 0x00000400 |
| #define | FLASH_FCIM_VOLTMASK 0x00000200 |
| #define | FLASH_FCIM_EMASK 0x00000004 |
| #define | FLASH_FCIM_PMASK 0x00000002 |
| #define | FLASH_FCIM_AMASK 0x00000001 |
| #define | FLASH_FCMISC_PROGMISC 0x00002000 |
| #define | FLASH_FCMISC_ERMISC 0x00000800 |
| #define | FLASH_FCMISC_INVDMISC 0x00000400 |
| #define | FLASH_FCMISC_VOLTMISC 0x00000200 |
| #define | FLASH_FCMISC_EMISC 0x00000004 |
| #define | FLASH_FCMISC_PMISC 0x00000002 |
| #define | FLASH_FCMISC_AMISC 0x00000001 |
| #define | FLASH_FMC2_WRKEY 0xA4420000 |
| #define | FLASH_FMC2_WRBUF 0x00000001 |
| #define | FLASH_FWBVAL_FWB_M 0xFFFFFFFF |
| #define | FLASH_FWBN_DATA_M 0xFFFFFFFF |
| #define | FLASH_FSIZE_SIZE_M 0x0000FFFF |
| #define | FLASH_FSIZE_SIZE_8KB 0x00000003 |
| #define | FLASH_FSIZE_SIZE_16KB 0x00000007 |
| #define | FLASH_FSIZE_SIZE_32KB 0x0000000F |
| #define | FLASH_FSIZE_SIZE_64KB 0x0000001F |
| #define | FLASH_FSIZE_SIZE_96KB 0x0000002F |
| #define | FLASH_FSIZE_SIZE_128KB 0x0000003F |
| #define | FLASH_FSIZE_SIZE_192KB 0x0000005F |
| #define | FLASH_FSIZE_SIZE_256KB 0x0000007F |
| #define | FLASH_SSIZE_SIZE_M 0x0000FFFF |
| #define | FLASH_SSIZE_SIZE_2KB 0x00000007 |
| #define | FLASH_SSIZE_SIZE_4KB 0x0000000F |
| #define | FLASH_SSIZE_SIZE_6KB 0x00000017 |
| #define | FLASH_SSIZE_SIZE_8KB 0x0000001F |
| #define | FLASH_SSIZE_SIZE_12KB 0x0000002F |
| #define | FLASH_SSIZE_SIZE_16KB 0x0000003F |
| #define | FLASH_SSIZE_SIZE_20KB 0x0000004F |
| #define | FLASH_SSIZE_SIZE_24KB 0x0000005F |
| #define | FLASH_SSIZE_SIZE_32KB 0x0000007F |
| #define | FLASH_ROMSWMAP_SAFERTOS 0x00000001 |
| #define | FLASH_RMCTL_BA 0x00000001 |
| #define | FLASH_BOOTCFG_NW 0x80000000 |
| #define | FLASH_BOOTCFG_PORT_M 0x0000E000 |
| #define | FLASH_BOOTCFG_PORT_A 0x00000000 |
| #define | FLASH_BOOTCFG_PORT_B 0x00002000 |
| #define | FLASH_BOOTCFG_PORT_C 0x00004000 |
| #define | FLASH_BOOTCFG_PORT_D 0x00006000 |
| #define | FLASH_BOOTCFG_PORT_E 0x00008000 |
| #define | FLASH_BOOTCFG_PORT_F 0x0000A000 |
| #define | FLASH_BOOTCFG_PORT_G 0x0000C000 |
| #define | FLASH_BOOTCFG_PORT_H 0x0000E000 |
| #define | FLASH_BOOTCFG_PIN_M 0x00001C00 |
| #define | FLASH_BOOTCFG_PIN_0 0x00000000 |
| #define | FLASH_BOOTCFG_PIN_1 0x00000400 |
| #define | FLASH_BOOTCFG_PIN_2 0x00000800 |
| #define | FLASH_BOOTCFG_PIN_3 0x00000C00 |
| #define | FLASH_BOOTCFG_PIN_4 0x00001000 |
| #define | FLASH_BOOTCFG_PIN_5 0x00001400 |
| #define | FLASH_BOOTCFG_PIN_6 0x00001800 |
| #define | FLASH_BOOTCFG_PIN_7 0x00001C00 |
| #define | FLASH_BOOTCFG_POL 0x00000200 |
| #define | FLASH_BOOTCFG_EN 0x00000100 |
| #define | FLASH_BOOTCFG_DBG1 0x00000002 |
| #define | FLASH_BOOTCFG_DBG0 0x00000001 |
| #define | FLASH_USERREG0_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG0_DATA_S 0 |
| #define | FLASH_USERREG1_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG1_DATA_S 0 |
| #define | FLASH_USERREG2_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG2_DATA_S 0 |
| #define | FLASH_USERREG3_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG3_DATA_S 0 |
| #define | SYSCTL_DID0_VER_M 0x70000000 |
| #define | SYSCTL_DID0_VER_1 0x10000000 |
| #define | SYSCTL_DID0_CLASS_M 0x00FF0000 |
| #define | SYSCTL_DID0_CLASS_BLIZZARD 0x00050000 |
| #define | SYSCTL_DID0_MAJ_M 0x0000FF00 |
| #define | SYSCTL_DID0_MAJ_REVA 0x00000000 |
| #define | SYSCTL_DID0_MAJ_REVB 0x00000100 |
| #define | SYSCTL_DID0_MAJ_REVC 0x00000200 |
| #define | SYSCTL_DID0_MIN_M 0x000000FF |
| #define | SYSCTL_DID0_MIN_0 0x00000000 |
| #define | SYSCTL_DID0_MIN_1 0x00000001 |
| #define | SYSCTL_DID0_MIN_2 0x00000002 |
| #define | SYSCTL_DID1_VER_M 0xF0000000 |
| #define | SYSCTL_DID1_VER_0 0x00000000 |
| #define | SYSCTL_DID1_VER_1 0x10000000 |
| #define | SYSCTL_DID1_FAM_M 0x0F000000 |
| #define | SYSCTL_DID1_FAM_STELLARIS 0x00000000 |
| #define | SYSCTL_DID1_PRTNO_M 0x00FF0000 |
| #define | SYSCTL_DID1_PRTNO_LM4F120H5QR 0x00040000 |
| #define | SYSCTL_DID1_PINCNT_M 0x0000E000 |
| #define | SYSCTL_DID1_PINCNT_28 0x00000000 |
| #define | SYSCTL_DID1_PINCNT_48 0x00002000 |
| #define | SYSCTL_DID1_PINCNT_100 0x00004000 |
| #define | SYSCTL_DID1_PINCNT_64 0x00006000 |
| #define | SYSCTL_DID1_PINCNT_144 0x00008000 |
| #define | SYSCTL_DID1_PINCNT_157 0x0000A000 |
| #define | SYSCTL_DID1_TEMP_M 0x000000E0 |
| #define | SYSCTL_DID1_TEMP_C 0x00000000 |
| #define | SYSCTL_DID1_TEMP_I 0x00000020 |
| #define | SYSCTL_DID1_TEMP_E 0x00000040 |
| #define | SYSCTL_DID1_PKG_M 0x00000018 |
| #define | SYSCTL_DID1_PKG_SOIC 0x00000000 |
| #define | SYSCTL_DID1_PKG_QFP 0x00000008 |
| #define | SYSCTL_DID1_PKG_BGA 0x00000010 |
| #define | SYSCTL_DID1_ROHS 0x00000004 |
| #define | SYSCTL_DID1_QUAL_M 0x00000003 |
| #define | SYSCTL_DID1_QUAL_ES 0x00000000 |
| #define | SYSCTL_DID1_QUAL_PP 0x00000001 |
| #define | SYSCTL_DID1_QUAL_FQ 0x00000002 |
| #define | SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 |
| #define | SYSCTL_DC0_SRAMSZ_2KB 0x00070000 |
| #define | SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 |
| #define | SYSCTL_DC0_SRAMSZ_6KB 0x00170000 |
| #define | SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 |
| #define | SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 |
| #define | SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 |
| #define | SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 |
| #define | SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 |
| #define | SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 |
| #define | SYSCTL_DC0_FLASHSZ_M 0x0000FFFF |
| #define | SYSCTL_DC0_FLASHSZ_8KB 0x00000003 |
| #define | SYSCTL_DC0_FLASHSZ_16KB 0x00000007 |
| #define | SYSCTL_DC0_FLASHSZ_32KB 0x0000000F |
| #define | SYSCTL_DC0_FLASHSZ_64KB 0x0000001F |
| #define | SYSCTL_DC0_FLASHSZ_96KB 0x0000002F |
| #define | SYSCTL_DC0_FLASHSZ_128K 0x0000003F |
| #define | SYSCTL_DC0_FLASHSZ_192K 0x0000005F |
| #define | SYSCTL_DC0_FLASHSZ_256K 0x0000007F |
| #define | SYSCTL_DC0_SRAMSZ_S 16 |
| #define | SYSCTL_DC0_FLASHSZ_S 0 |
| #define | SYSCTL_DC1_WDT1 0x10000000 |
| #define | SYSCTL_DC1_CAN1 0x02000000 |
| #define | SYSCTL_DC1_CAN0 0x01000000 |
| #define | SYSCTL_DC1_PWM1 0x00200000 |
| #define | SYSCTL_DC1_PWM0 0x00100000 |
| #define | SYSCTL_DC1_ADC1 0x00020000 |
| #define | SYSCTL_DC1_ADC0 0x00010000 |
| #define | SYSCTL_DC1_MINSYSDIV_M 0x0000F000 |
| #define | SYSCTL_DC1_MINSYSDIV_100 0x00001000 |
| #define | SYSCTL_DC1_MINSYSDIV_66 0x00002000 |
| #define | SYSCTL_DC1_MINSYSDIV_50 0x00003000 |
| #define | SYSCTL_DC1_MINSYSDIV_40 0x00004000 |
| #define | SYSCTL_DC1_MINSYSDIV_25 0x00007000 |
| #define | SYSCTL_DC1_MINSYSDIV_20 0x00009000 |
| #define | SYSCTL_DC1_ADC1SPD_M 0x00000C00 |
| #define | SYSCTL_DC1_ADC1SPD_125K 0x00000000 |
| #define | SYSCTL_DC1_ADC1SPD_250K 0x00000400 |
| #define | SYSCTL_DC1_ADC1SPD_500K 0x00000800 |
| #define | SYSCTL_DC1_ADC1SPD_1M 0x00000C00 |
| #define | SYSCTL_DC1_ADC0SPD_M 0x00000300 |
| #define | SYSCTL_DC1_ADC0SPD_125K 0x00000000 |
| #define | SYSCTL_DC1_ADC0SPD_250K 0x00000100 |
| #define | SYSCTL_DC1_ADC0SPD_500K 0x00000200 |
| #define | SYSCTL_DC1_ADC0SPD_1M 0x00000300 |
| #define | SYSCTL_DC1_MPU 0x00000080 |
| #define | SYSCTL_DC1_HIB 0x00000040 |
| #define | SYSCTL_DC1_TEMP 0x00000020 |
| #define | SYSCTL_DC1_PLL 0x00000010 |
| #define | SYSCTL_DC1_WDT0 0x00000008 |
| #define | SYSCTL_DC1_SWO 0x00000004 |
| #define | SYSCTL_DC1_SWD 0x00000002 |
| #define | SYSCTL_DC1_JTAG 0x00000001 |
| #define | SYSCTL_DC2_EPI0 0x40000000 |
| #define | SYSCTL_DC2_I2S0 0x10000000 |
| #define | SYSCTL_DC2_COMP2 0x04000000 |
| #define | SYSCTL_DC2_COMP1 0x02000000 |
| #define | SYSCTL_DC2_COMP0 0x01000000 |
| #define | SYSCTL_DC2_TIMER3 0x00080000 |
| #define | SYSCTL_DC2_TIMER2 0x00040000 |
| #define | SYSCTL_DC2_TIMER1 0x00020000 |
| #define | SYSCTL_DC2_TIMER0 0x00010000 |
| #define | SYSCTL_DC2_I2C1HS 0x00008000 |
| #define | SYSCTL_DC2_I2C1 0x00004000 |
| #define | SYSCTL_DC2_I2C0HS 0x00002000 |
| #define | SYSCTL_DC2_I2C0 0x00001000 |
| #define | SYSCTL_DC2_QEI1 0x00000200 |
| #define | SYSCTL_DC2_QEI0 0x00000100 |
| #define | SYSCTL_DC2_SSI1 0x00000020 |
| #define | SYSCTL_DC2_SSI0 0x00000010 |
| #define | SYSCTL_DC2_UART2 0x00000004 |
| #define | SYSCTL_DC2_UART1 0x00000002 |
| #define | SYSCTL_DC2_UART0 0x00000001 |
| #define | SYSCTL_DC3_32KHZ 0x80000000 |
| #define | SYSCTL_DC3_CCP5 0x20000000 |
| #define | SYSCTL_DC3_CCP4 0x10000000 |
| #define | SYSCTL_DC3_CCP3 0x08000000 |
| #define | SYSCTL_DC3_CCP2 0x04000000 |
| #define | SYSCTL_DC3_CCP1 0x02000000 |
| #define | SYSCTL_DC3_CCP0 0x01000000 |
| #define | SYSCTL_DC3_ADC0AIN7 0x00800000 |
| #define | SYSCTL_DC3_ADC0AIN6 0x00400000 |
| #define | SYSCTL_DC3_ADC0AIN5 0x00200000 |
| #define | SYSCTL_DC3_ADC0AIN4 0x00100000 |
| #define | SYSCTL_DC3_ADC0AIN3 0x00080000 |
| #define | SYSCTL_DC3_ADC0AIN2 0x00040000 |
| #define | SYSCTL_DC3_ADC0AIN1 0x00020000 |
| #define | SYSCTL_DC3_ADC0AIN0 0x00010000 |
| #define | SYSCTL_DC3_PWMFAULT 0x00008000 |
| #define | SYSCTL_DC3_C2O 0x00004000 |
| #define | SYSCTL_DC3_C2PLUS 0x00002000 |
| #define | SYSCTL_DC3_C2MINUS 0x00001000 |
| #define | SYSCTL_DC3_C1O 0x00000800 |
| #define | SYSCTL_DC3_C1PLUS 0x00000400 |
| #define | SYSCTL_DC3_C1MINUS 0x00000200 |
| #define | SYSCTL_DC3_C0O 0x00000100 |
| #define | SYSCTL_DC3_C0PLUS 0x00000080 |
| #define | SYSCTL_DC3_C0MINUS 0x00000040 |
| #define | SYSCTL_DC3_PWM5 0x00000020 |
| #define | SYSCTL_DC3_PWM4 0x00000010 |
| #define | SYSCTL_DC3_PWM3 0x00000008 |
| #define | SYSCTL_DC3_PWM2 0x00000004 |
| #define | SYSCTL_DC3_PWM1 0x00000002 |
| #define | SYSCTL_DC3_PWM0 0x00000001 |
| #define | SYSCTL_DC4_EPHY0 0x40000000 |
| #define | SYSCTL_DC4_EMAC0 0x10000000 |
| #define | SYSCTL_DC4_E1588 0x01000000 |
| #define | SYSCTL_DC4_PICAL 0x00040000 |
| #define | SYSCTL_DC4_CCP7 0x00008000 |
| #define | SYSCTL_DC4_CCP6 0x00004000 |
| #define | SYSCTL_DC4_UDMA 0x00002000 |
| #define | SYSCTL_DC4_ROM 0x00001000 |
| #define | SYSCTL_DC4_GPIOJ 0x00000100 |
| #define | SYSCTL_DC4_GPIOH 0x00000080 |
| #define | SYSCTL_DC4_GPIOG 0x00000040 |
| #define | SYSCTL_DC4_GPIOF 0x00000020 |
| #define | SYSCTL_DC4_GPIOE 0x00000010 |
| #define | SYSCTL_DC4_GPIOD 0x00000008 |
| #define | SYSCTL_DC4_GPIOC 0x00000004 |
| #define | SYSCTL_DC4_GPIOB 0x00000002 |
| #define | SYSCTL_DC4_GPIOA 0x00000001 |
| #define | SYSCTL_DC5_PWMFAULT3 0x08000000 |
| #define | SYSCTL_DC5_PWMFAULT2 0x04000000 |
| #define | SYSCTL_DC5_PWMFAULT1 0x02000000 |
| #define | SYSCTL_DC5_PWMFAULT0 0x01000000 |
| #define | SYSCTL_DC5_PWMEFLT 0x00200000 |
| #define | SYSCTL_DC5_PWMESYNC 0x00100000 |
| #define | SYSCTL_DC5_PWM7 0x00000080 |
| #define | SYSCTL_DC5_PWM6 0x00000040 |
| #define | SYSCTL_DC5_PWM5 0x00000020 |
| #define | SYSCTL_DC5_PWM4 0x00000010 |
| #define | SYSCTL_DC5_PWM3 0x00000008 |
| #define | SYSCTL_DC5_PWM2 0x00000004 |
| #define | SYSCTL_DC5_PWM1 0x00000002 |
| #define | SYSCTL_DC5_PWM0 0x00000001 |
| #define | SYSCTL_DC6_USB0PHY 0x00000010 |
| #define | SYSCTL_DC6_USB0_M 0x00000003 |
| #define | SYSCTL_DC6_USB0_DEV 0x00000001 |
| #define | SYSCTL_DC6_USB0_HOSTDEV 0x00000002 |
| #define | SYSCTL_DC6_USB0_OTG 0x00000003 |
| #define | SYSCTL_DC7_DMACH30 0x40000000 |
| #define | SYSCTL_DC7_DMACH29 0x20000000 |
| #define | SYSCTL_DC7_DMACH28 0x10000000 |
| #define | SYSCTL_DC7_DMACH27 0x08000000 |
| #define | SYSCTL_DC7_DMACH26 0x04000000 |
| #define | SYSCTL_DC7_DMACH25 0x02000000 |
| #define | SYSCTL_DC7_DMACH24 0x01000000 |
| #define | SYSCTL_DC7_DMACH23 0x00800000 |
| #define | SYSCTL_DC7_DMACH22 0x00400000 |
| #define | SYSCTL_DC7_DMACH21 0x00200000 |
| #define | SYSCTL_DC7_DMACH20 0x00100000 |
| #define | SYSCTL_DC7_DMACH19 0x00080000 |
| #define | SYSCTL_DC7_DMACH18 0x00040000 |
| #define | SYSCTL_DC7_DMACH17 0x00020000 |
| #define | SYSCTL_DC7_DMACH16 0x00010000 |
| #define | SYSCTL_DC7_DMACH15 0x00008000 |
| #define | SYSCTL_DC7_DMACH14 0x00004000 |
| #define | SYSCTL_DC7_DMACH13 0x00002000 |
| #define | SYSCTL_DC7_DMACH12 0x00001000 |
| #define | SYSCTL_DC7_DMACH11 0x00000800 |
| #define | SYSCTL_DC7_DMACH10 0x00000400 |
| #define | SYSCTL_DC7_DMACH9 0x00000200 |
| #define | SYSCTL_DC7_DMACH8 0x00000100 |
| #define | SYSCTL_DC7_DMACH7 0x00000080 |
| #define | SYSCTL_DC7_DMACH6 0x00000040 |
| #define | SYSCTL_DC7_DMACH5 0x00000020 |
| #define | SYSCTL_DC7_DMACH4 0x00000010 |
| #define | SYSCTL_DC7_DMACH3 0x00000008 |
| #define | SYSCTL_DC7_DMACH2 0x00000004 |
| #define | SYSCTL_DC7_DMACH1 0x00000002 |
| #define | SYSCTL_DC7_DMACH0 0x00000001 |
| #define | SYSCTL_DC8_ADC1AIN15 0x80000000 |
| #define | SYSCTL_DC8_ADC1AIN14 0x40000000 |
| #define | SYSCTL_DC8_ADC1AIN13 0x20000000 |
| #define | SYSCTL_DC8_ADC1AIN12 0x10000000 |
| #define | SYSCTL_DC8_ADC1AIN11 0x08000000 |
| #define | SYSCTL_DC8_ADC1AIN10 0x04000000 |
| #define | SYSCTL_DC8_ADC1AIN9 0x02000000 |
| #define | SYSCTL_DC8_ADC1AIN8 0x01000000 |
| #define | SYSCTL_DC8_ADC1AIN7 0x00800000 |
| #define | SYSCTL_DC8_ADC1AIN6 0x00400000 |
| #define | SYSCTL_DC8_ADC1AIN5 0x00200000 |
| #define | SYSCTL_DC8_ADC1AIN4 0x00100000 |
| #define | SYSCTL_DC8_ADC1AIN3 0x00080000 |
| #define | SYSCTL_DC8_ADC1AIN2 0x00040000 |
| #define | SYSCTL_DC8_ADC1AIN1 0x00020000 |
| #define | SYSCTL_DC8_ADC1AIN0 0x00010000 |
| #define | SYSCTL_DC8_ADC0AIN15 0x00008000 |
| #define | SYSCTL_DC8_ADC0AIN14 0x00004000 |
| #define | SYSCTL_DC8_ADC0AIN13 0x00002000 |
| #define | SYSCTL_DC8_ADC0AIN12 0x00001000 |
| #define | SYSCTL_DC8_ADC0AIN11 0x00000800 |
| #define | SYSCTL_DC8_ADC0AIN10 0x00000400 |
| #define | SYSCTL_DC8_ADC0AIN9 0x00000200 |
| #define | SYSCTL_DC8_ADC0AIN8 0x00000100 |
| #define | SYSCTL_DC8_ADC0AIN7 0x00000080 |
| #define | SYSCTL_DC8_ADC0AIN6 0x00000040 |
| #define | SYSCTL_DC8_ADC0AIN5 0x00000020 |
| #define | SYSCTL_DC8_ADC0AIN4 0x00000010 |
| #define | SYSCTL_DC8_ADC0AIN3 0x00000008 |
| #define | SYSCTL_DC8_ADC0AIN2 0x00000004 |
| #define | SYSCTL_DC8_ADC0AIN1 0x00000002 |
| #define | SYSCTL_DC8_ADC0AIN0 0x00000001 |
| #define | SYSCTL_PBORCTL_BORIOR 0x00000002 |
| #define | SYSCTL_SRCR0_WDT1 0x10000000 |
| #define | SYSCTL_SRCR0_CAN1 0x02000000 |
| #define | SYSCTL_SRCR0_CAN0 0x01000000 |
| #define | SYSCTL_SRCR0_PWM0 0x00100000 |
| #define | SYSCTL_SRCR0_ADC1 0x00020000 |
| #define | SYSCTL_SRCR0_ADC0 0x00010000 |
| #define | SYSCTL_SRCR0_HIB 0x00000040 |
| #define | SYSCTL_SRCR0_WDT0 0x00000008 |
| #define | SYSCTL_SRCR1_COMP2 0x04000000 |
| #define | SYSCTL_SRCR1_COMP1 0x02000000 |
| #define | SYSCTL_SRCR1_COMP0 0x01000000 |
| #define | SYSCTL_SRCR1_TIMER3 0x00080000 |
| #define | SYSCTL_SRCR1_TIMER2 0x00040000 |
| #define | SYSCTL_SRCR1_TIMER1 0x00020000 |
| #define | SYSCTL_SRCR1_TIMER0 0x00010000 |
| #define | SYSCTL_SRCR1_I2C1 0x00004000 |
| #define | SYSCTL_SRCR1_I2C0 0x00001000 |
| #define | SYSCTL_SRCR1_QEI1 0x00000200 |
| #define | SYSCTL_SRCR1_QEI0 0x00000100 |
| #define | SYSCTL_SRCR1_SSI1 0x00000020 |
| #define | SYSCTL_SRCR1_SSI0 0x00000010 |
| #define | SYSCTL_SRCR1_UART2 0x00000004 |
| #define | SYSCTL_SRCR1_UART1 0x00000002 |
| #define | SYSCTL_SRCR1_UART0 0x00000001 |
| #define | SYSCTL_SRCR2_USB0 0x00010000 |
| #define | SYSCTL_SRCR2_UDMA 0x00002000 |
| #define | SYSCTL_SRCR2_GPIOJ 0x00000100 |
| #define | SYSCTL_SRCR2_GPIOH 0x00000080 |
| #define | SYSCTL_SRCR2_GPIOG 0x00000040 |
| #define | SYSCTL_SRCR2_GPIOF 0x00000020 |
| #define | SYSCTL_SRCR2_GPIOE 0x00000010 |
| #define | SYSCTL_SRCR2_GPIOD 0x00000008 |
| #define | SYSCTL_SRCR2_GPIOC 0x00000004 |
| #define | SYSCTL_SRCR2_GPIOB 0x00000002 |
| #define | SYSCTL_SRCR2_GPIOA 0x00000001 |
| #define | SYSCTL_RIS_MOSCPUPRIS 0x00000100 |
| #define | SYSCTL_RIS_USBPLLLRIS 0x00000080 |
| #define | SYSCTL_RIS_PLLLRIS 0x00000040 |
| #define | SYSCTL_RIS_MOFRIS 0x00000008 |
| #define | SYSCTL_RIS_BORRIS 0x00000002 |
| #define | SYSCTL_IMC_MOSCPUPIM 0x00000100 |
| #define | SYSCTL_IMC_USBPLLLIM 0x00000080 |
| #define | SYSCTL_IMC_PLLLIM 0x00000040 |
| #define | SYSCTL_IMC_MOFIM 0x00000008 |
| #define | SYSCTL_IMC_BORIM 0x00000002 |
| #define | SYSCTL_MISC_MOSCPUPMIS 0x00000100 |
| #define | SYSCTL_MISC_USBPLLLMIS 0x00000080 |
| #define | SYSCTL_MISC_PLLLMIS 0x00000040 |
| #define | SYSCTL_MISC_MOFMIS 0x00000008 |
| #define | SYSCTL_MISC_BORMIS 0x00000002 |
| #define | SYSCTL_RESC_MOSCFAIL 0x00010000 |
| #define | SYSCTL_RESC_WDT1 0x00000020 |
| #define | SYSCTL_RESC_SW 0x00000010 |
| #define | SYSCTL_RESC_WDT0 0x00000008 |
| #define | SYSCTL_RESC_BOR 0x00000004 |
| #define | SYSCTL_RESC_POR 0x00000002 |
| #define | SYSCTL_RESC_EXT 0x00000001 |
| #define | SYSCTL_RCC_ACG 0x08000000 |
| #define | SYSCTL_RCC_SYSDIV_M 0x07800000 |
| #define | SYSCTL_RCC_USESYSDIV 0x00400000 |
| #define | SYSCTL_RCC_PWRDN 0x00002000 |
| #define | SYSCTL_RCC_BYPASS 0x00000800 |
| #define | SYSCTL_RCC_XTAL_M 0x000007C0 |
| #define | SYSCTL_RCC_XTAL_4MHZ 0x00000180 |
| #define | SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 |
| #define | SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 |
| #define | SYSCTL_RCC_XTAL_5MHZ 0x00000240 |
| #define | SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 |
| #define | SYSCTL_RCC_XTAL_6MHZ 0x000002C0 |
| #define | SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 |
| #define | SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 |
| #define | SYSCTL_RCC_XTAL_8MHZ 0x00000380 |
| #define | SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 |
| #define | SYSCTL_RCC_XTAL_10MHZ 0x00000400 |
| #define | SYSCTL_RCC_XTAL_12MHZ 0x00000440 |
| #define | SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 |
| #define | SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 |
| #define | SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 |
| #define | SYSCTL_RCC_XTAL_16MHZ 0x00000540 |
| #define | SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 |
| #define | SYSCTL_RCC_XTAL_18MHZ 0x000005C0 |
| #define | SYSCTL_RCC_XTAL_20MHZ 0x00000600 |
| #define | SYSCTL_RCC_XTAL_24MHZ 0x00000640 |
| #define | SYSCTL_RCC_XTAL_25MHZ 0x00000680 |
| #define | SYSCTL_RCC_OSCSRC_M 0x00000030 |
| #define | SYSCTL_RCC_OSCSRC_MAIN 0x00000000 |
| #define | SYSCTL_RCC_OSCSRC_INT 0x00000010 |
| #define | SYSCTL_RCC_OSCSRC_INT4 0x00000020 |
| #define | SYSCTL_RCC_OSCSRC_30 0x00000030 |
| #define | SYSCTL_RCC_IOSCDIS 0x00000002 |
| #define | SYSCTL_RCC_MOSCDIS 0x00000001 |
| #define | SYSCTL_RCC_SYSDIV_S 23 |
| #define | SYSCTL_GPIOHBCTL_PORTF 0x00000020 |
| #define | SYSCTL_GPIOHBCTL_PORTE 0x00000010 |
| #define | SYSCTL_GPIOHBCTL_PORTD 0x00000008 |
| #define | SYSCTL_GPIOHBCTL_PORTC 0x00000004 |
| #define | SYSCTL_GPIOHBCTL_PORTB 0x00000002 |
| #define | SYSCTL_GPIOHBCTL_PORTA 0x00000001 |
| #define | SYSCTL_RCC2_USERCC2 0x80000000 |
| #define | SYSCTL_RCC2_DIV400 0x40000000 |
| #define | SYSCTL_RCC2_SYSDIV2_M 0x1F800000 |
| #define | SYSCTL_RCC2_SYSDIV2_2 0x00800000 |
| #define | SYSCTL_RCC2_SYSDIV2_3 0x01000000 |
| #define | SYSCTL_RCC2_SYSDIV2_4 0x01800000 |
| #define | SYSCTL_RCC2_SYSDIV2_5 0x02000000 |
| #define | SYSCTL_RCC2_SYSDIV2_6 0x02800000 |
| #define | SYSCTL_RCC2_SYSDIV2_7 0x03000000 |
| #define | SYSCTL_RCC2_SYSDIV2_8 0x03800000 |
| #define | SYSCTL_RCC2_SYSDIV2_9 0x04000000 |
| #define | SYSCTL_RCC2_SYSDIV2_10 0x04800000 |
| #define | SYSCTL_RCC2_SYSDIV2_11 0x05000000 |
| #define | SYSCTL_RCC2_SYSDIV2_12 0x05800000 |
| #define | SYSCTL_RCC2_SYSDIV2_13 0x06000000 |
| #define | SYSCTL_RCC2_SYSDIV2_14 0x06800000 |
| #define | SYSCTL_RCC2_SYSDIV2_15 0x07000000 |
| #define | SYSCTL_RCC2_SYSDIV2_16 0x07800000 |
| #define | SYSCTL_RCC2_SYSDIV2_17 0x08000000 |
| #define | SYSCTL_RCC2_SYSDIV2_18 0x08800000 |
| #define | SYSCTL_RCC2_SYSDIV2_19 0x09000000 |
| #define | SYSCTL_RCC2_SYSDIV2_20 0x09800000 |
| #define | SYSCTL_RCC2_SYSDIV2_21 0x0A000000 |
| #define | SYSCTL_RCC2_SYSDIV2_22 0x0A800000 |
| #define | SYSCTL_RCC2_SYSDIV2_23 0x0B000000 |
| #define | SYSCTL_RCC2_SYSDIV2_24 0x0B800000 |
| #define | SYSCTL_RCC2_SYSDIV2_25 0x0C000000 |
| #define | SYSCTL_RCC2_SYSDIV2_26 0x0C800000 |
| #define | SYSCTL_RCC2_SYSDIV2_27 0x0D000000 |
| #define | SYSCTL_RCC2_SYSDIV2_28 0x0D800000 |
| #define | SYSCTL_RCC2_SYSDIV2_29 0x0E000000 |
| #define | SYSCTL_RCC2_SYSDIV2_30 0x0E800000 |
| #define | SYSCTL_RCC2_SYSDIV2_31 0x0F000000 |
| #define | SYSCTL_RCC2_SYSDIV2_32 0x0F800000 |
| #define | SYSCTL_RCC2_SYSDIV2_33 0x10000000 |
| #define | SYSCTL_RCC2_SYSDIV2_34 0x10800000 |
| #define | SYSCTL_RCC2_SYSDIV2_35 0x11000000 |
| #define | SYSCTL_RCC2_SYSDIV2_36 0x11800000 |
| #define | SYSCTL_RCC2_SYSDIV2_37 0x12000000 |
| #define | SYSCTL_RCC2_SYSDIV2_38 0x12800000 |
| #define | SYSCTL_RCC2_SYSDIV2_39 0x13000000 |
| #define | SYSCTL_RCC2_SYSDIV2_40 0x13800000 |
| #define | SYSCTL_RCC2_SYSDIV2_41 0x14000000 |
| #define | SYSCTL_RCC2_SYSDIV2_42 0x14800000 |
| #define | SYSCTL_RCC2_SYSDIV2_43 0x15000000 |
| #define | SYSCTL_RCC2_SYSDIV2_44 0x15800000 |
| #define | SYSCTL_RCC2_SYSDIV2_45 0x16000000 |
| #define | SYSCTL_RCC2_SYSDIV2_46 0x16800000 |
| #define | SYSCTL_RCC2_SYSDIV2_47 0x17000000 |
| #define | SYSCTL_RCC2_SYSDIV2_48 0x17800000 |
| #define | SYSCTL_RCC2_SYSDIV2_49 0x18000000 |
| #define | SYSCTL_RCC2_SYSDIV2_50 0x18800000 |
| #define | SYSCTL_RCC2_SYSDIV2_51 0x19000000 |
| #define | SYSCTL_RCC2_SYSDIV2_52 0x19800000 |
| #define | SYSCTL_RCC2_SYSDIV2_53 0x1A000000 |
| #define | SYSCTL_RCC2_SYSDIV2_54 0x1A800000 |
| #define | SYSCTL_RCC2_SYSDIV2_55 0x1B000000 |
| #define | SYSCTL_RCC2_SYSDIV2_56 0x1B800000 |
| #define | SYSCTL_RCC2_SYSDIV2_57 0x1C000000 |
| #define | SYSCTL_RCC2_SYSDIV2_58 0x1C800000 |
| #define | SYSCTL_RCC2_SYSDIV2_59 0x1D000000 |
| #define | SYSCTL_RCC2_SYSDIV2_60 0x1D800000 |
| #define | SYSCTL_RCC2_SYSDIV2_61 0x1E000000 |
| #define | SYSCTL_RCC2_SYSDIV2_62 0x1E800000 |
| #define | SYSCTL_RCC2_SYSDIV2_63 0x1F000000 |
| #define | SYSCTL_RCC2_SYSDIV2_64 0x1F800000 |
| #define | SYSCTL_RCC2_SYSDIV2LSB 0x00400000 |
| #define | SYSCTL_RCC2_USBPWRDN 0x00004000 |
| #define | SYSCTL_RCC2_PWRDN2 0x00002000 |
| #define | SYSCTL_RCC2_BYPASS2 0x00000800 |
| #define | SYSCTL_RCC2_OSCSRC2_M 0x00000070 |
| #define | SYSCTL_RCC2_OSCSRC2_MO 0x00000000 |
| #define | SYSCTL_RCC2_OSCSRC2_IO 0x00000010 |
| #define | SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 |
| #define | SYSCTL_RCC2_OSCSRC2_30 0x00000030 |
| #define | SYSCTL_RCC2_OSCSRC2_32 0x00000070 |
| #define | SYSCTL_RCC2_SYSDIV2_S 23 |
| #define | SYSCTL_MOSCCTL_NOXTAL 0x00000004 |
| #define | SYSCTL_MOSCCTL_MOSCIM 0x00000002 |
| #define | SYSCTL_MOSCCTL_CVAL 0x00000001 |
| #define | SYSCTL_RCGC0_WDT1 0x10000000 |
| #define | SYSCTL_RCGC0_CAN1 0x02000000 |
| #define | SYSCTL_RCGC0_CAN0 0x01000000 |
| #define | SYSCTL_RCGC0_PWM0 0x00100000 |
| #define | SYSCTL_RCGC0_ADC1 0x00020000 |
| #define | SYSCTL_RCGC0_ADC0 0x00010000 |
| #define | SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 |
| #define | SYSCTL_RCGC0_ADC1SPD_125K 0x00000000 |
| #define | SYSCTL_RCGC0_ADC1SPD_250K 0x00000400 |
| #define | SYSCTL_RCGC0_ADC1SPD_500K 0x00000800 |
| #define | SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 |
| #define | SYSCTL_RCGC0_ADC0SPD_M 0x00000300 |
| #define | SYSCTL_RCGC0_ADC0SPD_125K 0x00000000 |
| #define | SYSCTL_RCGC0_ADC0SPD_250K 0x00000100 |
| #define | SYSCTL_RCGC0_ADC0SPD_500K 0x00000200 |
| #define | SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 |
| #define | SYSCTL_RCGC0_HIB 0x00000040 |
| #define | SYSCTL_RCGC0_WDT0 0x00000008 |
| #define | SYSCTL_RCGC1_COMP2 0x04000000 |
| #define | SYSCTL_RCGC1_COMP1 0x02000000 |
| #define | SYSCTL_RCGC1_COMP0 0x01000000 |
| #define | SYSCTL_RCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_RCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_RCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_RCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_RCGC1_I2C1 0x00004000 |
| #define | SYSCTL_RCGC1_I2C0 0x00001000 |
| #define | SYSCTL_RCGC1_QEI1 0x00000200 |
| #define | SYSCTL_RCGC1_QEI0 0x00000100 |
| #define | SYSCTL_RCGC1_SSI1 0x00000020 |
| #define | SYSCTL_RCGC1_SSI0 0x00000010 |
| #define | SYSCTL_RCGC1_UART2 0x00000004 |
| #define | SYSCTL_RCGC1_UART1 0x00000002 |
| #define | SYSCTL_RCGC1_UART0 0x00000001 |
| #define | SYSCTL_RCGC2_USB0 0x00010000 |
| #define | SYSCTL_RCGC2_UDMA 0x00002000 |
| #define | SYSCTL_RCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_RCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_RCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_RCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_RCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_RCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_RCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_RCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_RCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_SCGC0_WDT1 0x10000000 |
| #define | SYSCTL_SCGC0_CAN1 0x02000000 |
| #define | SYSCTL_SCGC0_CAN0 0x01000000 |
| #define | SYSCTL_SCGC0_PWM0 0x00100000 |
| #define | SYSCTL_SCGC0_ADC1 0x00020000 |
| #define | SYSCTL_SCGC0_ADC0 0x00010000 |
| #define | SYSCTL_SCGC0_HIB 0x00000040 |
| #define | SYSCTL_SCGC0_WDT0 0x00000008 |
| #define | SYSCTL_SCGC1_COMP2 0x04000000 |
| #define | SYSCTL_SCGC1_COMP1 0x02000000 |
| #define | SYSCTL_SCGC1_COMP0 0x01000000 |
| #define | SYSCTL_SCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_SCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_SCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_SCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_SCGC1_I2C1 0x00004000 |
| #define | SYSCTL_SCGC1_I2C0 0x00001000 |
| #define | SYSCTL_SCGC1_QEI1 0x00000200 |
| #define | SYSCTL_SCGC1_QEI0 0x00000100 |
| #define | SYSCTL_SCGC1_SSI1 0x00000020 |
| #define | SYSCTL_SCGC1_SSI0 0x00000010 |
| #define | SYSCTL_SCGC1_UART2 0x00000004 |
| #define | SYSCTL_SCGC1_UART1 0x00000002 |
| #define | SYSCTL_SCGC1_UART0 0x00000001 |
| #define | SYSCTL_SCGC2_USB0 0x00010000 |
| #define | SYSCTL_SCGC2_UDMA 0x00002000 |
| #define | SYSCTL_SCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_SCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_SCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_SCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_SCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_SCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_SCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_SCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_SCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_DCGC0_WDT1 0x10000000 |
| #define | SYSCTL_DCGC0_CAN1 0x02000000 |
| #define | SYSCTL_DCGC0_CAN0 0x01000000 |
| #define | SYSCTL_DCGC0_PWM0 0x00100000 |
| #define | SYSCTL_DCGC0_ADC1 0x00020000 |
| #define | SYSCTL_DCGC0_ADC0 0x00010000 |
| #define | SYSCTL_DCGC0_HIB 0x00000040 |
| #define | SYSCTL_DCGC0_WDT0 0x00000008 |
| #define | SYSCTL_DCGC1_COMP2 0x04000000 |
| #define | SYSCTL_DCGC1_COMP1 0x02000000 |
| #define | SYSCTL_DCGC1_COMP0 0x01000000 |
| #define | SYSCTL_DCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_DCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_DCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_DCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_DCGC1_I2C1 0x00004000 |
| #define | SYSCTL_DCGC1_I2C0 0x00001000 |
| #define | SYSCTL_DCGC1_QEI1 0x00000200 |
| #define | SYSCTL_DCGC1_QEI0 0x00000100 |
| #define | SYSCTL_DCGC1_SSI1 0x00000020 |
| #define | SYSCTL_DCGC1_SSI0 0x00000010 |
| #define | SYSCTL_DCGC1_UART2 0x00000004 |
| #define | SYSCTL_DCGC1_UART1 0x00000002 |
| #define | SYSCTL_DCGC1_UART0 0x00000001 |
| #define | SYSCTL_DCGC2_USB0 0x00010000 |
| #define | SYSCTL_DCGC2_UDMA 0x00002000 |
| #define | SYSCTL_DCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_DCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_DCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_DCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_DCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_DCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_DCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_DCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_DCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_DSLPCLKCFG_D_M 0x1F800000 |
| #define | SYSCTL_DSLPCLKCFG_D_1 0x00000000 |
| #define | SYSCTL_DSLPCLKCFG_D_2 0x00800000 |
| #define | SYSCTL_DSLPCLKCFG_D_3 0x01000000 |
| #define | SYSCTL_DSLPCLKCFG_D_4 0x01800000 |
| #define | SYSCTL_DSLPCLKCFG_D_64 0x1F800000 |
| #define | SYSCTL_DSLPCLKCFG_O_M 0x00000070 |
| #define | SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 |
| #define | SYSCTL_DSLPCLKCFG_O_IO 0x00000010 |
| #define | SYSCTL_DSLPCLKCFG_O_30 0x00000030 |
| #define | SYSCTL_DSLPCLKCFG_O_32 0x00000070 |
| #define | SYSCTL_SYSPROP_FPU 0x00000001 |
| #define | SYSCTL_PIOSCCAL_UTEN 0x80000000 |
| #define | SYSCTL_PIOSCCAL_CAL 0x00000200 |
| #define | SYSCTL_PIOSCCAL_UPDATE 0x00000100 |
| #define | SYSCTL_PIOSCCAL_UT_M 0x0000007F |
| #define | SYSCTL_PIOSCCAL_UT_S 0 |
| #define | SYSCTL_PIOSCSTAT_DT_M 0x007F0000 |
| #define | SYSCTL_PIOSCSTAT_CR_M 0x00000300 |
| #define | SYSCTL_PIOSCSTAT_CRNONE 0x00000000 |
| #define | SYSCTL_PIOSCSTAT_CRPASS 0x00000100 |
| #define | SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 |
| #define | SYSCTL_PIOSCSTAT_CT_M 0x0000007F |
| #define | SYSCTL_PIOSCSTAT_DT_S 16 |
| #define | SYSCTL_PIOSCSTAT_CT_S 0 |
| #define | SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 |
| #define | SYSCTL_PLLFREQ0_MINT_M 0x000003FF |
| #define | SYSCTL_PLLFREQ0_MFRAC_S 10 |
| #define | SYSCTL_PLLFREQ0_MINT_S 0 |
| #define | SYSCTL_PLLFREQ1_Q_M 0x00001F00 |
| #define | SYSCTL_PLLFREQ1_N_M 0x0000001F |
| #define | SYSCTL_PLLFREQ1_Q_S 8 |
| #define | SYSCTL_PLLFREQ1_N_S 0 |
| #define | SYSCTL_PLLSTAT_LOCK 0x00000001 |
| #define | SYSCTL_DC9_ADC1DC7 0x00800000 |
| #define | SYSCTL_DC9_ADC1DC6 0x00400000 |
| #define | SYSCTL_DC9_ADC1DC5 0x00200000 |
| #define | SYSCTL_DC9_ADC1DC4 0x00100000 |
| #define | SYSCTL_DC9_ADC1DC3 0x00080000 |
| #define | SYSCTL_DC9_ADC1DC2 0x00040000 |
| #define | SYSCTL_DC9_ADC1DC1 0x00020000 |
| #define | SYSCTL_DC9_ADC1DC0 0x00010000 |
| #define | SYSCTL_DC9_ADC0DC7 0x00000080 |
| #define | SYSCTL_DC9_ADC0DC6 0x00000040 |
| #define | SYSCTL_DC9_ADC0DC5 0x00000020 |
| #define | SYSCTL_DC9_ADC0DC4 0x00000010 |
| #define | SYSCTL_DC9_ADC0DC3 0x00000008 |
| #define | SYSCTL_DC9_ADC0DC2 0x00000004 |
| #define | SYSCTL_DC9_ADC0DC1 0x00000002 |
| #define | SYSCTL_DC9_ADC0DC0 0x00000001 |
| #define | SYSCTL_NVMSTAT_TPSW 0x00000010 |
| #define | SYSCTL_NVMSTAT_FWB 0x00000001 |
| #define | SYSCTL_PPWD_P1 0x00000002 |
| #define | SYSCTL_PPWD_P0 0x00000001 |
| #define | SYSCTL_PPTIMER_P5 0x00000020 |
| #define | SYSCTL_PPTIMER_P4 0x00000010 |
| #define | SYSCTL_PPTIMER_P3 0x00000008 |
| #define | SYSCTL_PPTIMER_P2 0x00000004 |
| #define | SYSCTL_PPTIMER_P1 0x00000002 |
| #define | SYSCTL_PPTIMER_P0 0x00000001 |
| #define | SYSCTL_PPGPIO_P14 0x00004000 |
| #define | SYSCTL_PPGPIO_P13 0x00002000 |
| #define | SYSCTL_PPGPIO_P12 0x00001000 |
| #define | SYSCTL_PPGPIO_P11 0x00000800 |
| #define | SYSCTL_PPGPIO_P10 0x00000400 |
| #define | SYSCTL_PPGPIO_P9 0x00000200 |
| #define | SYSCTL_PPGPIO_P8 0x00000100 |
| #define | SYSCTL_PPGPIO_P7 0x00000080 |
| #define | SYSCTL_PPGPIO_P6 0x00000040 |
| #define | SYSCTL_PPGPIO_P5 0x00000020 |
| #define | SYSCTL_PPGPIO_P4 0x00000010 |
| #define | SYSCTL_PPGPIO_P3 0x00000008 |
| #define | SYSCTL_PPGPIO_P2 0x00000004 |
| #define | SYSCTL_PPGPIO_P1 0x00000002 |
| #define | SYSCTL_PPGPIO_P0 0x00000001 |
| #define | SYSCTL_PPDMA_P0 0x00000001 |
| #define | SYSCTL_PPHIB_P0 0x00000001 |
| #define | SYSCTL_PPUART_P7 0x00000080 |
| #define | SYSCTL_PPUART_P6 0x00000040 |
| #define | SYSCTL_PPUART_P5 0x00000020 |
| #define | SYSCTL_PPUART_P4 0x00000010 |
| #define | SYSCTL_PPUART_P3 0x00000008 |
| #define | SYSCTL_PPUART_P2 0x00000004 |
| #define | SYSCTL_PPUART_P1 0x00000002 |
| #define | SYSCTL_PPUART_P0 0x00000001 |
| #define | SYSCTL_PPSSI_P3 0x00000008 |
| #define | SYSCTL_PPSSI_P2 0x00000004 |
| #define | SYSCTL_PPSSI_P1 0x00000002 |
| #define | SYSCTL_PPSSI_P0 0x00000001 |
| #define | SYSCTL_PPI2C_P5 0x00000020 |
| #define | SYSCTL_PPI2C_P4 0x00000010 |
| #define | SYSCTL_PPI2C_P3 0x00000008 |
| #define | SYSCTL_PPI2C_P2 0x00000004 |
| #define | SYSCTL_PPI2C_P1 0x00000002 |
| #define | SYSCTL_PPI2C_P0 0x00000001 |
| #define | SYSCTL_PPUSB_P0 0x00000001 |
| #define | SYSCTL_PPCAN_P1 0x00000002 |
| #define | SYSCTL_PPCAN_P0 0x00000001 |
| #define | SYSCTL_PPADC_P1 0x00000002 |
| #define | SYSCTL_PPADC_P0 0x00000001 |
| #define | SYSCTL_PPACMP_P0 0x00000001 |
| #define | SYSCTL_PPPWM_P1 0x00000002 |
| #define | SYSCTL_PPPWM_P0 0x00000001 |
| #define | SYSCTL_PPQEI_P1 0x00000002 |
| #define | SYSCTL_PPQEI_P0 0x00000001 |
| #define | SYSCTL_PPEEPROM_P0 0x00000001 |
| #define | SYSCTL_PPWTIMER_P5 0x00000020 |
| #define | SYSCTL_PPWTIMER_P4 0x00000010 |
| #define | SYSCTL_PPWTIMER_P3 0x00000008 |
| #define | SYSCTL_PPWTIMER_P2 0x00000004 |
| #define | SYSCTL_PPWTIMER_P1 0x00000002 |
| #define | SYSCTL_PPWTIMER_P0 0x00000001 |
| #define | SYSCTL_SRWD_R1 0x00000002 |
| #define | SYSCTL_SRWD_R0 0x00000001 |
| #define | SYSCTL_SRTIMER_R5 0x00000020 |
| #define | SYSCTL_SRTIMER_R4 0x00000010 |
| #define | SYSCTL_SRTIMER_R3 0x00000008 |
| #define | SYSCTL_SRTIMER_R2 0x00000004 |
| #define | SYSCTL_SRTIMER_R1 0x00000002 |
| #define | SYSCTL_SRTIMER_R0 0x00000001 |
| #define | SYSCTL_SRGPIO_R14 0x00004000 |
| #define | SYSCTL_SRGPIO_R13 0x00002000 |
| #define | SYSCTL_SRGPIO_R12 0x00001000 |
| #define | SYSCTL_SRGPIO_R11 0x00000800 |
| #define | SYSCTL_SRGPIO_R10 0x00000400 |
| #define | SYSCTL_SRGPIO_R9 0x00000200 |
| #define | SYSCTL_SRGPIO_R8 0x00000100 |
| #define | SYSCTL_SRGPIO_R7 0x00000080 |
| #define | SYSCTL_SRGPIO_R6 0x00000040 |
| #define | SYSCTL_SRGPIO_R5 0x00000020 |
| #define | SYSCTL_SRGPIO_R4 0x00000010 |
| #define | SYSCTL_SRGPIO_R3 0x00000008 |
| #define | SYSCTL_SRGPIO_R2 0x00000004 |
| #define | SYSCTL_SRGPIO_R1 0x00000002 |
| #define | SYSCTL_SRGPIO_R0 0x00000001 |
| #define | SYSCTL_SRDMA_R0 0x00000001 |
| #define | SYSCTL_SRHIB_R0 0x00000001 |
| #define | SYSCTL_SRUART_R7 0x00000080 |
| #define | SYSCTL_SRUART_R6 0x00000040 |
| #define | SYSCTL_SRUART_R5 0x00000020 |
| #define | SYSCTL_SRUART_R4 0x00000010 |
| #define | SYSCTL_SRUART_R3 0x00000008 |
| #define | SYSCTL_SRUART_R2 0x00000004 |
| #define | SYSCTL_SRUART_R1 0x00000002 |
| #define | SYSCTL_SRUART_R0 0x00000001 |
| #define | SYSCTL_SRSSI_R3 0x00000008 |
| #define | SYSCTL_SRSSI_R2 0x00000004 |
| #define | SYSCTL_SRSSI_R1 0x00000002 |
| #define | SYSCTL_SRSSI_R0 0x00000001 |
| #define | SYSCTL_SRI2C_R5 0x00000020 |
| #define | SYSCTL_SRI2C_R4 0x00000010 |
| #define | SYSCTL_SRI2C_R3 0x00000008 |
| #define | SYSCTL_SRI2C_R2 0x00000004 |
| #define | SYSCTL_SRI2C_R1 0x00000002 |
| #define | SYSCTL_SRI2C_R0 0x00000001 |
| #define | SYSCTL_SRUSB_R0 0x00000001 |
| #define | SYSCTL_SRCAN_R1 0x00000002 |
| #define | SYSCTL_SRCAN_R0 0x00000001 |
| #define | SYSCTL_SRADC_R1 0x00000002 |
| #define | SYSCTL_SRADC_R0 0x00000001 |
| #define | SYSCTL_SRACMP_R0 0x00000001 |
| #define | SYSCTL_SREEPROM_R0 0x00000001 |
| #define | SYSCTL_SRWTIMER_R5 0x00000020 |
| #define | SYSCTL_SRWTIMER_R4 0x00000010 |
| #define | SYSCTL_SRWTIMER_R3 0x00000008 |
| #define | SYSCTL_SRWTIMER_R2 0x00000004 |
| #define | SYSCTL_SRWTIMER_R1 0x00000002 |
| #define | SYSCTL_SRWTIMER_R0 0x00000001 |
| #define | SYSCTL_RCGCWD_R1 0x00000002 |
| #define | SYSCTL_RCGCWD_R0 0x00000001 |
| #define | SYSCTL_RCGCTIMER_R5 0x00000020 |
| #define | SYSCTL_RCGCTIMER_R4 0x00000010 |
| #define | SYSCTL_RCGCTIMER_R3 0x00000008 |
| #define | SYSCTL_RCGCTIMER_R2 0x00000004 |
| #define | SYSCTL_RCGCTIMER_R1 0x00000002 |
| #define | SYSCTL_RCGCTIMER_R0 0x00000001 |
| #define | SYSCTL_RCGCGPIO_R14 0x00004000 |
| #define | SYSCTL_RCGCGPIO_R13 0x00002000 |
| #define | SYSCTL_RCGCGPIO_R12 0x00001000 |
| #define | SYSCTL_RCGCGPIO_R11 0x00000800 |
| #define | SYSCTL_RCGCGPIO_R10 0x00000400 |
| #define | SYSCTL_RCGCGPIO_R9 0x00000200 |
| #define | SYSCTL_RCGCGPIO_R8 0x00000100 |
| #define | SYSCTL_RCGCGPIO_R7 0x00000080 |
| #define | SYSCTL_RCGCGPIO_R6 0x00000040 |
| #define | SYSCTL_RCGCGPIO_R5 0x00000020 |
| #define | SYSCTL_RCGCGPIO_R4 0x00000010 |
| #define | SYSCTL_RCGCGPIO_R3 0x00000008 |
| #define | SYSCTL_RCGCGPIO_R2 0x00000004 |
| #define | SYSCTL_RCGCGPIO_R1 0x00000002 |
| #define | SYSCTL_RCGCGPIO_R0 0x00000001 |
| #define | SYSCTL_RCGCDMA_R0 0x00000001 |
| #define | SYSCTL_RCGCHIB_R0 0x00000001 |
| #define | SYSCTL_RCGCUART_R7 0x00000080 |
| #define | SYSCTL_RCGCUART_R6 0x00000040 |
| #define | SYSCTL_RCGCUART_R5 0x00000020 |
| #define | SYSCTL_RCGCUART_R4 0x00000010 |
| #define | SYSCTL_RCGCUART_R3 0x00000008 |
| #define | SYSCTL_RCGCUART_R2 0x00000004 |
| #define | SYSCTL_RCGCUART_R1 0x00000002 |
| #define | SYSCTL_RCGCUART_R0 0x00000001 |
| #define | SYSCTL_RCGCSSI_R3 0x00000008 |
| #define | SYSCTL_RCGCSSI_R2 0x00000004 |
| #define | SYSCTL_RCGCSSI_R1 0x00000002 |
| #define | SYSCTL_RCGCSSI_R0 0x00000001 |
| #define | SYSCTL_RCGCI2C_R5 0x00000020 |
| #define | SYSCTL_RCGCI2C_R4 0x00000010 |
| #define | SYSCTL_RCGCI2C_R3 0x00000008 |
| #define | SYSCTL_RCGCI2C_R2 0x00000004 |
| #define | SYSCTL_RCGCI2C_R1 0x00000002 |
| #define | SYSCTL_RCGCI2C_R0 0x00000001 |
| #define | SYSCTL_RCGCUSB_R0 0x00000001 |
| #define | SYSCTL_RCGCCAN_R1 0x00000002 |
| #define | SYSCTL_RCGCCAN_R0 0x00000001 |
| #define | SYSCTL_RCGCADC_R1 0x00000002 |
| #define | SYSCTL_RCGCADC_R0 0x00000001 |
| #define | SYSCTL_RCGCACMP_R0 0x00000001 |
| #define | SYSCTL_RCGCEEPROM_R0 0x00000001 |
| #define | SYSCTL_RCGCWTIMER_R5 0x00000020 |
| #define | SYSCTL_RCGCWTIMER_R4 0x00000010 |
| #define | SYSCTL_RCGCWTIMER_R3 0x00000008 |
| #define | SYSCTL_RCGCWTIMER_R2 0x00000004 |
| #define | SYSCTL_RCGCWTIMER_R1 0x00000002 |
| #define | SYSCTL_RCGCWTIMER_R0 0x00000001 |
| #define | SYSCTL_SCGCWD_S1 0x00000002 |
| #define | SYSCTL_SCGCWD_S0 0x00000001 |
| #define | SYSCTL_SCGCTIMER_S5 0x00000020 |
| #define | SYSCTL_SCGCTIMER_S4 0x00000010 |
| #define | SYSCTL_SCGCTIMER_S3 0x00000008 |
| #define | SYSCTL_SCGCTIMER_S2 0x00000004 |
| #define | SYSCTL_SCGCTIMER_S1 0x00000002 |
| #define | SYSCTL_SCGCTIMER_S0 0x00000001 |
| #define | SYSCTL_SCGCGPIO_S14 0x00004000 |
| #define | SYSCTL_SCGCGPIO_S13 0x00002000 |
| #define | SYSCTL_SCGCGPIO_S12 0x00001000 |
| #define | SYSCTL_SCGCGPIO_S11 0x00000800 |
| #define | SYSCTL_SCGCGPIO_S10 0x00000400 |
| #define | SYSCTL_SCGCGPIO_S9 0x00000200 |
| #define | SYSCTL_SCGCGPIO_S8 0x00000100 |
| #define | SYSCTL_SCGCGPIO_S7 0x00000080 |
| #define | SYSCTL_SCGCGPIO_S6 0x00000040 |
| #define | SYSCTL_SCGCGPIO_S5 0x00000020 |
| #define | SYSCTL_SCGCGPIO_S4 0x00000010 |
| #define | SYSCTL_SCGCGPIO_S3 0x00000008 |
| #define | SYSCTL_SCGCGPIO_S2 0x00000004 |
| #define | SYSCTL_SCGCGPIO_S1 0x00000002 |
| #define | SYSCTL_SCGCGPIO_S0 0x00000001 |
| #define | SYSCTL_SCGCDMA_S0 0x00000001 |
| #define | SYSCTL_SCGCHIB_S0 0x00000001 |
| #define | SYSCTL_SCGCUART_S7 0x00000080 |
| #define | SYSCTL_SCGCUART_S6 0x00000040 |
| #define | SYSCTL_SCGCUART_S5 0x00000020 |
| #define | SYSCTL_SCGCUART_S4 0x00000010 |
| #define | SYSCTL_SCGCUART_S3 0x00000008 |
| #define | SYSCTL_SCGCUART_S2 0x00000004 |
| #define | SYSCTL_SCGCUART_S1 0x00000002 |
| #define | SYSCTL_SCGCUART_S0 0x00000001 |
| #define | SYSCTL_SCGCSSI_S3 0x00000008 |
| #define | SYSCTL_SCGCSSI_S2 0x00000004 |
| #define | SYSCTL_SCGCSSI_S1 0x00000002 |
| #define | SYSCTL_SCGCSSI_S0 0x00000001 |
| #define | SYSCTL_SCGCI2C_S5 0x00000020 |
| #define | SYSCTL_SCGCI2C_S4 0x00000010 |
| #define | SYSCTL_SCGCI2C_S3 0x00000008 |
| #define | SYSCTL_SCGCI2C_S2 0x00000004 |
| #define | SYSCTL_SCGCI2C_S1 0x00000002 |
| #define | SYSCTL_SCGCI2C_S0 0x00000001 |
| #define | SYSCTL_SCGCUSB_S0 0x00000001 |
| #define | SYSCTL_SCGCCAN_S1 0x00000002 |
| #define | SYSCTL_SCGCCAN_S0 0x00000001 |
| #define | SYSCTL_SCGCADC_S1 0x00000002 |
| #define | SYSCTL_SCGCADC_S0 0x00000001 |
| #define | SYSCTL_SCGCACMP_S0 0x00000001 |
| #define | SYSCTL_SCGCEEPROM_S0 0x00000001 |
| #define | SYSCTL_SCGCWTIMER_S5 0x00000020 |
| #define | SYSCTL_SCGCWTIMER_S4 0x00000010 |
| #define | SYSCTL_SCGCWTIMER_S3 0x00000008 |
| #define | SYSCTL_SCGCWTIMER_S2 0x00000004 |
| #define | SYSCTL_SCGCWTIMER_S1 0x00000002 |
| #define | SYSCTL_SCGCWTIMER_S0 0x00000001 |
| #define | SYSCTL_DCGCWD_D1 0x00000002 |
| #define | SYSCTL_DCGCWD_D0 0x00000001 |
| #define | SYSCTL_DCGCTIMER_D5 0x00000020 |
| #define | SYSCTL_DCGCTIMER_D4 0x00000010 |
| #define | SYSCTL_DCGCTIMER_D3 0x00000008 |
| #define | SYSCTL_DCGCTIMER_D2 0x00000004 |
| #define | SYSCTL_DCGCTIMER_D1 0x00000002 |
| #define | SYSCTL_DCGCTIMER_D0 0x00000001 |
| #define | SYSCTL_DCGCGPIO_D14 0x00004000 |
| #define | SYSCTL_DCGCGPIO_D13 0x00002000 |
| #define | SYSCTL_DCGCGPIO_D12 0x00001000 |
| #define | SYSCTL_DCGCGPIO_D11 0x00000800 |
| #define | SYSCTL_DCGCGPIO_D10 0x00000400 |
| #define | SYSCTL_DCGCGPIO_D9 0x00000200 |
| #define | SYSCTL_DCGCGPIO_D8 0x00000100 |
| #define | SYSCTL_DCGCGPIO_D7 0x00000080 |
| #define | SYSCTL_DCGCGPIO_D6 0x00000040 |
| #define | SYSCTL_DCGCGPIO_D5 0x00000020 |
| #define | SYSCTL_DCGCGPIO_D4 0x00000010 |
| #define | SYSCTL_DCGCGPIO_D3 0x00000008 |
| #define | SYSCTL_DCGCGPIO_D2 0x00000004 |
| #define | SYSCTL_DCGCGPIO_D1 0x00000002 |
| #define | SYSCTL_DCGCGPIO_D0 0x00000001 |
| #define | SYSCTL_DCGCDMA_D0 0x00000001 |
| #define | SYSCTL_DCGCHIB_D0 0x00000001 |
| #define | SYSCTL_DCGCUART_D7 0x00000080 |
| #define | SYSCTL_DCGCUART_D6 0x00000040 |
| #define | SYSCTL_DCGCUART_D5 0x00000020 |
| #define | SYSCTL_DCGCUART_D4 0x00000010 |
| #define | SYSCTL_DCGCUART_D3 0x00000008 |
| #define | SYSCTL_DCGCUART_D2 0x00000004 |
| #define | SYSCTL_DCGCUART_D1 0x00000002 |
| #define | SYSCTL_DCGCUART_D0 0x00000001 |
| #define | SYSCTL_DCGCSSI_D3 0x00000008 |
| #define | SYSCTL_DCGCSSI_D2 0x00000004 |
| #define | SYSCTL_DCGCSSI_D1 0x00000002 |
| #define | SYSCTL_DCGCSSI_D0 0x00000001 |
| #define | SYSCTL_DCGCI2C_D5 0x00000020 |
| #define | SYSCTL_DCGCI2C_D4 0x00000010 |
| #define | SYSCTL_DCGCI2C_D3 0x00000008 |
| #define | SYSCTL_DCGCI2C_D2 0x00000004 |
| #define | SYSCTL_DCGCI2C_D1 0x00000002 |
| #define | SYSCTL_DCGCI2C_D0 0x00000001 |
| #define | SYSCTL_DCGCUSB_D0 0x00000001 |
| #define | SYSCTL_DCGCCAN_D1 0x00000002 |
| #define | SYSCTL_DCGCCAN_D0 0x00000001 |
| #define | SYSCTL_DCGCADC_D1 0x00000002 |
| #define | SYSCTL_DCGCADC_D0 0x00000001 |
| #define | SYSCTL_DCGCACMP_D0 0x00000001 |
| #define | SYSCTL_DCGCEEPROM_D0 0x00000001 |
| #define | SYSCTL_DCGCWTIMER_D5 0x00000020 |
| #define | SYSCTL_DCGCWTIMER_D4 0x00000010 |
| #define | SYSCTL_DCGCWTIMER_D3 0x00000008 |
| #define | SYSCTL_DCGCWTIMER_D2 0x00000004 |
| #define | SYSCTL_DCGCWTIMER_D1 0x00000002 |
| #define | SYSCTL_DCGCWTIMER_D0 0x00000001 |
| #define | SYSCTL_PCWD_P1 0x00000002 |
| #define | SYSCTL_PCWD_P0 0x00000001 |
| #define | SYSCTL_PCTIMER_P5 0x00000020 |
| #define | SYSCTL_PCTIMER_P4 0x00000010 |
| #define | SYSCTL_PCTIMER_P3 0x00000008 |
| #define | SYSCTL_PCTIMER_P2 0x00000004 |
| #define | SYSCTL_PCTIMER_P1 0x00000002 |
| #define | SYSCTL_PCTIMER_P0 0x00000001 |
| #define | SYSCTL_PCGPIO_P14 0x00004000 |
| #define | SYSCTL_PCGPIO_P13 0x00002000 |
| #define | SYSCTL_PCGPIO_P12 0x00001000 |
| #define | SYSCTL_PCGPIO_P11 0x00000800 |
| #define | SYSCTL_PCGPIO_P10 0x00000400 |
| #define | SYSCTL_PCGPIO_P9 0x00000200 |
| #define | SYSCTL_PCGPIO_P8 0x00000100 |
| #define | SYSCTL_PCGPIO_P7 0x00000080 |
| #define | SYSCTL_PCGPIO_P6 0x00000040 |
| #define | SYSCTL_PCGPIO_P5 0x00000020 |
| #define | SYSCTL_PCGPIO_P4 0x00000010 |
| #define | SYSCTL_PCGPIO_P3 0x00000008 |
| #define | SYSCTL_PCGPIO_P2 0x00000004 |
| #define | SYSCTL_PCGPIO_P1 0x00000002 |
| #define | SYSCTL_PCGPIO_P0 0x00000001 |
| #define | SYSCTL_PCDMA_P0 0x00000001 |
| #define | SYSCTL_PCHIB_P0 0x00000001 |
| #define | SYSCTL_PCUART_P7 0x00000080 |
| #define | SYSCTL_PCUART_P6 0x00000040 |
| #define | SYSCTL_PCUART_P5 0x00000020 |
| #define | SYSCTL_PCUART_P4 0x00000010 |
| #define | SYSCTL_PCUART_P3 0x00000008 |
| #define | SYSCTL_PCUART_P2 0x00000004 |
| #define | SYSCTL_PCUART_P1 0x00000002 |
| #define | SYSCTL_PCUART_P0 0x00000001 |
| #define | SYSCTL_PCSSI_P3 0x00000008 |
| #define | SYSCTL_PCSSI_P2 0x00000004 |
| #define | SYSCTL_PCSSI_P1 0x00000002 |
| #define | SYSCTL_PCSSI_P0 0x00000001 |
| #define | SYSCTL_PCI2C_P5 0x00000020 |
| #define | SYSCTL_PCI2C_P4 0x00000010 |
| #define | SYSCTL_PCI2C_P3 0x00000008 |
| #define | SYSCTL_PCI2C_P2 0x00000004 |
| #define | SYSCTL_PCI2C_P1 0x00000002 |
| #define | SYSCTL_PCI2C_P0 0x00000001 |
| #define | SYSCTL_PCUSB_P0 0x00000001 |
| #define | SYSCTL_PCCAN_P1 0x00000002 |
| #define | SYSCTL_PCCAN_P0 0x00000001 |
| #define | SYSCTL_PCADC_P1 0x00000002 |
| #define | SYSCTL_PCADC_P0 0x00000001 |
| #define | SYSCTL_PCACMP_P0 0x00000001 |
| #define | SYSCTL_PCEEPROM_P0 0x00000001 |
| #define | SYSCTL_PCWTIMER_P5 0x00000020 |
| #define | SYSCTL_PCWTIMER_P4 0x00000010 |
| #define | SYSCTL_PCWTIMER_P3 0x00000008 |
| #define | SYSCTL_PCWTIMER_P2 0x00000004 |
| #define | SYSCTL_PCWTIMER_P1 0x00000002 |
| #define | SYSCTL_PCWTIMER_P0 0x00000001 |
| #define | SYSCTL_PRWD_R1 0x00000002 |
| #define | SYSCTL_PRWD_R0 0x00000001 |
| #define | SYSCTL_PRTIMER_R5 0x00000020 |
| #define | SYSCTL_PRTIMER_R4 0x00000010 |
| #define | SYSCTL_PRTIMER_R3 0x00000008 |
| #define | SYSCTL_PRTIMER_R2 0x00000004 |
| #define | SYSCTL_PRTIMER_R1 0x00000002 |
| #define | SYSCTL_PRTIMER_R0 0x00000001 |
| #define | SYSCTL_PRGPIO_R14 0x00004000 |
| #define | SYSCTL_PRGPIO_R13 0x00002000 |
| #define | SYSCTL_PRGPIO_R12 0x00001000 |
| #define | SYSCTL_PRGPIO_R11 0x00000800 |
| #define | SYSCTL_PRGPIO_R10 0x00000400 |
| #define | SYSCTL_PRGPIO_R9 0x00000200 |
| #define | SYSCTL_PRGPIO_R8 0x00000100 |
| #define | SYSCTL_PRGPIO_R7 0x00000080 |
| #define | SYSCTL_PRGPIO_R6 0x00000040 |
| #define | SYSCTL_PRGPIO_R5 0x00000020 |
| #define | SYSCTL_PRGPIO_R4 0x00000010 |
| #define | SYSCTL_PRGPIO_R3 0x00000008 |
| #define | SYSCTL_PRGPIO_R2 0x00000004 |
| #define | SYSCTL_PRGPIO_R1 0x00000002 |
| #define | SYSCTL_PRGPIO_R0 0x00000001 |
| #define | SYSCTL_PRDMA_R0 0x00000001 |
| #define | SYSCTL_PRHIB_R0 0x00000001 |
| #define | SYSCTL_PRUART_R7 0x00000080 |
| #define | SYSCTL_PRUART_R6 0x00000040 |
| #define | SYSCTL_PRUART_R5 0x00000020 |
| #define | SYSCTL_PRUART_R4 0x00000010 |
| #define | SYSCTL_PRUART_R3 0x00000008 |
| #define | SYSCTL_PRUART_R2 0x00000004 |
| #define | SYSCTL_PRUART_R1 0x00000002 |
| #define | SYSCTL_PRUART_R0 0x00000001 |
| #define | SYSCTL_PRSSI_R3 0x00000008 |
| #define | SYSCTL_PRSSI_R2 0x00000004 |
| #define | SYSCTL_PRSSI_R1 0x00000002 |
| #define | SYSCTL_PRSSI_R0 0x00000001 |
| #define | SYSCTL_PRI2C_R5 0x00000020 |
| #define | SYSCTL_PRI2C_R4 0x00000010 |
| #define | SYSCTL_PRI2C_R3 0x00000008 |
| #define | SYSCTL_PRI2C_R2 0x00000004 |
| #define | SYSCTL_PRI2C_R1 0x00000002 |
| #define | SYSCTL_PRI2C_R0 0x00000001 |
| #define | SYSCTL_PRUSB_R0 0x00000001 |
| #define | SYSCTL_PRCAN_R1 0x00000002 |
| #define | SYSCTL_PRCAN_R0 0x00000001 |
| #define | SYSCTL_PRADC_R1 0x00000002 |
| #define | SYSCTL_PRADC_R0 0x00000001 |
| #define | SYSCTL_PRACMP_R0 0x00000001 |
| #define | SYSCTL_PREEPROM_R0 0x00000001 |
| #define | SYSCTL_PRWTIMER_R5 0x00000020 |
| #define | SYSCTL_PRWTIMER_R4 0x00000010 |
| #define | SYSCTL_PRWTIMER_R3 0x00000008 |
| #define | SYSCTL_PRWTIMER_R2 0x00000004 |
| #define | SYSCTL_PRWTIMER_R1 0x00000002 |
| #define | SYSCTL_PRWTIMER_R0 0x00000001 |
| #define | UDMA_STAT_DMACHANS_M 0x001F0000 |
| #define | UDMA_STAT_STATE_M 0x000000F0 |
| #define | UDMA_STAT_STATE_IDLE 0x00000000 |
| #define | UDMA_STAT_STATE_RD_CTRL 0x00000010 |
| #define | UDMA_STAT_STATE_RD_SRCENDP 0x00000020 |
| #define | UDMA_STAT_STATE_RD_DSTENDP 0x00000030 |
| #define | UDMA_STAT_STATE_RD_SRCDAT 0x00000040 |
| #define | UDMA_STAT_STATE_WR_DSTDAT 0x00000050 |
| #define | UDMA_STAT_STATE_WAIT 0x00000060 |
| #define | UDMA_STAT_STATE_WR_CTRL 0x00000070 |
| #define | UDMA_STAT_STATE_STALL 0x00000080 |
| #define | UDMA_STAT_STATE_DONE 0x00000090 |
| #define | UDMA_STAT_STATE_UNDEF 0x000000A0 |
| #define | UDMA_STAT_MASTEN 0x00000001 |
| #define | UDMA_STAT_DMACHANS_S 16 |
| #define | UDMA_CFG_MASTEN 0x00000001 |
| #define | UDMA_CTLBASE_ADDR_M 0xFFFFFC00 |
| #define | UDMA_CTLBASE_ADDR_S 10 |
| #define | UDMA_ALTBASE_ADDR_M 0xFFFFFFFF |
| #define | UDMA_ALTBASE_ADDR_S 0 |
| #define | UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF |
| #define | UDMA_SWREQ_M 0xFFFFFFFF |
| #define | UDMA_USEBURSTSET_SET_M 0xFFFFFFFF |
| #define | UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_REQMASKSET_SET_M 0xFFFFFFFF |
| #define | UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ENASET_SET_M 0xFFFFFFFF |
| #define | UDMA_ENACLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ALTSET_SET_M 0xFFFFFFFF |
| #define | UDMA_ALTCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_PRIOSET_SET_M 0xFFFFFFFF |
| #define | UDMA_PRIOCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ERRCLR_ERRCLR 0x00000001 |
| #define | UDMA_CHASGN_M 0xFFFFFFFF |
| #define | UDMA_CHASGN_PRIMARY 0x00000000 |
| #define | UDMA_CHASGN_SECONDARY 0x00000001 |
| #define | UDMA_CHIS_M 0xFFFFFFFF |
| #define | UDMA_CHMAP0_CH7SEL_M 0xF0000000 |
| #define | UDMA_CHMAP0_CH6SEL_M 0x0F000000 |
| #define | UDMA_CHMAP0_CH5SEL_M 0x00F00000 |
| #define | UDMA_CHMAP0_CH4SEL_M 0x000F0000 |
| #define | UDMA_CHMAP0_CH3SEL_M 0x0000F000 |
| #define | UDMA_CHMAP0_CH2SEL_M 0x00000F00 |
| #define | UDMA_CHMAP0_CH1SEL_M 0x000000F0 |
| #define | UDMA_CHMAP0_CH0SEL_M 0x0000000F |
| #define | UDMA_CHMAP0_CH7SEL_S 28 |
| #define | UDMA_CHMAP0_CH6SEL_S 24 |
| #define | UDMA_CHMAP0_CH5SEL_S 20 |
| #define | UDMA_CHMAP0_CH4SEL_S 16 |
| #define | UDMA_CHMAP0_CH3SEL_S 12 |
| #define | UDMA_CHMAP0_CH2SEL_S 8 |
| #define | UDMA_CHMAP0_CH1SEL_S 4 |
| #define | UDMA_CHMAP0_CH0SEL_S 0 |
| #define | UDMA_CHMAP1_CH15SEL_M 0xF0000000 |
| #define | UDMA_CHMAP1_CH14SEL_M 0x0F000000 |
| #define | UDMA_CHMAP1_CH13SEL_M 0x00F00000 |
| #define | UDMA_CHMAP1_CH12SEL_M 0x000F0000 |
| #define | UDMA_CHMAP1_CH11SEL_M 0x0000F000 |
| #define | UDMA_CHMAP1_CH10SEL_M 0x00000F00 |
| #define | UDMA_CHMAP1_CH9SEL_M 0x000000F0 |
| #define | UDMA_CHMAP1_CH8SEL_M 0x0000000F |
| #define | UDMA_CHMAP1_CH15SEL_S 28 |
| #define | UDMA_CHMAP1_CH14SEL_S 24 |
| #define | UDMA_CHMAP1_CH13SEL_S 20 |
| #define | UDMA_CHMAP1_CH12SEL_S 16 |
| #define | UDMA_CHMAP1_CH11SEL_S 12 |
| #define | UDMA_CHMAP1_CH10SEL_S 8 |
| #define | UDMA_CHMAP1_CH9SEL_S 4 |
| #define | UDMA_CHMAP1_CH8SEL_S 0 |
| #define | UDMA_CHMAP2_CH23SEL_M 0xF0000000 |
| #define | UDMA_CHMAP2_CH22SEL_M 0x0F000000 |
| #define | UDMA_CHMAP2_CH21SEL_M 0x00F00000 |
| #define | UDMA_CHMAP2_CH20SEL_M 0x000F0000 |
| #define | UDMA_CHMAP2_CH19SEL_M 0x0000F000 |
| #define | UDMA_CHMAP2_CH18SEL_M 0x00000F00 |
| #define | UDMA_CHMAP2_CH17SEL_M 0x000000F0 |
| #define | UDMA_CHMAP2_CH16SEL_M 0x0000000F |
| #define | UDMA_CHMAP2_CH23SEL_S 28 |
| #define | UDMA_CHMAP2_CH22SEL_S 24 |
| #define | UDMA_CHMAP2_CH21SEL_S 20 |
| #define | UDMA_CHMAP2_CH20SEL_S 16 |
| #define | UDMA_CHMAP2_CH19SEL_S 12 |
| #define | UDMA_CHMAP2_CH18SEL_S 8 |
| #define | UDMA_CHMAP2_CH17SEL_S 4 |
| #define | UDMA_CHMAP2_CH16SEL_S 0 |
| #define | UDMA_CHMAP3_CH31SEL_M 0xF0000000 |
| #define | UDMA_CHMAP3_CH30SEL_M 0x0F000000 |
| #define | UDMA_CHMAP3_CH29SEL_M 0x00F00000 |
| #define | UDMA_CHMAP3_CH28SEL_M 0x000F0000 |
| #define | UDMA_CHMAP3_CH27SEL_M 0x0000F000 |
| #define | UDMA_CHMAP3_CH26SEL_M 0x00000F00 |
| #define | UDMA_CHMAP3_CH25SEL_M 0x000000F0 |
| #define | UDMA_CHMAP3_CH24SEL_M 0x0000000F |
| #define | UDMA_CHMAP3_CH31SEL_S 28 |
| #define | UDMA_CHMAP3_CH30SEL_S 24 |
| #define | UDMA_CHMAP3_CH29SEL_S 20 |
| #define | UDMA_CHMAP3_CH28SEL_S 16 |
| #define | UDMA_CHMAP3_CH27SEL_S 12 |
| #define | UDMA_CHMAP3_CH26SEL_S 8 |
| #define | UDMA_CHMAP3_CH25SEL_S 4 |
| #define | UDMA_CHMAP3_CH24SEL_S 0 |
| #define | UDMA_SRCENDP_ADDR_M 0xFFFFFFFF |
| #define | UDMA_SRCENDP_ADDR_S 0 |
| #define | UDMA_DSTENDP_ADDR_M 0xFFFFFFFF |
| #define | UDMA_DSTENDP_ADDR_S 0 |
| #define | UDMA_CHCTL_DSTINC_M 0xC0000000 |
| #define | UDMA_CHCTL_DSTINC_8 0x00000000 |
| #define | UDMA_CHCTL_DSTINC_16 0x40000000 |
| #define | UDMA_CHCTL_DSTINC_32 0x80000000 |
| #define | UDMA_CHCTL_DSTINC_NONE 0xC0000000 |
| #define | UDMA_CHCTL_DSTSIZE_M 0x30000000 |
| #define | UDMA_CHCTL_DSTSIZE_8 0x00000000 |
| #define | UDMA_CHCTL_DSTSIZE_16 0x10000000 |
| #define | UDMA_CHCTL_DSTSIZE_32 0x20000000 |
| #define | UDMA_CHCTL_SRCINC_M 0x0C000000 |
| #define | UDMA_CHCTL_SRCINC_8 0x00000000 |
| #define | UDMA_CHCTL_SRCINC_16 0x04000000 |
| #define | UDMA_CHCTL_SRCINC_32 0x08000000 |
| #define | UDMA_CHCTL_SRCINC_NONE 0x0C000000 |
| #define | UDMA_CHCTL_SRCSIZE_M 0x03000000 |
| #define | UDMA_CHCTL_SRCSIZE_8 0x00000000 |
| #define | UDMA_CHCTL_SRCSIZE_16 0x01000000 |
| #define | UDMA_CHCTL_SRCSIZE_32 0x02000000 |
| #define | UDMA_CHCTL_ARBSIZE_M 0x0003C000 |
| #define | UDMA_CHCTL_ARBSIZE_1 0x00000000 |
| #define | UDMA_CHCTL_ARBSIZE_2 0x00004000 |
| #define | UDMA_CHCTL_ARBSIZE_4 0x00008000 |
| #define | UDMA_CHCTL_ARBSIZE_8 0x0000C000 |
| #define | UDMA_CHCTL_ARBSIZE_16 0x00010000 |
| #define | UDMA_CHCTL_ARBSIZE_32 0x00014000 |
| #define | UDMA_CHCTL_ARBSIZE_64 0x00018000 |
| #define | UDMA_CHCTL_ARBSIZE_128 0x0001C000 |
| #define | UDMA_CHCTL_ARBSIZE_256 0x00020000 |
| #define | UDMA_CHCTL_ARBSIZE_512 0x00024000 |
| #define | UDMA_CHCTL_ARBSIZE_1024 0x00028000 |
| #define | UDMA_CHCTL_XFERSIZE_M 0x00003FF0 |
| #define | UDMA_CHCTL_NXTUSEBURST 0x00000008 |
| #define | UDMA_CHCTL_XFERMODE_M 0x00000007 |
| #define | UDMA_CHCTL_XFERMODE_STOP 0x00000000 |
| #define | UDMA_CHCTL_XFERMODE_BASIC 0x00000001 |
| #define | UDMA_CHCTL_XFERMODE_AUTO 0x00000002 |
| #define | UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 |
| #define | UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 |
| #define | UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 |
| #define | UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 |
| #define | UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 |
| #define | UDMA_CHCTL_XFERSIZE_S 4 |
| #define | NVIC_INT_TYPE_LINES_M 0x0000001F |
| #define | NVIC_INT_TYPE_LINES_S 0 |
| #define | NVIC_ACTLR_DISOOFP 0x00000200 |
| #define | NVIC_ACTLR_DISFPCA 0x00000100 |
| #define | NVIC_ACTLR_DISFOLD 0x00000004 |
| #define | NVIC_ACTLR_DISWBUF 0x00000002 |
| #define | NVIC_ACTLR_DISMCYC 0x00000001 |
| #define | NVIC_ST_CTRL_COUNT 0x00010000 |
| #define | NVIC_ST_CTRL_CLK_SRC 0x00000004 |
| #define | NVIC_ST_CTRL_INTEN 0x00000002 |
| #define | NVIC_ST_CTRL_ENABLE 0x00000001 |
| #define | NVIC_ST_RELOAD_M 0x00FFFFFF |
| #define | NVIC_ST_RELOAD_S 0 |
| #define | NVIC_ST_CURRENT_M 0x00FFFFFF |
| #define | NVIC_ST_CURRENT_S 0 |
| #define | NVIC_ST_CAL_NOREF 0x80000000 |
| #define | NVIC_ST_CAL_SKEW 0x40000000 |
| #define | NVIC_ST_CAL_ONEMS_M 0x00FFFFFF |
| #define | NVIC_ST_CAL_ONEMS_S 0 |
| #define | NVIC_EN0_INT_M 0xFFFFFFFF |
| #define | NVIC_EN0_INT0 0x00000001 |
| #define | NVIC_EN0_INT1 0x00000002 |
| #define | NVIC_EN0_INT2 0x00000004 |
| #define | NVIC_EN0_INT3 0x00000008 |
| #define | NVIC_EN0_INT4 0x00000010 |
| #define | NVIC_EN0_INT5 0x00000020 |
| #define | NVIC_EN0_INT6 0x00000040 |
| #define | NVIC_EN0_INT7 0x00000080 |
| #define | NVIC_EN0_INT8 0x00000100 |
| #define | NVIC_EN0_INT9 0x00000200 |
| #define | NVIC_EN0_INT10 0x00000400 |
| #define | NVIC_EN0_INT11 0x00000800 |
| #define | NVIC_EN0_INT12 0x00001000 |
| #define | NVIC_EN0_INT13 0x00002000 |
| #define | NVIC_EN0_INT14 0x00004000 |
| #define | NVIC_EN0_INT15 0x00008000 |
| #define | NVIC_EN0_INT16 0x00010000 |
| #define | NVIC_EN0_INT17 0x00020000 |
| #define | NVIC_EN0_INT18 0x00040000 |
| #define | NVIC_EN0_INT19 0x00080000 |
| #define | NVIC_EN0_INT20 0x00100000 |
| #define | NVIC_EN0_INT21 0x00200000 |
| #define | NVIC_EN0_INT22 0x00400000 |
| #define | NVIC_EN0_INT23 0x00800000 |
| #define | NVIC_EN0_INT24 0x01000000 |
| #define | NVIC_EN0_INT25 0x02000000 |
| #define | NVIC_EN0_INT26 0x04000000 |
| #define | NVIC_EN0_INT27 0x08000000 |
| #define | NVIC_EN0_INT28 0x10000000 |
| #define | NVIC_EN0_INT29 0x20000000 |
| #define | NVIC_EN0_INT30 0x40000000 |
| #define | NVIC_EN0_INT31 0x80000000 |
| #define | NVIC_EN1_INT_M 0xFFFFFFFF |
| #define | NVIC_EN2_INT_M 0xFFFFFFFF |
| #define | NVIC_EN3_INT_M 0xFFFFFFFF |
| #define | NVIC_EN4_INT_M 0x000007FF |
| #define | NVIC_DIS0_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS0_INT0 0x00000001 |
| #define | NVIC_DIS0_INT1 0x00000002 |
| #define | NVIC_DIS0_INT2 0x00000004 |
| #define | NVIC_DIS0_INT3 0x00000008 |
| #define | NVIC_DIS0_INT4 0x00000010 |
| #define | NVIC_DIS0_INT5 0x00000020 |
| #define | NVIC_DIS0_INT6 0x00000040 |
| #define | NVIC_DIS0_INT7 0x00000080 |
| #define | NVIC_DIS0_INT8 0x00000100 |
| #define | NVIC_DIS0_INT9 0x00000200 |
| #define | NVIC_DIS0_INT10 0x00000400 |
| #define | NVIC_DIS0_INT11 0x00000800 |
| #define | NVIC_DIS0_INT12 0x00001000 |
| #define | NVIC_DIS0_INT13 0x00002000 |
| #define | NVIC_DIS0_INT14 0x00004000 |
| #define | NVIC_DIS0_INT15 0x00008000 |
| #define | NVIC_DIS0_INT16 0x00010000 |
| #define | NVIC_DIS0_INT17 0x00020000 |
| #define | NVIC_DIS0_INT18 0x00040000 |
| #define | NVIC_DIS0_INT19 0x00080000 |
| #define | NVIC_DIS0_INT20 0x00100000 |
| #define | NVIC_DIS0_INT21 0x00200000 |
| #define | NVIC_DIS0_INT22 0x00400000 |
| #define | NVIC_DIS0_INT23 0x00800000 |
| #define | NVIC_DIS0_INT24 0x01000000 |
| #define | NVIC_DIS0_INT25 0x02000000 |
| #define | NVIC_DIS0_INT26 0x04000000 |
| #define | NVIC_DIS0_INT27 0x08000000 |
| #define | NVIC_DIS0_INT28 0x10000000 |
| #define | NVIC_DIS0_INT29 0x20000000 |
| #define | NVIC_DIS0_INT30 0x40000000 |
| #define | NVIC_DIS0_INT31 0x80000000 |
| #define | NVIC_DIS1_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS2_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS3_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS4_INT_M 0x000007FF |
| #define | NVIC_PEND0_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND0_INT0 0x00000001 |
| #define | NVIC_PEND0_INT1 0x00000002 |
| #define | NVIC_PEND0_INT2 0x00000004 |
| #define | NVIC_PEND0_INT3 0x00000008 |
| #define | NVIC_PEND0_INT4 0x00000010 |
| #define | NVIC_PEND0_INT5 0x00000020 |
| #define | NVIC_PEND0_INT6 0x00000040 |
| #define | NVIC_PEND0_INT7 0x00000080 |
| #define | NVIC_PEND0_INT8 0x00000100 |
| #define | NVIC_PEND0_INT9 0x00000200 |
| #define | NVIC_PEND0_INT10 0x00000400 |
| #define | NVIC_PEND0_INT11 0x00000800 |
| #define | NVIC_PEND0_INT12 0x00001000 |
| #define | NVIC_PEND0_INT13 0x00002000 |
| #define | NVIC_PEND0_INT14 0x00004000 |
| #define | NVIC_PEND0_INT15 0x00008000 |
| #define | NVIC_PEND0_INT16 0x00010000 |
| #define | NVIC_PEND0_INT17 0x00020000 |
| #define | NVIC_PEND0_INT18 0x00040000 |
| #define | NVIC_PEND0_INT19 0x00080000 |
| #define | NVIC_PEND0_INT20 0x00100000 |
| #define | NVIC_PEND0_INT21 0x00200000 |
| #define | NVIC_PEND0_INT22 0x00400000 |
| #define | NVIC_PEND0_INT23 0x00800000 |
| #define | NVIC_PEND0_INT24 0x01000000 |
| #define | NVIC_PEND0_INT25 0x02000000 |
| #define | NVIC_PEND0_INT26 0x04000000 |
| #define | NVIC_PEND0_INT27 0x08000000 |
| #define | NVIC_PEND0_INT28 0x10000000 |
| #define | NVIC_PEND0_INT29 0x20000000 |
| #define | NVIC_PEND0_INT30 0x40000000 |
| #define | NVIC_PEND0_INT31 0x80000000 |
| #define | NVIC_PEND1_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND2_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND3_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND4_INT_M 0x000007FF |
| #define | NVIC_UNPEND0_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND0_INT0 0x00000001 |
| #define | NVIC_UNPEND0_INT1 0x00000002 |
| #define | NVIC_UNPEND0_INT2 0x00000004 |
| #define | NVIC_UNPEND0_INT3 0x00000008 |
| #define | NVIC_UNPEND0_INT4 0x00000010 |
| #define | NVIC_UNPEND0_INT5 0x00000020 |
| #define | NVIC_UNPEND0_INT6 0x00000040 |
| #define | NVIC_UNPEND0_INT7 0x00000080 |
| #define | NVIC_UNPEND0_INT8 0x00000100 |
| #define | NVIC_UNPEND0_INT9 0x00000200 |
| #define | NVIC_UNPEND0_INT10 0x00000400 |
| #define | NVIC_UNPEND0_INT11 0x00000800 |
| #define | NVIC_UNPEND0_INT12 0x00001000 |
| #define | NVIC_UNPEND0_INT13 0x00002000 |
| #define | NVIC_UNPEND0_INT14 0x00004000 |
| #define | NVIC_UNPEND0_INT15 0x00008000 |
| #define | NVIC_UNPEND0_INT16 0x00010000 |
| #define | NVIC_UNPEND0_INT17 0x00020000 |
| #define | NVIC_UNPEND0_INT18 0x00040000 |
| #define | NVIC_UNPEND0_INT19 0x00080000 |
| #define | NVIC_UNPEND0_INT20 0x00100000 |
| #define | NVIC_UNPEND0_INT21 0x00200000 |
| #define | NVIC_UNPEND0_INT22 0x00400000 |
| #define | NVIC_UNPEND0_INT23 0x00800000 |
| #define | NVIC_UNPEND0_INT24 0x01000000 |
| #define | NVIC_UNPEND0_INT25 0x02000000 |
| #define | NVIC_UNPEND0_INT26 0x04000000 |
| #define | NVIC_UNPEND0_INT27 0x08000000 |
| #define | NVIC_UNPEND0_INT28 0x10000000 |
| #define | NVIC_UNPEND0_INT29 0x20000000 |
| #define | NVIC_UNPEND0_INT30 0x40000000 |
| #define | NVIC_UNPEND0_INT31 0x80000000 |
| #define | NVIC_UNPEND1_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND1_INT32 0x00000001 |
| #define | NVIC_UNPEND1_INT33 0x00000002 |
| #define | NVIC_UNPEND1_INT34 0x00000004 |
| #define | NVIC_UNPEND1_INT35 0x00000008 |
| #define | NVIC_UNPEND1_INT36 0x00000010 |
| #define | NVIC_UNPEND1_INT37 0x00000020 |
| #define | NVIC_UNPEND1_INT38 0x00000040 |
| #define | NVIC_UNPEND1_INT39 0x00000080 |
| #define | NVIC_UNPEND1_INT40 0x00000100 |
| #define | NVIC_UNPEND1_INT41 0x00000200 |
| #define | NVIC_UNPEND1_INT42 0x00000400 |
| #define | NVIC_UNPEND1_INT43 0x00000800 |
| #define | NVIC_UNPEND1_INT44 0x00001000 |
| #define | NVIC_UNPEND1_INT45 0x00002000 |
| #define | NVIC_UNPEND1_INT46 0x00004000 |
| #define | NVIC_UNPEND1_INT47 0x00008000 |
| #define | NVIC_UNPEND1_INT48 0x00010000 |
| #define | NVIC_UNPEND1_INT49 0x00020000 |
| #define | NVIC_UNPEND1_INT50 0x00040000 |
| #define | NVIC_UNPEND1_INT51 0x00080000 |
| #define | NVIC_UNPEND1_INT52 0x00100000 |
| #define | NVIC_UNPEND1_INT53 0x00200000 |
| #define | NVIC_UNPEND1_INT54 0x00400000 |
| #define | NVIC_UNPEND1_INT55 0x00800000 |
| #define | NVIC_UNPEND2_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND3_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND4_INT_M 0x000007FF |
| #define | NVIC_ACTIVE0_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE0_INT0 0x00000001 |
| #define | NVIC_ACTIVE0_INT1 0x00000002 |
| #define | NVIC_ACTIVE0_INT2 0x00000004 |
| #define | NVIC_ACTIVE0_INT3 0x00000008 |
| #define | NVIC_ACTIVE0_INT4 0x00000010 |
| #define | NVIC_ACTIVE0_INT5 0x00000020 |
| #define | NVIC_ACTIVE0_INT6 0x00000040 |
| #define | NVIC_ACTIVE0_INT7 0x00000080 |
| #define | NVIC_ACTIVE0_INT8 0x00000100 |
| #define | NVIC_ACTIVE0_INT9 0x00000200 |
| #define | NVIC_ACTIVE0_INT10 0x00000400 |
| #define | NVIC_ACTIVE0_INT11 0x00000800 |
| #define | NVIC_ACTIVE0_INT12 0x00001000 |
| #define | NVIC_ACTIVE0_INT13 0x00002000 |
| #define | NVIC_ACTIVE0_INT14 0x00004000 |
| #define | NVIC_ACTIVE0_INT15 0x00008000 |
| #define | NVIC_ACTIVE0_INT16 0x00010000 |
| #define | NVIC_ACTIVE0_INT17 0x00020000 |
| #define | NVIC_ACTIVE0_INT18 0x00040000 |
| #define | NVIC_ACTIVE0_INT19 0x00080000 |
| #define | NVIC_ACTIVE0_INT20 0x00100000 |
| #define | NVIC_ACTIVE0_INT21 0x00200000 |
| #define | NVIC_ACTIVE0_INT22 0x00400000 |
| #define | NVIC_ACTIVE0_INT23 0x00800000 |
| #define | NVIC_ACTIVE0_INT24 0x01000000 |
| #define | NVIC_ACTIVE0_INT25 0x02000000 |
| #define | NVIC_ACTIVE0_INT26 0x04000000 |
| #define | NVIC_ACTIVE0_INT27 0x08000000 |
| #define | NVIC_ACTIVE0_INT28 0x10000000 |
| #define | NVIC_ACTIVE0_INT29 0x20000000 |
| #define | NVIC_ACTIVE0_INT30 0x40000000 |
| #define | NVIC_ACTIVE0_INT31 0x80000000 |
| #define | NVIC_ACTIVE1_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE2_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE3_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE4_INT_M 0x000007FF |
| #define | NVIC_PRI0_INT3_M 0xE0000000 |
| #define | NVIC_PRI0_INT2_M 0x00E00000 |
| #define | NVIC_PRI0_INT1_M 0x0000E000 |
| #define | NVIC_PRI0_INT0_M 0x000000E0 |
| #define | NVIC_PRI0_INT3_S 29 |
| #define | NVIC_PRI0_INT2_S 21 |
| #define | NVIC_PRI0_INT1_S 13 |
| #define | NVIC_PRI0_INT0_S 5 |
| #define | NVIC_PRI1_INT7_M 0xE0000000 |
| #define | NVIC_PRI1_INT6_M 0x00E00000 |
| #define | NVIC_PRI1_INT5_M 0x0000E000 |
| #define | NVIC_PRI1_INT4_M 0x000000E0 |
| #define | NVIC_PRI1_INT7_S 29 |
| #define | NVIC_PRI1_INT6_S 21 |
| #define | NVIC_PRI1_INT5_S 13 |
| #define | NVIC_PRI1_INT4_S 5 |
| #define | NVIC_PRI2_INT11_M 0xE0000000 |
| #define | NVIC_PRI2_INT10_M 0x00E00000 |
| #define | NVIC_PRI2_INT9_M 0x0000E000 |
| #define | NVIC_PRI2_INT8_M 0x000000E0 |
| #define | NVIC_PRI2_INT11_S 29 |
| #define | NVIC_PRI2_INT10_S 21 |
| #define | NVIC_PRI2_INT9_S 13 |
| #define | NVIC_PRI2_INT8_S 5 |
| #define | NVIC_PRI3_INT15_M 0xE0000000 |
| #define | NVIC_PRI3_INT14_M 0x00E00000 |
| #define | NVIC_PRI3_INT13_M 0x0000E000 |
| #define | NVIC_PRI3_INT12_M 0x000000E0 |
| #define | NVIC_PRI3_INT15_S 29 |
| #define | NVIC_PRI3_INT14_S 21 |
| #define | NVIC_PRI3_INT13_S 13 |
| #define | NVIC_PRI3_INT12_S 5 |
| #define | NVIC_PRI4_INT19_M 0xE0000000 |
| #define | NVIC_PRI4_INT18_M 0x00E00000 |
| #define | NVIC_PRI4_INT17_M 0x0000E000 |
| #define | NVIC_PRI4_INT16_M 0x000000E0 |
| #define | NVIC_PRI4_INT19_S 29 |
| #define | NVIC_PRI4_INT18_S 21 |
| #define | NVIC_PRI4_INT17_S 13 |
| #define | NVIC_PRI4_INT16_S 5 |
| #define | NVIC_PRI5_INT23_M 0xE0000000 |
| #define | NVIC_PRI5_INT22_M 0x00E00000 |
| #define | NVIC_PRI5_INT21_M 0x0000E000 |
| #define | NVIC_PRI5_INT20_M 0x000000E0 |
| #define | NVIC_PRI5_INT23_S 29 |
| #define | NVIC_PRI5_INT22_S 21 |
| #define | NVIC_PRI5_INT21_S 13 |
| #define | NVIC_PRI5_INT20_S 5 |
| #define | NVIC_PRI6_INT27_M 0xE0000000 |
| #define | NVIC_PRI6_INT26_M 0x00E00000 |
| #define | NVIC_PRI6_INT25_M 0x0000E000 |
| #define | NVIC_PRI6_INT24_M 0x000000E0 |
| #define | NVIC_PRI6_INT27_S 29 |
| #define | NVIC_PRI6_INT26_S 21 |
| #define | NVIC_PRI6_INT25_S 13 |
| #define | NVIC_PRI6_INT24_S 5 |
| #define | NVIC_PRI7_INT31_M 0xE0000000 |
| #define | NVIC_PRI7_INT30_M 0x00E00000 |
| #define | NVIC_PRI7_INT29_M 0x0000E000 |
| #define | NVIC_PRI7_INT28_M 0x000000E0 |
| #define | NVIC_PRI7_INT31_S 29 |
| #define | NVIC_PRI7_INT30_S 21 |
| #define | NVIC_PRI7_INT29_S 13 |
| #define | NVIC_PRI7_INT28_S 5 |
| #define | NVIC_PRI8_INT35_M 0xE0000000 |
| #define | NVIC_PRI8_INT34_M 0x00E00000 |
| #define | NVIC_PRI8_INT33_M 0x0000E000 |
| #define | NVIC_PRI8_INT32_M 0x000000E0 |
| #define | NVIC_PRI8_INT35_S 29 |
| #define | NVIC_PRI8_INT34_S 21 |
| #define | NVIC_PRI8_INT33_S 13 |
| #define | NVIC_PRI8_INT32_S 5 |
| #define | NVIC_PRI9_INT39_M 0xE0000000 |
| #define | NVIC_PRI9_INT38_M 0x00E00000 |
| #define | NVIC_PRI9_INT37_M 0x0000E000 |
| #define | NVIC_PRI9_INT36_M 0x000000E0 |
| #define | NVIC_PRI9_INT39_S 29 |
| #define | NVIC_PRI9_INT38_S 21 |
| #define | NVIC_PRI9_INT37_S 13 |
| #define | NVIC_PRI9_INT36_S 5 |
| #define | NVIC_PRI10_INT43_M 0xE0000000 |
| #define | NVIC_PRI10_INT42_M 0x00E00000 |
| #define | NVIC_PRI10_INT41_M 0x0000E000 |
| #define | NVIC_PRI10_INT40_M 0x000000E0 |
| #define | NVIC_PRI10_INT43_S 29 |
| #define | NVIC_PRI10_INT42_S 21 |
| #define | NVIC_PRI10_INT41_S 13 |
| #define | NVIC_PRI10_INT40_S 5 |
| #define | NVIC_PRI11_INT47_M 0xE0000000 |
| #define | NVIC_PRI11_INT46_M 0x00E00000 |
| #define | NVIC_PRI11_INT45_M 0x0000E000 |
| #define | NVIC_PRI11_INT44_M 0x000000E0 |
| #define | NVIC_PRI11_INT47_S 29 |
| #define | NVIC_PRI11_INT46_S 21 |
| #define | NVIC_PRI11_INT45_S 13 |
| #define | NVIC_PRI11_INT44_S 5 |
| #define | NVIC_PRI12_INT51_M 0xE0000000 |
| #define | NVIC_PRI12_INT50_M 0x00E00000 |
| #define | NVIC_PRI12_INT49_M 0x0000E000 |
| #define | NVIC_PRI12_INT48_M 0x000000E0 |
| #define | NVIC_PRI12_INT51_S 29 |
| #define | NVIC_PRI12_INT50_S 21 |
| #define | NVIC_PRI12_INT49_S 13 |
| #define | NVIC_PRI12_INT48_S 5 |
| #define | NVIC_PRI13_INT55_M 0xE0000000 |
| #define | NVIC_PRI13_INT54_M 0x00E00000 |
| #define | NVIC_PRI13_INT53_M 0x0000E000 |
| #define | NVIC_PRI13_INT52_M 0x000000E0 |
| #define | NVIC_PRI13_INT55_S 29 |
| #define | NVIC_PRI13_INT54_S 21 |
| #define | NVIC_PRI13_INT53_S 13 |
| #define | NVIC_PRI13_INT52_S 5 |
| #define | NVIC_PRI14_INTD_M 0xE0000000 |
| #define | NVIC_PRI14_INTC_M 0x00E00000 |
| #define | NVIC_PRI14_INTB_M 0x0000E000 |
| #define | NVIC_PRI14_INTA_M 0x000000E0 |
| #define | NVIC_PRI14_INTD_S 29 |
| #define | NVIC_PRI14_INTC_S 21 |
| #define | NVIC_PRI14_INTB_S 13 |
| #define | NVIC_PRI14_INTA_S 5 |
| #define | NVIC_PRI15_INTD_M 0xE0000000 |
| #define | NVIC_PRI15_INTC_M 0x00E00000 |
| #define | NVIC_PRI15_INTB_M 0x0000E000 |
| #define | NVIC_PRI15_INTA_M 0x000000E0 |
| #define | NVIC_PRI15_INTD_S 29 |
| #define | NVIC_PRI15_INTC_S 21 |
| #define | NVIC_PRI15_INTB_S 13 |
| #define | NVIC_PRI15_INTA_S 5 |
| #define | NVIC_PRI16_INTD_M 0xE0000000 |
| #define | NVIC_PRI16_INTC_M 0x00E00000 |
| #define | NVIC_PRI16_INTB_M 0x0000E000 |
| #define | NVIC_PRI16_INTA_M 0x000000E0 |
| #define | NVIC_PRI16_INTD_S 29 |
| #define | NVIC_PRI16_INTC_S 21 |
| #define | NVIC_PRI16_INTB_S 13 |
| #define | NVIC_PRI16_INTA_S 5 |
| #define | NVIC_PRI17_INTD_M 0xE0000000 |
| #define | NVIC_PRI17_INTC_M 0x00E00000 |
| #define | NVIC_PRI17_INTB_M 0x0000E000 |
| #define | NVIC_PRI17_INTA_M 0x000000E0 |
| #define | NVIC_PRI17_INTD_S 29 |
| #define | NVIC_PRI17_INTC_S 21 |
| #define | NVIC_PRI17_INTB_S 13 |
| #define | NVIC_PRI17_INTA_S 5 |
| #define | NVIC_PRI18_INTD_M 0xE0000000 |
| #define | NVIC_PRI18_INTC_M 0x00E00000 |
| #define | NVIC_PRI18_INTB_M 0x0000E000 |
| #define | NVIC_PRI18_INTA_M 0x000000E0 |
| #define | NVIC_PRI18_INTD_S 29 |
| #define | NVIC_PRI18_INTC_S 21 |
| #define | NVIC_PRI18_INTB_S 13 |
| #define | NVIC_PRI18_INTA_S 5 |
| #define | NVIC_PRI19_INTD_M 0xE0000000 |
| #define | NVIC_PRI19_INTC_M 0x00E00000 |
| #define | NVIC_PRI19_INTB_M 0x0000E000 |
| #define | NVIC_PRI19_INTA_M 0x000000E0 |
| #define | NVIC_PRI19_INTD_S 29 |
| #define | NVIC_PRI19_INTC_S 21 |
| #define | NVIC_PRI19_INTB_S 13 |
| #define | NVIC_PRI19_INTA_S 5 |
| #define | NVIC_PRI20_INTD_M 0xE0000000 |
| #define | NVIC_PRI20_INTC_M 0x00E00000 |
| #define | NVIC_PRI20_INTB_M 0x0000E000 |
| #define | NVIC_PRI20_INTA_M 0x000000E0 |
| #define | NVIC_PRI20_INTD_S 29 |
| #define | NVIC_PRI20_INTC_S 21 |
| #define | NVIC_PRI20_INTB_S 13 |
| #define | NVIC_PRI20_INTA_S 5 |
| #define | NVIC_PRI21_INTD_M 0xE0000000 |
| #define | NVIC_PRI21_INTC_M 0x00E00000 |
| #define | NVIC_PRI21_INTB_M 0x0000E000 |
| #define | NVIC_PRI21_INTA_M 0x000000E0 |
| #define | NVIC_PRI21_INTD_S 29 |
| #define | NVIC_PRI21_INTC_S 21 |
| #define | NVIC_PRI21_INTB_S 13 |
| #define | NVIC_PRI21_INTA_S 5 |
| #define | NVIC_PRI22_INTD_M 0xE0000000 |
| #define | NVIC_PRI22_INTC_M 0x00E00000 |
| #define | NVIC_PRI22_INTB_M 0x0000E000 |
| #define | NVIC_PRI22_INTA_M 0x000000E0 |
| #define | NVIC_PRI22_INTD_S 29 |
| #define | NVIC_PRI22_INTC_S 21 |
| #define | NVIC_PRI22_INTB_S 13 |
| #define | NVIC_PRI22_INTA_S 5 |
| #define | NVIC_PRI23_INTD_M 0xE0000000 |
| #define | NVIC_PRI23_INTC_M 0x00E00000 |
| #define | NVIC_PRI23_INTB_M 0x0000E000 |
| #define | NVIC_PRI23_INTA_M 0x000000E0 |
| #define | NVIC_PRI23_INTD_S 29 |
| #define | NVIC_PRI23_INTC_S 21 |
| #define | NVIC_PRI23_INTB_S 13 |
| #define | NVIC_PRI23_INTA_S 5 |
| #define | NVIC_PRI24_INTD_M 0xE0000000 |
| #define | NVIC_PRI24_INTC_M 0x00E00000 |
| #define | NVIC_PRI24_INTB_M 0x0000E000 |
| #define | NVIC_PRI24_INTA_M 0x000000E0 |
| #define | NVIC_PRI24_INTD_S 29 |
| #define | NVIC_PRI24_INTC_S 21 |
| #define | NVIC_PRI24_INTB_S 13 |
| #define | NVIC_PRI24_INTA_S 5 |
| #define | NVIC_PRI25_INTD_M 0xE0000000 |
| #define | NVIC_PRI25_INTC_M 0x00E00000 |
| #define | NVIC_PRI25_INTB_M 0x0000E000 |
| #define | NVIC_PRI25_INTA_M 0x000000E0 |
| #define | NVIC_PRI25_INTD_S 29 |
| #define | NVIC_PRI25_INTC_S 21 |
| #define | NVIC_PRI25_INTB_S 13 |
| #define | NVIC_PRI25_INTA_S 5 |
| #define | NVIC_PRI26_INTD_M 0xE0000000 |
| #define | NVIC_PRI26_INTC_M 0x00E00000 |
| #define | NVIC_PRI26_INTB_M 0x0000E000 |
| #define | NVIC_PRI26_INTA_M 0x000000E0 |
| #define | NVIC_PRI26_INTD_S 29 |
| #define | NVIC_PRI26_INTC_S 21 |
| #define | NVIC_PRI26_INTB_S 13 |
| #define | NVIC_PRI26_INTA_S 5 |
| #define | NVIC_PRI27_INTD_M 0xE0000000 |
| #define | NVIC_PRI27_INTC_M 0x00E00000 |
| #define | NVIC_PRI27_INTB_M 0x0000E000 |
| #define | NVIC_PRI27_INTA_M 0x000000E0 |
| #define | NVIC_PRI27_INTD_S 29 |
| #define | NVIC_PRI27_INTC_S 21 |
| #define | NVIC_PRI27_INTB_S 13 |
| #define | NVIC_PRI27_INTA_S 5 |
| #define | NVIC_PRI28_INTD_M 0xE0000000 |
| #define | NVIC_PRI28_INTC_M 0x00E00000 |
| #define | NVIC_PRI28_INTB_M 0x0000E000 |
| #define | NVIC_PRI28_INTA_M 0x000000E0 |
| #define | NVIC_PRI28_INTD_S 29 |
| #define | NVIC_PRI28_INTC_S 21 |
| #define | NVIC_PRI28_INTB_S 13 |
| #define | NVIC_PRI28_INTA_S 5 |
| #define | NVIC_PRI29_INTD_M 0xE0000000 |
| #define | NVIC_PRI29_INTC_M 0x00E00000 |
| #define | NVIC_PRI29_INTB_M 0x0000E000 |
| #define | NVIC_PRI29_INTA_M 0x000000E0 |
| #define | NVIC_PRI29_INTD_S 29 |
| #define | NVIC_PRI29_INTC_S 21 |
| #define | NVIC_PRI29_INTB_S 13 |
| #define | NVIC_PRI29_INTA_S 5 |
| #define | NVIC_PRI30_INTD_M 0xE0000000 |
| #define | NVIC_PRI30_INTC_M 0x00E00000 |
| #define | NVIC_PRI30_INTB_M 0x0000E000 |
| #define | NVIC_PRI30_INTA_M 0x000000E0 |
| #define | NVIC_PRI30_INTD_S 29 |
| #define | NVIC_PRI30_INTC_S 21 |
| #define | NVIC_PRI30_INTB_S 13 |
| #define | NVIC_PRI30_INTA_S 5 |
| #define | NVIC_PRI31_INTD_M 0xE0000000 |
| #define | NVIC_PRI31_INTC_M 0x00E00000 |
| #define | NVIC_PRI31_INTB_M 0x0000E000 |
| #define | NVIC_PRI31_INTA_M 0x000000E0 |
| #define | NVIC_PRI31_INTD_S 29 |
| #define | NVIC_PRI31_INTC_S 21 |
| #define | NVIC_PRI31_INTB_S 13 |
| #define | NVIC_PRI31_INTA_S 5 |
| #define | NVIC_PRI32_INTD_M 0xE0000000 |
| #define | NVIC_PRI32_INTC_M 0x00E00000 |
| #define | NVIC_PRI32_INTB_M 0x0000E000 |
| #define | NVIC_PRI32_INTA_M 0x000000E0 |
| #define | NVIC_PRI32_INTD_S 29 |
| #define | NVIC_PRI32_INTC_S 21 |
| #define | NVIC_PRI32_INTB_S 13 |
| #define | NVIC_PRI32_INTA_S 5 |
| #define | NVIC_PRI33_INTD_M 0xE0000000 |
| #define | NVIC_PRI33_INTC_M 0x00E00000 |
| #define | NVIC_PRI33_INTB_M 0x0000E000 |
| #define | NVIC_PRI33_INTA_M 0x000000E0 |
| #define | NVIC_PRI33_INTD_S 29 |
| #define | NVIC_PRI33_INTC_S 21 |
| #define | NVIC_PRI33_INTB_S 13 |
| #define | NVIC_PRI33_INTA_S 5 |
| #define | NVIC_PRI34_INTD_M 0xE0000000 |
| #define | NVIC_PRI34_INTC_M 0x00E00000 |
| #define | NVIC_PRI34_INTB_M 0x0000E000 |
| #define | NVIC_PRI34_INTA_M 0x000000E0 |
| #define | NVIC_PRI34_INTD_S 29 |
| #define | NVIC_PRI34_INTC_S 21 |
| #define | NVIC_PRI34_INTB_S 13 |
| #define | NVIC_PRI34_INTA_S 5 |
| #define | NVIC_CPUID_IMP_M 0xFF000000 |
| #define | NVIC_CPUID_IMP_ARM 0x41000000 |
| #define | NVIC_CPUID_VAR_M 0x00F00000 |
| #define | NVIC_CPUID_CON_M 0x000F0000 |
| #define | NVIC_CPUID_PARTNO_M 0x0000FFF0 |
| #define | NVIC_CPUID_PARTNO_CM4 0x0000C240 |
| #define | NVIC_CPUID_REV_M 0x0000000F |
| #define | NVIC_INT_CTRL_NMI_SET 0x80000000 |
| #define | NVIC_INT_CTRL_PEND_SV 0x10000000 |
| #define | NVIC_INT_CTRL_UNPEND_SV 0x08000000 |
| #define | NVIC_INT_CTRL_PENDSTSET 0x04000000 |
| #define | NVIC_INT_CTRL_PENDSTCLR 0x02000000 |
| #define | NVIC_INT_CTRL_ISR_PRE 0x00800000 |
| #define | NVIC_INT_CTRL_ISR_PEND 0x00400000 |
| #define | NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 |
| #define | NVIC_INT_CTRL_VEC_PEN_NMI 0x00002000 |
| #define | NVIC_INT_CTRL_VEC_PEN_HARD 0x00003000 |
| #define | NVIC_INT_CTRL_VEC_PEN_MEM 0x00004000 |
| #define | NVIC_INT_CTRL_VEC_PEN_BUS 0x00005000 |
| #define | NVIC_INT_CTRL_VEC_PEN_USG 0x00006000 |
| #define | NVIC_INT_CTRL_VEC_PEN_SVC 0x0000B000 |
| #define | NVIC_INT_CTRL_VEC_PEN_PNDSV 0x0000E000 |
| #define | NVIC_INT_CTRL_VEC_PEN_TICK 0x0000F000 |
| #define | NVIC_INT_CTRL_RET_BASE 0x00000800 |
| #define | NVIC_INT_CTRL_VEC_ACT_M 0x000000FF |
| #define | NVIC_INT_CTRL_VEC_ACT_S 0 |
| #define | NVIC_VTABLE_BASE 0x20000000 |
| #define | NVIC_VTABLE_OFFSET_M 0x1FFFFC00 |
| #define | NVIC_VTABLE_OFFSET_S 10 |
| #define | NVIC_APINT_VECTKEY_M 0xFFFF0000 |
| #define | NVIC_APINT_VECTKEY 0x05FA0000 |
| #define | NVIC_APINT_ENDIANESS 0x00008000 |
| #define | NVIC_APINT_PRIGROUP_M 0x00000700 |
| #define | NVIC_APINT_PRIGROUP_7_1 0x00000000 |
| #define | NVIC_APINT_PRIGROUP_6_2 0x00000100 |
| #define | NVIC_APINT_PRIGROUP_5_3 0x00000200 |
| #define | NVIC_APINT_PRIGROUP_4_4 0x00000300 |
| #define | NVIC_APINT_PRIGROUP_3_5 0x00000400 |
| #define | NVIC_APINT_PRIGROUP_2_6 0x00000500 |
| #define | NVIC_APINT_PRIGROUP_1_7 0x00000600 |
| #define | NVIC_APINT_PRIGROUP_0_8 0x00000700 |
| #define | NVIC_APINT_SYSRESETREQ 0x00000004 |
| #define | NVIC_APINT_VECT_CLR_ACT 0x00000002 |
| #define | NVIC_APINT_VECT_RESET 0x00000001 |
| #define | NVIC_SYS_CTRL_SEVONPEND 0x00000010 |
| #define | NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 |
| #define | NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 |
| #define | NVIC_CFG_CTRL_STKALIGN 0x00000200 |
| #define | NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 |
| #define | NVIC_CFG_CTRL_DIV0 0x00000010 |
| #define | NVIC_CFG_CTRL_UNALIGNED 0x00000008 |
| #define | NVIC_CFG_CTRL_MAIN_PEND 0x00000002 |
| #define | NVIC_CFG_CTRL_BASE_THR 0x00000001 |
| #define | NVIC_SYS_PRI1_USAGE_M 0x00E00000 |
| #define | NVIC_SYS_PRI1_BUS_M 0x0000E000 |
| #define | NVIC_SYS_PRI1_MEM_M 0x000000E0 |
| #define | NVIC_SYS_PRI1_USAGE_S 21 |
| #define | NVIC_SYS_PRI1_BUS_S 13 |
| #define | NVIC_SYS_PRI1_MEM_S 5 |
| #define | NVIC_SYS_PRI2_SVC_M 0xE0000000 |
| #define | NVIC_SYS_PRI2_SVC_S 29 |
| #define | NVIC_SYS_PRI3_TICK_M 0xE0000000 |
| #define | NVIC_SYS_PRI3_PENDSV_M 0x00E00000 |
| #define | NVIC_SYS_PRI3_DEBUG_M 0x000000E0 |
| #define | NVIC_SYS_PRI3_TICK_S 29 |
| #define | NVIC_SYS_PRI3_PENDSV_S 21 |
| #define | NVIC_SYS_PRI3_DEBUG_S 5 |
| #define | NVIC_SYS_HND_CTRL_USAGE 0x00040000 |
| #define | NVIC_SYS_HND_CTRL_BUS 0x00020000 |
| #define | NVIC_SYS_HND_CTRL_MEM 0x00010000 |
| #define | NVIC_SYS_HND_CTRL_SVC 0x00008000 |
| #define | NVIC_SYS_HND_CTRL_BUSP 0x00004000 |
| #define | NVIC_SYS_HND_CTRL_MEMP 0x00002000 |
| #define | NVIC_SYS_HND_CTRL_USAGEP 0x00001000 |
| #define | NVIC_SYS_HND_CTRL_TICK 0x00000800 |
| #define | NVIC_SYS_HND_CTRL_PNDSV 0x00000400 |
| #define | NVIC_SYS_HND_CTRL_MON 0x00000100 |
| #define | NVIC_SYS_HND_CTRL_SVCA 0x00000080 |
| #define | NVIC_SYS_HND_CTRL_USGA 0x00000008 |
| #define | NVIC_SYS_HND_CTRL_BUSA 0x00000002 |
| #define | NVIC_SYS_HND_CTRL_MEMA 0x00000001 |
| #define | NVIC_FAULT_STAT_DIV0 0x02000000 |
| #define | NVIC_FAULT_STAT_UNALIGN 0x01000000 |
| #define | NVIC_FAULT_STAT_NOCP 0x00080000 |
| #define | NVIC_FAULT_STAT_INVPC 0x00040000 |
| #define | NVIC_FAULT_STAT_INVSTAT 0x00020000 |
| #define | NVIC_FAULT_STAT_UNDEF 0x00010000 |
| #define | NVIC_FAULT_STAT_BFARV 0x00008000 |
| #define | NVIC_FAULT_STAT_BLSPERR 0x00002000 |
| #define | NVIC_FAULT_STAT_BSTKE 0x00001000 |
| #define | NVIC_FAULT_STAT_BUSTKE 0x00000800 |
| #define | NVIC_FAULT_STAT_IMPRE 0x00000400 |
| #define | NVIC_FAULT_STAT_PRECISE 0x00000200 |
| #define | NVIC_FAULT_STAT_IBUS 0x00000100 |
| #define | NVIC_FAULT_STAT_MMARV 0x00000080 |
| #define | NVIC_FAULT_STAT_MLSPERR 0x00000020 |
| #define | NVIC_FAULT_STAT_MSTKE 0x00000010 |
| #define | NVIC_FAULT_STAT_MUSTKE 0x00000008 |
| #define | NVIC_FAULT_STAT_DERR 0x00000002 |
| #define | NVIC_FAULT_STAT_IERR 0x00000001 |
| #define | NVIC_HFAULT_STAT_DBG 0x80000000 |
| #define | NVIC_HFAULT_STAT_FORCED 0x40000000 |
| #define | NVIC_HFAULT_STAT_VECT 0x00000002 |
| #define | NVIC_DEBUG_STAT_EXTRNL 0x00000010 |
| #define | NVIC_DEBUG_STAT_VCATCH 0x00000008 |
| #define | NVIC_DEBUG_STAT_DWTTRAP 0x00000004 |
| #define | NVIC_DEBUG_STAT_BKPT 0x00000002 |
| #define | NVIC_DEBUG_STAT_HALTED 0x00000001 |
| #define | NVIC_MM_ADDR_M 0xFFFFFFFF |
| #define | NVIC_MM_ADDR_S 0 |
| #define | NVIC_FAULT_ADDR_M 0xFFFFFFFF |
| #define | NVIC_FAULT_ADDR_S 0 |
| #define | NVIC_CPAC_CP11_M 0x00C00000 |
| #define | NVIC_CPAC_CP11_DIS 0x00000000 |
| #define | NVIC_CPAC_CP11_PRIV 0x00400000 |
| #define | NVIC_CPAC_CP11_FULL 0x00C00000 |
| #define | NVIC_CPAC_CP10_M 0x00300000 |
| #define | NVIC_CPAC_CP10_DIS 0x00000000 |
| #define | NVIC_CPAC_CP10_PRIV 0x00100000 |
| #define | NVIC_CPAC_CP10_FULL 0x00300000 |
| #define | NVIC_MPU_TYPE_IREGION_M 0x00FF0000 |
| #define | NVIC_MPU_TYPE_DREGION_M 0x0000FF00 |
| #define | NVIC_MPU_TYPE_SEPARATE 0x00000001 |
| #define | NVIC_MPU_TYPE_IREGION_S 16 |
| #define | NVIC_MPU_TYPE_DREGION_S 8 |
| #define | NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 |
| #define | NVIC_MPU_CTRL_HFNMIENA 0x00000002 |
| #define | NVIC_MPU_CTRL_ENABLE 0x00000001 |
| #define | NVIC_MPU_NUMBER_M 0x00000007 |
| #define | NVIC_MPU_NUMBER_S 0 |
| #define | NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE_VALID 0x00000010 |
| #define | NVIC_MPU_BASE_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE_ADDR_S 5 |
| #define | NVIC_MPU_BASE_REGION_S 0 |
| #define | NVIC_MPU_ATTR_XN 0x10000000 |
| #define | NVIC_MPU_ATTR_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE1_VALID 0x00000010 |
| #define | NVIC_MPU_BASE1_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE1_ADDR_S 5 |
| #define | NVIC_MPU_BASE1_REGION_S 0 |
| #define | NVIC_MPU_ATTR1_XN 0x10000000 |
| #define | NVIC_MPU_ATTR1_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR1_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR1_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR1_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR1_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR1_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR1_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR1_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE2_VALID 0x00000010 |
| #define | NVIC_MPU_BASE2_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE2_ADDR_S 5 |
| #define | NVIC_MPU_BASE2_REGION_S 0 |
| #define | NVIC_MPU_ATTR2_XN 0x10000000 |
| #define | NVIC_MPU_ATTR2_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR2_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR2_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR2_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR2_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR2_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR2_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR2_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE3_VALID 0x00000010 |
| #define | NVIC_MPU_BASE3_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE3_ADDR_S 5 |
| #define | NVIC_MPU_BASE3_REGION_S 0 |
| #define | NVIC_MPU_ATTR3_XN 0x10000000 |
| #define | NVIC_MPU_ATTR3_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR3_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR3_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR3_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR3_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR3_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR3_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR3_ENABLE 0x00000001 |
| #define | NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 |
| #define | NVIC_DBG_CTRL_DBGKEY 0xA05F0000 |
| #define | NVIC_DBG_CTRL_S_RESET_ST 0x02000000 |
| #define | NVIC_DBG_CTRL_S_RETIRE_ST 0x01000000 |
| #define | NVIC_DBG_CTRL_S_LOCKUP 0x00080000 |
| #define | NVIC_DBG_CTRL_S_SLEEP 0x00040000 |
| #define | NVIC_DBG_CTRL_S_HALT 0x00020000 |
| #define | NVIC_DBG_CTRL_S_REGRDY 0x00010000 |
| #define | NVIC_DBG_CTRL_C_SNAPSTALL 0x00000020 |
| #define | NVIC_DBG_CTRL_C_MASKINT 0x00000008 |
| #define | NVIC_DBG_CTRL_C_STEP 0x00000004 |
| #define | NVIC_DBG_CTRL_C_HALT 0x00000002 |
| #define | NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 |
| #define | NVIC_DBG_XFER_REG_WNR 0x00010000 |
| #define | NVIC_DBG_XFER_REG_SEL_M 0x0000001F |
| #define | NVIC_DBG_XFER_REG_R0 0x00000000 |
| #define | NVIC_DBG_XFER_REG_R1 0x00000001 |
| #define | NVIC_DBG_XFER_REG_R2 0x00000002 |
| #define | NVIC_DBG_XFER_REG_R3 0x00000003 |
| #define | NVIC_DBG_XFER_REG_R4 0x00000004 |
| #define | NVIC_DBG_XFER_REG_R5 0x00000005 |
| #define | NVIC_DBG_XFER_REG_R6 0x00000006 |
| #define | NVIC_DBG_XFER_REG_R7 0x00000007 |
| #define | NVIC_DBG_XFER_REG_R8 0x00000008 |
| #define | NVIC_DBG_XFER_REG_R9 0x00000009 |
| #define | NVIC_DBG_XFER_REG_R10 0x0000000A |
| #define | NVIC_DBG_XFER_REG_R11 0x0000000B |
| #define | NVIC_DBG_XFER_REG_R12 0x0000000C |
| #define | NVIC_DBG_XFER_REG_R13 0x0000000D |
| #define | NVIC_DBG_XFER_REG_R14 0x0000000E |
| #define | NVIC_DBG_XFER_REG_R15 0x0000000F |
| #define | NVIC_DBG_XFER_REG_FLAGS 0x00000010 |
| #define | NVIC_DBG_XFER_REG_MSP 0x00000011 |
| #define | NVIC_DBG_XFER_REG_PSP 0x00000012 |
| #define | NVIC_DBG_XFER_REG_DSP 0x00000013 |
| #define | NVIC_DBG_XFER_REG_CFBP 0x00000014 |
| #define | NVIC_DBG_DATA_M 0xFFFFFFFF |
| #define | NVIC_DBG_DATA_S 0 |
| #define | NVIC_DBG_INT_HARDERR 0x00000400 |
| #define | NVIC_DBG_INT_INTERR 0x00000200 |
| #define | NVIC_DBG_INT_BUSERR 0x00000100 |
| #define | NVIC_DBG_INT_STATERR 0x00000080 |
| #define | NVIC_DBG_INT_CHKERR 0x00000040 |
| #define | NVIC_DBG_INT_NOCPERR 0x00000020 |
| #define | NVIC_DBG_INT_MMERR 0x00000010 |
| #define | NVIC_DBG_INT_RESET 0x00000008 |
| #define | NVIC_DBG_INT_RSTPENDCLR 0x00000004 |
| #define | NVIC_DBG_INT_RSTPENDING 0x00000002 |
| #define | NVIC_DBG_INT_RSTVCATCH 0x00000001 |
| #define | NVIC_SW_TRIG_INTID_M 0x000000FF |
| #define | NVIC_SW_TRIG_INTID_S 0 |
| #define | NVIC_FPCC_ASPEN 0x80000000 |
| #define | NVIC_FPCC_LSPEN 0x40000000 |
| #define | NVIC_FPCC_MONRDY 0x00000100 |
| #define | NVIC_FPCC_BFRDY 0x00000040 |
| #define | NVIC_FPCC_MMRDY 0x00000020 |
| #define | NVIC_FPCC_HFRDY 0x00000010 |
| #define | NVIC_FPCC_THREAD 0x00000008 |
| #define | NVIC_FPCC_USER 0x00000002 |
| #define | NVIC_FPCC_LSPACT 0x00000001 |
| #define | NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 |
| #define | NVIC_FPCA_ADDRESS_S 3 |
| #define | NVIC_FPDSC_AHP 0x04000000 |
| #define | NVIC_FPDSC_DN 0x02000000 |
| #define | NVIC_FPDSC_FZ 0x01000000 |
| #define | NVIC_FPDSC_RMODE_M 0x00C00000 |
| #define | NVIC_FPDSC_RMODE_RN 0x00000000 |
| #define | NVIC_FPDSC_RMODE_RP 0x00400000 |
| #define | NVIC_FPDSC_RMODE_RM 0x00800000 |
| #define | NVIC_FPDSC_RMODE_RZ 0x00C00000 |
| #define | EEPROM_EEPROMPP_R (*((volatile unsigned long *)0x400AFFC0)) |
| #define | EEPROM_EEPROMPP_SIZE_M 0x0000001F |
| #define | EEPROM_EEPROMPP_SIZE_S 0 |
| #define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000)) |
Definition at line 988 of file cortex-m4-def.h.
| #define ADC0_CC_R (*((volatile unsigned long *)0x40038FC8)) |
Definition at line 1043 of file cortex-m4-def.h.
| #define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40)) |
Definition at line 1033 of file cortex-m4-def.h.
| #define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44)) |
Definition at line 1034 of file cortex-m4-def.h.
| #define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48)) |
Definition at line 1035 of file cortex-m4-def.h.
| #define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C)) |
Definition at line 1036 of file cortex-m4-def.h.
| #define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50)) |
Definition at line 1037 of file cortex-m4-def.h.
| #define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54)) |
Definition at line 1038 of file cortex-m4-def.h.
| #define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58)) |
Definition at line 1039 of file cortex-m4-def.h.
| #define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C)) |
Definition at line 1040 of file cortex-m4-def.h.
| #define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00)) |
Definition at line 1025 of file cortex-m4-def.h.
| #define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04)) |
Definition at line 1026 of file cortex-m4-def.h.
| #define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08)) |
Definition at line 1027 of file cortex-m4-def.h.
| #define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C)) |
Definition at line 1028 of file cortex-m4-def.h.
| #define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10)) |
Definition at line 1029 of file cortex-m4-def.h.
| #define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14)) |
Definition at line 1030 of file cortex-m4-def.h.
| #define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18)) |
Definition at line 1031 of file cortex-m4-def.h.
| #define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C)) |
Definition at line 1032 of file cortex-m4-def.h.
| #define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034)) |
Definition at line 999 of file cortex-m4-def.h.
| #define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00)) |
Definition at line 1024 of file cortex-m4-def.h.
| #define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014)) |
Definition at line 993 of file cortex-m4-def.h.
| #define ADC0_IM_R (*((volatile unsigned long *)0x40038008)) |
Definition at line 990 of file cortex-m4-def.h.
| #define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C)) |
Definition at line 991 of file cortex-m4-def.h.
| #define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010)) |
Definition at line 992 of file cortex-m4-def.h.
| #define ADC0_PC_R (*((volatile unsigned long *)0x40038FC4)) |
Definition at line 1042 of file cortex-m4-def.h.
| #define ADC0_PP_R (*((volatile unsigned long *)0x40038FC0)) |
Definition at line 1041 of file cortex-m4-def.h.
| #define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028)) |
Definition at line 997 of file cortex-m4-def.h.
| #define ADC0_RIS_R (*((volatile unsigned long *)0x40038004)) |
Definition at line 989 of file cortex-m4-def.h.
| #define ADC0_SAC_R (*((volatile unsigned long *)0x40038030)) |
Definition at line 998 of file cortex-m4-def.h.
| #define ADC0_SPC_R (*((volatile unsigned long *)0x40038024)) |
Definition at line 996 of file cortex-m4-def.h.
| #define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044)) |
Definition at line 1001 of file cortex-m4-def.h.
| #define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064)) |
Definition at line 1007 of file cortex-m4-def.h.
| #define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084)) |
Definition at line 1013 of file cortex-m4-def.h.
| #define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) |
Definition at line 1019 of file cortex-m4-def.h.
| #define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054)) |
Definition at line 1005 of file cortex-m4-def.h.
| #define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074)) |
Definition at line 1011 of file cortex-m4-def.h.
| #define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094)) |
Definition at line 1017 of file cortex-m4-def.h.
| #define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4)) |
Definition at line 1023 of file cortex-m4-def.h.
| #define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) |
Definition at line 1002 of file cortex-m4-def.h.
| #define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) |
Definition at line 1008 of file cortex-m4-def.h.
| #define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) |
Definition at line 1014 of file cortex-m4-def.h.
| #define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) |
Definition at line 1020 of file cortex-m4-def.h.
| #define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) |
Definition at line 1003 of file cortex-m4-def.h.
| #define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) |
Definition at line 1009 of file cortex-m4-def.h.
| #define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) |
Definition at line 1015 of file cortex-m4-def.h.
| #define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) |
Definition at line 1021 of file cortex-m4-def.h.
| #define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040)) |
Definition at line 1000 of file cortex-m4-def.h.
| #define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060)) |
Definition at line 1006 of file cortex-m4-def.h.
| #define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080)) |
Definition at line 1012 of file cortex-m4-def.h.
| #define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) |
Definition at line 1018 of file cortex-m4-def.h.
| #define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050)) |
Definition at line 1004 of file cortex-m4-def.h.
| #define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070)) |
Definition at line 1010 of file cortex-m4-def.h.
| #define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090)) |
Definition at line 1016 of file cortex-m4-def.h.
| #define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0)) |
Definition at line 1022 of file cortex-m4-def.h.
| #define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020)) |
Definition at line 995 of file cortex-m4-def.h.
| #define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018)) |
Definition at line 994 of file cortex-m4-def.h.
| #define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000)) |
Definition at line 1050 of file cortex-m4-def.h.
| #define ADC1_CC_R (*((volatile unsigned long *)0x40039FC8)) |
Definition at line 1105 of file cortex-m4-def.h.
| #define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40)) |
Definition at line 1095 of file cortex-m4-def.h.
| #define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44)) |
Definition at line 1096 of file cortex-m4-def.h.
| #define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48)) |
Definition at line 1097 of file cortex-m4-def.h.
| #define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C)) |
Definition at line 1098 of file cortex-m4-def.h.
| #define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50)) |
Definition at line 1099 of file cortex-m4-def.h.
| #define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54)) |
Definition at line 1100 of file cortex-m4-def.h.
| #define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58)) |
Definition at line 1101 of file cortex-m4-def.h.
| #define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C)) |
Definition at line 1102 of file cortex-m4-def.h.
| #define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00)) |
Definition at line 1087 of file cortex-m4-def.h.
| #define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04)) |
Definition at line 1088 of file cortex-m4-def.h.
| #define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08)) |
Definition at line 1089 of file cortex-m4-def.h.
| #define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C)) |
Definition at line 1090 of file cortex-m4-def.h.
| #define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10)) |
Definition at line 1091 of file cortex-m4-def.h.
| #define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14)) |
Definition at line 1092 of file cortex-m4-def.h.
| #define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18)) |
Definition at line 1093 of file cortex-m4-def.h.
| #define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C)) |
Definition at line 1094 of file cortex-m4-def.h.
| #define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034)) |
Definition at line 1061 of file cortex-m4-def.h.
| #define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00)) |
Definition at line 1086 of file cortex-m4-def.h.
| #define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014)) |
Definition at line 1055 of file cortex-m4-def.h.
| #define ADC1_IM_R (*((volatile unsigned long *)0x40039008)) |
Definition at line 1052 of file cortex-m4-def.h.
| #define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C)) |
Definition at line 1053 of file cortex-m4-def.h.
| #define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010)) |
Definition at line 1054 of file cortex-m4-def.h.
| #define ADC1_PC_R (*((volatile unsigned long *)0x40039FC4)) |
Definition at line 1104 of file cortex-m4-def.h.
| #define ADC1_PP_R (*((volatile unsigned long *)0x40039FC0)) |
Definition at line 1103 of file cortex-m4-def.h.
| #define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028)) |
Definition at line 1059 of file cortex-m4-def.h.
| #define ADC1_RIS_R (*((volatile unsigned long *)0x40039004)) |
Definition at line 1051 of file cortex-m4-def.h.
| #define ADC1_SAC_R (*((volatile unsigned long *)0x40039030)) |
Definition at line 1060 of file cortex-m4-def.h.
| #define ADC1_SPC_R (*((volatile unsigned long *)0x40039024)) |
Definition at line 1058 of file cortex-m4-def.h.
| #define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044)) |
Definition at line 1063 of file cortex-m4-def.h.
| #define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064)) |
Definition at line 1069 of file cortex-m4-def.h.
| #define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084)) |
Definition at line 1075 of file cortex-m4-def.h.
| #define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4)) |
Definition at line 1081 of file cortex-m4-def.h.
| #define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054)) |
Definition at line 1067 of file cortex-m4-def.h.
| #define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074)) |
Definition at line 1073 of file cortex-m4-def.h.
| #define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094)) |
Definition at line 1079 of file cortex-m4-def.h.
| #define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4)) |
Definition at line 1085 of file cortex-m4-def.h.
| #define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048)) |
Definition at line 1064 of file cortex-m4-def.h.
| #define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068)) |
Definition at line 1070 of file cortex-m4-def.h.
| #define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088)) |
Definition at line 1076 of file cortex-m4-def.h.
| #define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8)) |
Definition at line 1082 of file cortex-m4-def.h.
| #define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C)) |
Definition at line 1065 of file cortex-m4-def.h.
| #define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C)) |
Definition at line 1071 of file cortex-m4-def.h.
| #define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C)) |
Definition at line 1077 of file cortex-m4-def.h.
| #define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC)) |
Definition at line 1083 of file cortex-m4-def.h.
| #define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040)) |
Definition at line 1062 of file cortex-m4-def.h.
| #define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060)) |
Definition at line 1068 of file cortex-m4-def.h.
| #define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080)) |
Definition at line 1074 of file cortex-m4-def.h.
| #define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0)) |
Definition at line 1080 of file cortex-m4-def.h.
| #define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050)) |
Definition at line 1066 of file cortex-m4-def.h.
| #define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070)) |
Definition at line 1072 of file cortex-m4-def.h.
| #define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090)) |
Definition at line 1078 of file cortex-m4-def.h.
| #define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0)) |
Definition at line 1084 of file cortex-m4-def.h.
| #define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020)) |
Definition at line 1057 of file cortex-m4-def.h.
| #define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018)) |
Definition at line 1056 of file cortex-m4-def.h.
| #define ADC_ACTSS_ASEN0 0x00000001 |
Definition at line 3411 of file cortex-m4-def.h.
| #define ADC_ACTSS_ASEN1 0x00000002 |
Definition at line 3410 of file cortex-m4-def.h.
| #define ADC_ACTSS_ASEN2 0x00000004 |
Definition at line 3409 of file cortex-m4-def.h.
| #define ADC_ACTSS_ASEN3 0x00000008 |
Definition at line 3408 of file cortex-m4-def.h.
| #define ADC_CC_CS_M 0x0000000F |
Definition at line 4237 of file cortex-m4-def.h.
| #define ADC_CC_CS_PIOSC 0x00000001 |
Definition at line 4242 of file cortex-m4-def.h.
| #define ADC_CC_CS_SYSPLL 0x00000000 |
Definition at line 4238 of file cortex-m4-def.h.
| #define ADC_DCCMP0_COMP0_M 0x00000FFF |
Definition at line 4127 of file cortex-m4-def.h.
| #define ADC_DCCMP0_COMP0_S 0 |
Definition at line 4129 of file cortex-m4-def.h.
| #define ADC_DCCMP0_COMP1_M 0x0FFF0000 |
Definition at line 4126 of file cortex-m4-def.h.
| #define ADC_DCCMP0_COMP1_S 16 |
Definition at line 4128 of file cortex-m4-def.h.
| #define ADC_DCCMP1_COMP0_M 0x00000FFF |
Definition at line 4137 of file cortex-m4-def.h.
| #define ADC_DCCMP1_COMP0_S 0 |
Definition at line 4139 of file cortex-m4-def.h.
| #define ADC_DCCMP1_COMP1_M 0x0FFF0000 |
Definition at line 4136 of file cortex-m4-def.h.
| #define ADC_DCCMP1_COMP1_S 16 |
Definition at line 4138 of file cortex-m4-def.h.
| #define ADC_DCCMP2_COMP0_M 0x00000FFF |
Definition at line 4147 of file cortex-m4-def.h.
| #define ADC_DCCMP2_COMP0_S 0 |
Definition at line 4149 of file cortex-m4-def.h.
| #define ADC_DCCMP2_COMP1_M 0x0FFF0000 |
Definition at line 4146 of file cortex-m4-def.h.
| #define ADC_DCCMP2_COMP1_S 16 |
Definition at line 4148 of file cortex-m4-def.h.
| #define ADC_DCCMP3_COMP0_M 0x00000FFF |
Definition at line 4157 of file cortex-m4-def.h.
| #define ADC_DCCMP3_COMP0_S 0 |
Definition at line 4159 of file cortex-m4-def.h.
| #define ADC_DCCMP3_COMP1_M 0x0FFF0000 |
Definition at line 4156 of file cortex-m4-def.h.
| #define ADC_DCCMP3_COMP1_S 16 |
Definition at line 4158 of file cortex-m4-def.h.
| #define ADC_DCCMP4_COMP0_M 0x00000FFF |
Definition at line 4167 of file cortex-m4-def.h.
| #define ADC_DCCMP4_COMP0_S 0 |
Definition at line 4169 of file cortex-m4-def.h.
| #define ADC_DCCMP4_COMP1_M 0x0FFF0000 |
Definition at line 4166 of file cortex-m4-def.h.
| #define ADC_DCCMP4_COMP1_S 16 |
Definition at line 4168 of file cortex-m4-def.h.
| #define ADC_DCCMP5_COMP0_M 0x00000FFF |
Definition at line 4177 of file cortex-m4-def.h.
| #define ADC_DCCMP5_COMP0_S 0 |
Definition at line 4179 of file cortex-m4-def.h.
| #define ADC_DCCMP5_COMP1_M 0x0FFF0000 |
Definition at line 4176 of file cortex-m4-def.h.
| #define ADC_DCCMP5_COMP1_S 16 |
Definition at line 4178 of file cortex-m4-def.h.
| #define ADC_DCCMP6_COMP0_M 0x00000FFF |
Definition at line 4187 of file cortex-m4-def.h.
| #define ADC_DCCMP6_COMP0_S 0 |
Definition at line 4189 of file cortex-m4-def.h.
| #define ADC_DCCMP6_COMP1_M 0x0FFF0000 |
Definition at line 4186 of file cortex-m4-def.h.
| #define ADC_DCCMP6_COMP1_S 16 |
Definition at line 4188 of file cortex-m4-def.h.
| #define ADC_DCCMP7_COMP0_M 0x00000FFF |
Definition at line 4197 of file cortex-m4-def.h.
| #define ADC_DCCMP7_COMP0_S 0 |
Definition at line 4199 of file cortex-m4-def.h.
| #define ADC_DCCMP7_COMP1_M 0x0FFF0000 |
Definition at line 4196 of file cortex-m4-def.h.
| #define ADC_DCCMP7_COMP1_S 16 |
Definition at line 4198 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIC_HIGH 0x0000000C |
Definition at line 4002 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIC_LOW 0x00000000 |
Definition at line 4000 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIC_M 0x0000000C |
Definition at line 3999 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIC_MID 0x00000004 |
Definition at line 4001 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIE 0x00000010 |
Definition at line 3998 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIM_ALWAYS 0x00000000 |
Definition at line 4004 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIM_HALWAYS 0x00000002 |
Definition at line 4006 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIM_HONCE 0x00000003 |
Definition at line 4007 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIM_M 0x00000003 |
Definition at line 4003 of file cortex-m4-def.h.
| #define ADC_DCCTL0_CIM_ONCE 0x00000001 |
Definition at line 4005 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIC_HIGH 0x0000000C |
Definition at line 4018 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIC_LOW 0x00000000 |
Definition at line 4016 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIC_M 0x0000000C |
Definition at line 4015 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIC_MID 0x00000004 |
Definition at line 4017 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIE 0x00000010 |
Definition at line 4014 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIM_ALWAYS 0x00000000 |
Definition at line 4020 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIM_HALWAYS 0x00000002 |
Definition at line 4022 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIM_HONCE 0x00000003 |
Definition at line 4023 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIM_M 0x00000003 |
Definition at line 4019 of file cortex-m4-def.h.
| #define ADC_DCCTL1_CIM_ONCE 0x00000001 |
Definition at line 4021 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIC_HIGH 0x0000000C |
Definition at line 4034 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIC_LOW 0x00000000 |
Definition at line 4032 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIC_M 0x0000000C |
Definition at line 4031 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIC_MID 0x00000004 |
Definition at line 4033 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIE 0x00000010 |
Definition at line 4030 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIM_ALWAYS 0x00000000 |
Definition at line 4036 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIM_HALWAYS 0x00000002 |
Definition at line 4038 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIM_HONCE 0x00000003 |
Definition at line 4039 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIM_M 0x00000003 |
Definition at line 4035 of file cortex-m4-def.h.
| #define ADC_DCCTL2_CIM_ONCE 0x00000001 |
Definition at line 4037 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIC_HIGH 0x0000000C |
Definition at line 4050 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIC_LOW 0x00000000 |
Definition at line 4048 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIC_M 0x0000000C |
Definition at line 4047 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIC_MID 0x00000004 |
Definition at line 4049 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIE 0x00000010 |
Definition at line 4046 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIM_ALWAYS 0x00000000 |
Definition at line 4052 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIM_HALWAYS 0x00000002 |
Definition at line 4054 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIM_HONCE 0x00000003 |
Definition at line 4055 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIM_M 0x00000003 |
Definition at line 4051 of file cortex-m4-def.h.
| #define ADC_DCCTL3_CIM_ONCE 0x00000001 |
Definition at line 4053 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIC_HIGH 0x0000000C |
Definition at line 4066 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIC_LOW 0x00000000 |
Definition at line 4064 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIC_M 0x0000000C |
Definition at line 4063 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIC_MID 0x00000004 |
Definition at line 4065 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIE 0x00000010 |
Definition at line 4062 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIM_ALWAYS 0x00000000 |
Definition at line 4068 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIM_HALWAYS 0x00000002 |
Definition at line 4070 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIM_HONCE 0x00000003 |
Definition at line 4071 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIM_M 0x00000003 |
Definition at line 4067 of file cortex-m4-def.h.
| #define ADC_DCCTL4_CIM_ONCE 0x00000001 |
Definition at line 4069 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIC_HIGH 0x0000000C |
Definition at line 4082 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIC_LOW 0x00000000 |
Definition at line 4080 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIC_M 0x0000000C |
Definition at line 4079 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIC_MID 0x00000004 |
Definition at line 4081 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIE 0x00000010 |
Definition at line 4078 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIM_ALWAYS 0x00000000 |
Definition at line 4084 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIM_HALWAYS 0x00000002 |
Definition at line 4086 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIM_HONCE 0x00000003 |
Definition at line 4087 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIM_M 0x00000003 |
Definition at line 4083 of file cortex-m4-def.h.
| #define ADC_DCCTL5_CIM_ONCE 0x00000001 |
Definition at line 4085 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIC_HIGH 0x0000000C |
Definition at line 4098 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIC_LOW 0x00000000 |
Definition at line 4096 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIC_M 0x0000000C |
Definition at line 4095 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIC_MID 0x00000004 |
Definition at line 4097 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIE 0x00000010 |
Definition at line 4094 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIM_ALWAYS 0x00000000 |
Definition at line 4100 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIM_HALWAYS 0x00000002 |
Definition at line 4102 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIM_HONCE 0x00000003 |
Definition at line 4103 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIM_M 0x00000003 |
Definition at line 4099 of file cortex-m4-def.h.
| #define ADC_DCCTL6_CIM_ONCE 0x00000001 |
Definition at line 4101 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIC_HIGH 0x0000000C |
Definition at line 4114 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIC_LOW 0x00000000 |
Definition at line 4112 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIC_M 0x0000000C |
Definition at line 4111 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIC_MID 0x00000004 |
Definition at line 4113 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIE 0x00000010 |
Definition at line 4110 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIM_ALWAYS 0x00000000 |
Definition at line 4116 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIM_HALWAYS 0x00000002 |
Definition at line 4118 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIM_HONCE 0x00000003 |
Definition at line 4119 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIM_M 0x00000003 |
Definition at line 4115 of file cortex-m4-def.h.
| #define ADC_DCCTL7_CIM_ONCE 0x00000001 |
Definition at line 4117 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT0 0x00000001 |
Definition at line 3609 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT1 0x00000002 |
Definition at line 3607 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT2 0x00000004 |
Definition at line 3605 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT3 0x00000008 |
Definition at line 3603 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT4 0x00000010 |
Definition at line 3601 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT5 0x00000020 |
Definition at line 3599 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT6 0x00000040 |
Definition at line 3597 of file cortex-m4-def.h.
| #define ADC_DCISC_DCINT7 0x00000080 |
Definition at line 3595 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT0 0x00000001 |
Definition at line 3991 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT1 0x00000002 |
Definition at line 3990 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT2 0x00000004 |
Definition at line 3989 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT3 0x00000008 |
Definition at line 3988 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT4 0x00000010 |
Definition at line 3987 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT5 0x00000020 |
Definition at line 3986 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT6 0x00000040 |
Definition at line 3985 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCINT7 0x00000080 |
Definition at line 3984 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG0 0x00010000 |
Definition at line 3983 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG1 0x00020000 |
Definition at line 3982 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG2 0x00040000 |
Definition at line 3981 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG3 0x00080000 |
Definition at line 3980 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG4 0x00100000 |
Definition at line 3979 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG5 0x00200000 |
Definition at line 3978 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG6 0x00400000 |
Definition at line 3977 of file cortex-m4-def.h.
| #define ADC_DCRIC_DCTRIG7 0x00800000 |
Definition at line 3976 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_ALWAYS 0x0000000F |
Definition at line 3503 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_COMP0 0x00000001 |
Definition at line 3499 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_COMP1 0x00000002 |
Definition at line 3500 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_EXTERNAL 0x00000004 |
Definition at line 3501 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_M 0x0000000F |
Definition at line 3497 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_PROCESSOR 0x00000000 |
Definition at line 3498 of file cortex-m4-def.h.
| #define ADC_EMUX_EM0_TIMER 0x00000005 |
Definition at line 3502 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_ALWAYS 0x000000F0 |
Definition at line 3496 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_COMP0 0x00000010 |
Definition at line 3492 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_COMP1 0x00000020 |
Definition at line 3493 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_EXTERNAL 0x00000040 |
Definition at line 3494 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_M 0x000000F0 |
Definition at line 3490 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_PROCESSOR 0x00000000 |
Definition at line 3491 of file cortex-m4-def.h.
| #define ADC_EMUX_EM1_TIMER 0x00000050 |
Definition at line 3495 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_ALWAYS 0x00000F00 |
Definition at line 3489 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_COMP0 0x00000100 |
Definition at line 3485 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_COMP1 0x00000200 |
Definition at line 3486 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_EXTERNAL 0x00000400 |
Definition at line 3487 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_M 0x00000F00 |
Definition at line 3483 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_PROCESSOR 0x00000000 |
Definition at line 3484 of file cortex-m4-def.h.
| #define ADC_EMUX_EM2_TIMER 0x00000500 |
Definition at line 3488 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_ALWAYS 0x0000F000 |
Definition at line 3482 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_COMP0 0x00001000 |
Definition at line 3478 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_COMP1 0x00002000 |
Definition at line 3479 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_EXTERNAL 0x00004000 |
Definition at line 3480 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_M 0x0000F000 |
Definition at line 3476 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_PROCESSOR 0x00000000 |
Definition at line 3477 of file cortex-m4-def.h.
| #define ADC_EMUX_EM3_TIMER 0x00005000 |
Definition at line 3481 of file cortex-m4-def.h.
| #define ADC_IM_DCONSS0 0x00010000 |
Definition at line 3436 of file cortex-m4-def.h.
| #define ADC_IM_DCONSS1 0x00020000 |
Definition at line 3434 of file cortex-m4-def.h.
| #define ADC_IM_DCONSS2 0x00040000 |
Definition at line 3432 of file cortex-m4-def.h.
| #define ADC_IM_DCONSS3 0x00080000 |
Definition at line 3430 of file cortex-m4-def.h.
| #define ADC_IM_MASK0 0x00000001 |
Definition at line 3441 of file cortex-m4-def.h.
| #define ADC_IM_MASK1 0x00000002 |
Definition at line 3440 of file cortex-m4-def.h.
| #define ADC_IM_MASK2 0x00000004 |
Definition at line 3439 of file cortex-m4-def.h.
| #define ADC_IM_MASK3 0x00000008 |
Definition at line 3438 of file cortex-m4-def.h.
| #define ADC_ISC_DCINSS0 0x00010000 |
Definition at line 3454 of file cortex-m4-def.h.
| #define ADC_ISC_DCINSS1 0x00020000 |
Definition at line 3452 of file cortex-m4-def.h.
| #define ADC_ISC_DCINSS2 0x00040000 |
Definition at line 3450 of file cortex-m4-def.h.
| #define ADC_ISC_DCINSS3 0x00080000 |
Definition at line 3448 of file cortex-m4-def.h.
| #define ADC_ISC_IN0 0x00000001 |
Definition at line 3459 of file cortex-m4-def.h.
| #define ADC_ISC_IN1 0x00000002 |
Definition at line 3458 of file cortex-m4-def.h.
| #define ADC_ISC_IN2 0x00000004 |
Definition at line 3457 of file cortex-m4-def.h.
| #define ADC_ISC_IN3 0x00000008 |
Definition at line 3456 of file cortex-m4-def.h.
| #define ADC_OSTAT_OV0 0x00000001 |
Definition at line 3469 of file cortex-m4-def.h.
| #define ADC_OSTAT_OV1 0x00000002 |
Definition at line 3468 of file cortex-m4-def.h.
| #define ADC_OSTAT_OV2 0x00000004 |
Definition at line 3467 of file cortex-m4-def.h.
| #define ADC_OSTAT_OV3 0x00000008 |
Definition at line 3466 of file cortex-m4-def.h.
| #define ADC_PC_SR_125K 0x00000001 |
Definition at line 4227 of file cortex-m4-def.h.
| #define ADC_PC_SR_1M 0x00000007 |
Definition at line 4230 of file cortex-m4-def.h.
| #define ADC_PC_SR_250K 0x00000003 |
Definition at line 4228 of file cortex-m4-def.h.
| #define ADC_PC_SR_500K 0x00000005 |
Definition at line 4229 of file cortex-m4-def.h.
| #define ADC_PC_SR_M 0x0000000F |
Definition at line 4226 of file cortex-m4-def.h.
| #define ADC_PP_CH_M 0x000003F0 |
Definition at line 4211 of file cortex-m4-def.h.
| #define ADC_PP_CH_S 4 |
Definition at line 4219 of file cortex-m4-def.h.
| #define ADC_PP_DC_M 0x0000FC00 |
Definition at line 4210 of file cortex-m4-def.h.
| #define ADC_PP_DC_S 10 |
Definition at line 4218 of file cortex-m4-def.h.
| #define ADC_PP_MSR_125K 0x00000001 |
Definition at line 4213 of file cortex-m4-def.h.
| #define ADC_PP_MSR_1M 0x00000007 |
Definition at line 4216 of file cortex-m4-def.h.
| #define ADC_PP_MSR_250K 0x00000003 |
Definition at line 4214 of file cortex-m4-def.h.
| #define ADC_PP_MSR_500K 0x00000005 |
Definition at line 4215 of file cortex-m4-def.h.
| #define ADC_PP_MSR_M 0x0000000F |
Definition at line 4212 of file cortex-m4-def.h.
| #define ADC_PP_RSL_M 0x007C0000 |
Definition at line 4207 of file cortex-m4-def.h.
| #define ADC_PP_RSL_S 18 |
Definition at line 4217 of file cortex-m4-def.h.
| #define ADC_PP_TS 0x00800000 |
Definition at line 4206 of file cortex-m4-def.h.
| #define ADC_PP_TYPE_M 0x00030000 |
Definition at line 4208 of file cortex-m4-def.h.
| #define ADC_PP_TYPE_SAR 0x00000000 |
Definition at line 4209 of file cortex-m4-def.h.
| #define ADC_PSSI_GSYNC 0x80000000 |
Definition at line 3569 of file cortex-m4-def.h.
| #define ADC_PSSI_SS0 0x00000001 |
Definition at line 3574 of file cortex-m4-def.h.
| #define ADC_PSSI_SS1 0x00000002 |
Definition at line 3573 of file cortex-m4-def.h.
| #define ADC_PSSI_SS2 0x00000004 |
Definition at line 3572 of file cortex-m4-def.h.
| #define ADC_PSSI_SS3 0x00000008 |
Definition at line 3571 of file cortex-m4-def.h.
| #define ADC_PSSI_SYNCWAIT 0x08000000 |
Definition at line 3570 of file cortex-m4-def.h.
| #define ADC_RIS_INR0 0x00000001 |
Definition at line 3423 of file cortex-m4-def.h.
| #define ADC_RIS_INR1 0x00000002 |
Definition at line 3422 of file cortex-m4-def.h.
| #define ADC_RIS_INR2 0x00000004 |
Definition at line 3421 of file cortex-m4-def.h.
| #define ADC_RIS_INR3 0x00000008 |
Definition at line 3420 of file cortex-m4-def.h.
| #define ADC_RIS_INRDC 0x00010000 |
Definition at line 3418 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_16X 0x00000004 |
Definition at line 3586 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_2X 0x00000001 |
Definition at line 3583 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_32X 0x00000005 |
Definition at line 3587 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_4X 0x00000002 |
Definition at line 3584 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_64X 0x00000006 |
Definition at line 3588 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_8X 0x00000003 |
Definition at line 3585 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_M 0x00000007 |
Definition at line 3581 of file cortex-m4-def.h.
| #define ADC_SAC_AVG_OFF 0x00000000 |
Definition at line 3582 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_0 0x00000000 |
Definition at line 3547 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_112_5 0x00000005 |
Definition at line 3552 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_135 0x00000006 |
Definition at line 3553 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_157_5 0x00000007 |
Definition at line 3554 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_180 0x00000008 |
Definition at line 3555 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_202_5 0x00000009 |
Definition at line 3556 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_225 0x0000000A |
Definition at line 3557 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_22_5 0x00000001 |
Definition at line 3548 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_247_5 0x0000000B |
Definition at line 3558 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_270 0x0000000C |
Definition at line 3559 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_292_5 0x0000000D |
Definition at line 3560 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_315 0x0000000E |
Definition at line 3561 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_337_5 0x0000000F |
Definition at line 3562 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_45 0x00000002 |
Definition at line 3549 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_67_5 0x00000003 |
Definition at line 3550 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_90 0x00000004 |
Definition at line 3551 of file cortex-m4-def.h.
| #define ADC_SPC_PHASE_M 0x0000000F |
Definition at line 3546 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D0 0x00000001 |
Definition at line 3670 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D1 0x00000010 |
Definition at line 3666 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D2 0x00000100 |
Definition at line 3662 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D3 0x00001000 |
Definition at line 3658 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D4 0x00010000 |
Definition at line 3654 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D5 0x00100000 |
Definition at line 3650 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D6 0x01000000 |
Definition at line 3646 of file cortex-m4-def.h.
| #define ADC_SSCTL0_D7 0x10000000 |
Definition at line 3642 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END0 0x00000002 |
Definition at line 3669 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END1 0x00000020 |
Definition at line 3665 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END2 0x00000200 |
Definition at line 3661 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END3 0x00002000 |
Definition at line 3657 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END4 0x00020000 |
Definition at line 3653 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END5 0x00200000 |
Definition at line 3649 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END6 0x02000000 |
Definition at line 3645 of file cortex-m4-def.h.
| #define ADC_SSCTL0_END7 0x20000000 |
Definition at line 3641 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE0 0x00000004 |
Definition at line 3668 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE1 0x00000040 |
Definition at line 3664 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE2 0x00000400 |
Definition at line 3660 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE3 0x00004000 |
Definition at line 3656 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE4 0x00040000 |
Definition at line 3652 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE5 0x00400000 |
Definition at line 3648 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE6 0x04000000 |
Definition at line 3644 of file cortex-m4-def.h.
| #define ADC_SSCTL0_IE7 0x40000000 |
Definition at line 3640 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS0 0x00000008 |
Definition at line 3667 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS1 0x00000080 |
Definition at line 3663 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS2 0x00000800 |
Definition at line 3659 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS3 0x00008000 |
Definition at line 3655 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS4 0x00080000 |
Definition at line 3651 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS5 0x00800000 |
Definition at line 3647 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS6 0x08000000 |
Definition at line 3643 of file cortex-m4-def.h.
| #define ADC_SSCTL0_TS7 0x80000000 |
Definition at line 3639 of file cortex-m4-def.h.
| #define ADC_SSCTL1_D0 0x00000001 |
Definition at line 3777 of file cortex-m4-def.h.
| #define ADC_SSCTL1_D1 0x00000010 |
Definition at line 3773 of file cortex-m4-def.h.
| #define ADC_SSCTL1_D2 0x00000100 |
Definition at line 3769 of file cortex-m4-def.h.
| #define ADC_SSCTL1_D3 0x00001000 |
Definition at line 3765 of file cortex-m4-def.h.
| #define ADC_SSCTL1_END0 0x00000002 |
Definition at line 3776 of file cortex-m4-def.h.
| #define ADC_SSCTL1_END1 0x00000020 |
Definition at line 3772 of file cortex-m4-def.h.
| #define ADC_SSCTL1_END2 0x00000200 |
Definition at line 3768 of file cortex-m4-def.h.
| #define ADC_SSCTL1_END3 0x00002000 |
Definition at line 3764 of file cortex-m4-def.h.
| #define ADC_SSCTL1_IE0 0x00000004 |
Definition at line 3775 of file cortex-m4-def.h.
| #define ADC_SSCTL1_IE1 0x00000040 |
Definition at line 3771 of file cortex-m4-def.h.
| #define ADC_SSCTL1_IE2 0x00000400 |
Definition at line 3767 of file cortex-m4-def.h.
| #define ADC_SSCTL1_IE3 0x00004000 |
Definition at line 3763 of file cortex-m4-def.h.
| #define ADC_SSCTL1_TS0 0x00000008 |
Definition at line 3774 of file cortex-m4-def.h.
| #define ADC_SSCTL1_TS1 0x00000080 |
Definition at line 3770 of file cortex-m4-def.h.
| #define ADC_SSCTL1_TS2 0x00000800 |
Definition at line 3766 of file cortex-m4-def.h.
| #define ADC_SSCTL1_TS3 0x00008000 |
Definition at line 3762 of file cortex-m4-def.h.
| #define ADC_SSCTL2_D0 0x00000001 |
Definition at line 3864 of file cortex-m4-def.h.
| #define ADC_SSCTL2_D1 0x00000010 |
Definition at line 3860 of file cortex-m4-def.h.
| #define ADC_SSCTL2_D2 0x00000100 |
Definition at line 3856 of file cortex-m4-def.h.
| #define ADC_SSCTL2_D3 0x00001000 |
Definition at line 3852 of file cortex-m4-def.h.
| #define ADC_SSCTL2_END0 0x00000002 |
Definition at line 3863 of file cortex-m4-def.h.
| #define ADC_SSCTL2_END1 0x00000020 |
Definition at line 3859 of file cortex-m4-def.h.
| #define ADC_SSCTL2_END2 0x00000200 |
Definition at line 3855 of file cortex-m4-def.h.
| #define ADC_SSCTL2_END3 0x00002000 |
Definition at line 3851 of file cortex-m4-def.h.
| #define ADC_SSCTL2_IE0 0x00000004 |
Definition at line 3862 of file cortex-m4-def.h.
| #define ADC_SSCTL2_IE1 0x00000040 |
Definition at line 3858 of file cortex-m4-def.h.
| #define ADC_SSCTL2_IE2 0x00000400 |
Definition at line 3854 of file cortex-m4-def.h.
| #define ADC_SSCTL2_IE3 0x00004000 |
Definition at line 3850 of file cortex-m4-def.h.
| #define ADC_SSCTL2_TS0 0x00000008 |
Definition at line 3861 of file cortex-m4-def.h.
| #define ADC_SSCTL2_TS1 0x00000080 |
Definition at line 3857 of file cortex-m4-def.h.
| #define ADC_SSCTL2_TS2 0x00000800 |
Definition at line 3853 of file cortex-m4-def.h.
| #define ADC_SSCTL2_TS3 0x00008000 |
Definition at line 3849 of file cortex-m4-def.h.
| #define ADC_SSCTL3_D0 0x00000001 |
Definition at line 3933 of file cortex-m4-def.h.
| #define ADC_SSCTL3_END0 0x00000002 |
Definition at line 3932 of file cortex-m4-def.h.
| #define ADC_SSCTL3_IE0 0x00000004 |
Definition at line 3931 of file cortex-m4-def.h.
| #define ADC_SSCTL3_TS0 0x00000008 |
Definition at line 3930 of file cortex-m4-def.h.
| #define ADC_SSDC0_S0DCSEL_M 0x0000000F |
Definition at line 3733 of file cortex-m4-def.h.
| #define ADC_SSDC0_S0DCSEL_S 0 |
Definition at line 3741 of file cortex-m4-def.h.
| #define ADC_SSDC0_S1DCSEL_M 0x000000F0 |
Definition at line 3731 of file cortex-m4-def.h.
| #define ADC_SSDC0_S1DCSEL_S 4 |
Definition at line 3740 of file cortex-m4-def.h.
| #define ADC_SSDC0_S2DCSEL_M 0x00000F00 |
Definition at line 3729 of file cortex-m4-def.h.
| #define ADC_SSDC0_S2DCSEL_S 8 |
Definition at line 3739 of file cortex-m4-def.h.
| #define ADC_SSDC0_S3DCSEL_M 0x0000F000 |
Definition at line 3727 of file cortex-m4-def.h.
| #define ADC_SSDC0_S3DCSEL_S 12 |
Definition at line 3738 of file cortex-m4-def.h.
| #define ADC_SSDC0_S4DCSEL_M 0x000F0000 |
Definition at line 3725 of file cortex-m4-def.h.
| #define ADC_SSDC0_S4DCSEL_S 16 |
Definition at line 3737 of file cortex-m4-def.h.
| #define ADC_SSDC0_S5DCSEL_M 0x00F00000 |
Definition at line 3723 of file cortex-m4-def.h.
| #define ADC_SSDC0_S5DCSEL_S 20 |
Definition at line 3736 of file cortex-m4-def.h.
| #define ADC_SSDC0_S6DCSEL_M 0x0F000000 |
Definition at line 3721 of file cortex-m4-def.h.
| #define ADC_SSDC0_S6DCSEL_S 24 |
Definition at line 3735 of file cortex-m4-def.h.
| #define ADC_SSDC0_S7DCSEL_M 0xF0000000 |
Definition at line 3719 of file cortex-m4-def.h.
| #define ADC_SSDC1_S0DCSEL_M 0x0000000F |
Definition at line 3824 of file cortex-m4-def.h.
| #define ADC_SSDC1_S0DCSEL_S 0 |
Definition at line 3828 of file cortex-m4-def.h.
| #define ADC_SSDC1_S1DCSEL_M 0x000000F0 |
Definition at line 3822 of file cortex-m4-def.h.
| #define ADC_SSDC1_S1DCSEL_S 4 |
Definition at line 3827 of file cortex-m4-def.h.
| #define ADC_SSDC1_S2DCSEL_M 0x00000F00 |
Definition at line 3820 of file cortex-m4-def.h.
| #define ADC_SSDC1_S2DCSEL_S 8 |
Definition at line 3826 of file cortex-m4-def.h.
| #define ADC_SSDC1_S3DCSEL_M 0x0000F000 |
Definition at line 3818 of file cortex-m4-def.h.
| #define ADC_SSDC2_S0DCSEL_M 0x0000000F |
Definition at line 3911 of file cortex-m4-def.h.
| #define ADC_SSDC2_S0DCSEL_S 0 |
Definition at line 3915 of file cortex-m4-def.h.
| #define ADC_SSDC2_S1DCSEL_M 0x000000F0 |
Definition at line 3909 of file cortex-m4-def.h.
| #define ADC_SSDC2_S1DCSEL_S 4 |
Definition at line 3914 of file cortex-m4-def.h.
| #define ADC_SSDC2_S2DCSEL_M 0x00000F00 |
Definition at line 3907 of file cortex-m4-def.h.
| #define ADC_SSDC2_S2DCSEL_S 8 |
Definition at line 3913 of file cortex-m4-def.h.
| #define ADC_SSDC2_S3DCSEL_M 0x0000F000 |
Definition at line 3905 of file cortex-m4-def.h.
| #define ADC_SSDC3_S0DCSEL_M 0x0000000F |
Definition at line 3968 of file cortex-m4-def.h.
| #define ADC_SSFIFO0_DATA_M 0x00000FFF |
Definition at line 3677 of file cortex-m4-def.h.
| #define ADC_SSFIFO0_DATA_S 0 |
Definition at line 3678 of file cortex-m4-def.h.
| #define ADC_SSFIFO1_DATA_M 0x00000FFF |
Definition at line 3784 of file cortex-m4-def.h.
| #define ADC_SSFIFO1_DATA_S 0 |
Definition at line 3785 of file cortex-m4-def.h.
| #define ADC_SSFIFO2_DATA_M 0x00000FFF |
Definition at line 3871 of file cortex-m4-def.h.
| #define ADC_SSFIFO2_DATA_S 0 |
Definition at line 3872 of file cortex-m4-def.h.
| #define ADC_SSFIFO3_DATA_M 0x00000FFF |
Definition at line 3940 of file cortex-m4-def.h.
| #define ADC_SSFIFO3_DATA_S 0 |
Definition at line 3941 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_EMPTY 0x00000100 |
Definition at line 3686 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_FULL 0x00001000 |
Definition at line 3685 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_HPTR_M 0x000000F0 |
Definition at line 3687 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_HPTR_S 4 |
Definition at line 3689 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_TPTR_M 0x0000000F |
Definition at line 3688 of file cortex-m4-def.h.
| #define ADC_SSFSTAT0_TPTR_S 0 |
Definition at line 3690 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_EMPTY 0x00000100 |
Definition at line 3793 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_FULL 0x00001000 |
Definition at line 3792 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_HPTR_M 0x000000F0 |
Definition at line 3794 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_HPTR_S 4 |
Definition at line 3796 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_TPTR_M 0x0000000F |
Definition at line 3795 of file cortex-m4-def.h.
| #define ADC_SSFSTAT1_TPTR_S 0 |
Definition at line 3797 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_EMPTY 0x00000100 |
Definition at line 3880 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_FULL 0x00001000 |
Definition at line 3879 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_HPTR_M 0x000000F0 |
Definition at line 3881 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_HPTR_S 4 |
Definition at line 3883 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_TPTR_M 0x0000000F |
Definition at line 3882 of file cortex-m4-def.h.
| #define ADC_SSFSTAT2_TPTR_S 0 |
Definition at line 3884 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_EMPTY 0x00000100 |
Definition at line 3949 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_FULL 0x00001000 |
Definition at line 3948 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_HPTR_M 0x000000F0 |
Definition at line 3950 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_HPTR_S 4 |
Definition at line 3952 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_TPTR_M 0x0000000F |
Definition at line 3951 of file cortex-m4-def.h.
| #define ADC_SSFSTAT3_TPTR_S 0 |
Definition at line 3953 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX0_M 0x0000000F |
Definition at line 3624 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX0_S 0 |
Definition at line 3632 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX1_M 0x000000F0 |
Definition at line 3623 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX1_S 4 |
Definition at line 3631 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX2_M 0x00000F00 |
Definition at line 3622 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX2_S 8 |
Definition at line 3630 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX3_M 0x0000F000 |
Definition at line 3621 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX3_S 12 |
Definition at line 3629 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX4_M 0x000F0000 |
Definition at line 3620 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX4_S 16 |
Definition at line 3628 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX5_M 0x00F00000 |
Definition at line 3619 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX5_S 20 |
Definition at line 3627 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX6_M 0x0F000000 |
Definition at line 3618 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX6_S 24 |
Definition at line 3626 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX7_M 0xF0000000 |
Definition at line 3617 of file cortex-m4-def.h.
| #define ADC_SSMUX0_MUX7_S 28 |
Definition at line 3625 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX0_M 0x0000000F |
Definition at line 3751 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX0_S 0 |
Definition at line 3755 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX1_M 0x000000F0 |
Definition at line 3750 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX1_S 4 |
Definition at line 3754 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX2_M 0x00000F00 |
Definition at line 3749 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX2_S 8 |
Definition at line 3753 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX3_M 0x0000F000 |
Definition at line 3748 of file cortex-m4-def.h.
| #define ADC_SSMUX1_MUX3_S 12 |
Definition at line 3752 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX0_M 0x0000000F |
Definition at line 3838 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX0_S 0 |
Definition at line 3842 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX1_M 0x000000F0 |
Definition at line 3837 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX1_S 4 |
Definition at line 3841 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX2_M 0x00000F00 |
Definition at line 3836 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX2_S 8 |
Definition at line 3840 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX3_M 0x0000F000 |
Definition at line 3835 of file cortex-m4-def.h.
| #define ADC_SSMUX2_MUX3_S 12 |
Definition at line 3839 of file cortex-m4-def.h.
| #define ADC_SSMUX3_MUX0_M 0x0000000F |
Definition at line 3922 of file cortex-m4-def.h.
| #define ADC_SSMUX3_MUX0_S 0 |
Definition at line 3923 of file cortex-m4-def.h.
| #define ADC_SSOP0_S0DCOP 0x00000001 |
Definition at line 3711 of file cortex-m4-def.h.
| #define ADC_SSOP0_S1DCOP 0x00000010 |
Definition at line 3709 of file cortex-m4-def.h.
| #define ADC_SSOP0_S2DCOP 0x00000100 |
Definition at line 3707 of file cortex-m4-def.h.
| #define ADC_SSOP0_S3DCOP 0x00001000 |
Definition at line 3705 of file cortex-m4-def.h.
| #define ADC_SSOP0_S4DCOP 0x00010000 |
Definition at line 3703 of file cortex-m4-def.h.
| #define ADC_SSOP0_S5DCOP 0x00100000 |
Definition at line 3701 of file cortex-m4-def.h.
| #define ADC_SSOP0_S6DCOP 0x01000000 |
Definition at line 3699 of file cortex-m4-def.h.
| #define ADC_SSOP0_S7DCOP 0x10000000 |
Definition at line 3697 of file cortex-m4-def.h.
| #define ADC_SSOP1_S0DCOP 0x00000001 |
Definition at line 3810 of file cortex-m4-def.h.
| #define ADC_SSOP1_S1DCOP 0x00000010 |
Definition at line 3808 of file cortex-m4-def.h.
| #define ADC_SSOP1_S2DCOP 0x00000100 |
Definition at line 3806 of file cortex-m4-def.h.
| #define ADC_SSOP1_S3DCOP 0x00001000 |
Definition at line 3804 of file cortex-m4-def.h.
| #define ADC_SSOP2_S0DCOP 0x00000001 |
Definition at line 3897 of file cortex-m4-def.h.
| #define ADC_SSOP2_S1DCOP 0x00000010 |
Definition at line 3895 of file cortex-m4-def.h.
| #define ADC_SSOP2_S2DCOP 0x00000100 |
Definition at line 3893 of file cortex-m4-def.h.
| #define ADC_SSOP2_S3DCOP 0x00001000 |
Definition at line 3891 of file cortex-m4-def.h.
| #define ADC_SSOP3_S0DCOP 0x00000001 |
Definition at line 3960 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS0_1ST 0x00000000 |
Definition at line 3536 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS0_2ND 0x00000001 |
Definition at line 3537 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS0_3RD 0x00000002 |
Definition at line 3538 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS0_4TH 0x00000003 |
Definition at line 3539 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS0_M 0x00000003 |
Definition at line 3535 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS1_1ST 0x00000000 |
Definition at line 3531 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS1_2ND 0x00000010 |
Definition at line 3532 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS1_3RD 0x00000020 |
Definition at line 3533 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS1_4TH 0x00000030 |
Definition at line 3534 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS1_M 0x00000030 |
Definition at line 3530 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS2_1ST 0x00000000 |
Definition at line 3526 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS2_2ND 0x00000100 |
Definition at line 3527 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS2_3RD 0x00000200 |
Definition at line 3528 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS2_4TH 0x00000300 |
Definition at line 3529 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS2_M 0x00000300 |
Definition at line 3525 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS3_1ST 0x00000000 |
Definition at line 3521 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS3_2ND 0x00001000 |
Definition at line 3522 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS3_3RD 0x00002000 |
Definition at line 3523 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS3_4TH 0x00003000 |
Definition at line 3524 of file cortex-m4-def.h.
| #define ADC_SSPRI_SS3_M 0x00003000 |
Definition at line 3520 of file cortex-m4-def.h.
| #define ADC_USTAT_UV0 0x00000001 |
Definition at line 3513 of file cortex-m4-def.h.
| #define ADC_USTAT_UV1 0x00000002 |
Definition at line 3512 of file cortex-m4-def.h.
| #define ADC_USTAT_UV2 0x00000004 |
Definition at line 3511 of file cortex-m4-def.h.
| #define ADC_USTAT_UV3 0x00000008 |
Definition at line 3510 of file cortex-m4-def.h.
| #define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C)) |
Definition at line 1130 of file cortex-m4-def.h.
| #define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018)) |
Definition at line 1133 of file cortex-m4-def.h.
| #define CAN0_CTL_R (*((volatile unsigned long *)0x40040000)) |
Definition at line 1127 of file cortex-m4-def.h.
| #define CAN0_ERR_R (*((volatile unsigned long *)0x40040008)) |
Definition at line 1129 of file cortex-m4-def.h.
| #define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030)) |
Definition at line 1138 of file cortex-m4-def.h.
| #define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034)) |
Definition at line 1139 of file cortex-m4-def.h.
| #define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024)) |
Definition at line 1135 of file cortex-m4-def.h.
| #define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020)) |
Definition at line 1134 of file cortex-m4-def.h.
| #define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C)) |
Definition at line 1141 of file cortex-m4-def.h.
| #define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040)) |
Definition at line 1142 of file cortex-m4-def.h.
| #define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044)) |
Definition at line 1143 of file cortex-m4-def.h.
| #define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048)) |
Definition at line 1144 of file cortex-m4-def.h.
| #define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038)) |
Definition at line 1140 of file cortex-m4-def.h.
| #define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028)) |
Definition at line 1136 of file cortex-m4-def.h.
| #define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C)) |
Definition at line 1137 of file cortex-m4-def.h.
| #define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090)) |
Definition at line 1149 of file cortex-m4-def.h.
| #define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094)) |
Definition at line 1150 of file cortex-m4-def.h.
| #define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084)) |
Definition at line 1146 of file cortex-m4-def.h.
| #define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080)) |
Definition at line 1145 of file cortex-m4-def.h.
| #define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C)) |
Definition at line 1152 of file cortex-m4-def.h.
| #define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0)) |
Definition at line 1153 of file cortex-m4-def.h.
| #define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4)) |
Definition at line 1154 of file cortex-m4-def.h.
| #define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8)) |
Definition at line 1155 of file cortex-m4-def.h.
| #define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098)) |
Definition at line 1151 of file cortex-m4-def.h.
| #define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088)) |
Definition at line 1147 of file cortex-m4-def.h.
| #define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C)) |
Definition at line 1148 of file cortex-m4-def.h.
| #define CAN0_INT_R (*((volatile unsigned long *)0x40040010)) |
Definition at line 1131 of file cortex-m4-def.h.
| #define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140)) |
Definition at line 1160 of file cortex-m4-def.h.
| #define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160)) |
Definition at line 1162 of file cortex-m4-def.h.
| #define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144)) |
Definition at line 1161 of file cortex-m4-def.h.
| #define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164)) |
Definition at line 1163 of file cortex-m4-def.h.
| #define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120)) |
Definition at line 1158 of file cortex-m4-def.h.
| #define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124)) |
Definition at line 1159 of file cortex-m4-def.h.
| #define CAN0_STS_R (*((volatile unsigned long *)0x40040004)) |
Definition at line 1128 of file cortex-m4-def.h.
| #define CAN0_TST_R (*((volatile unsigned long *)0x40040014)) |
Definition at line 1132 of file cortex-m4-def.h.
| #define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100)) |
Definition at line 1156 of file cortex-m4-def.h.
| #define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104)) |
Definition at line 1157 of file cortex-m4-def.h.
| #define CAN_BIT_BRP_M 0x0000003F |
Definition at line 4409 of file cortex-m4-def.h.
| #define CAN_BIT_BRP_S 0 |
Definition at line 4413 of file cortex-m4-def.h.
| #define CAN_BIT_SJW_M 0x000000C0 |
Definition at line 4408 of file cortex-m4-def.h.
| #define CAN_BIT_SJW_S 6 |
Definition at line 4412 of file cortex-m4-def.h.
| #define CAN_BIT_TSEG1_M 0x00000F00 |
Definition at line 4407 of file cortex-m4-def.h.
| #define CAN_BIT_TSEG1_S 8 |
Definition at line 4411 of file cortex-m4-def.h.
| #define CAN_BIT_TSEG2_M 0x00007000 |
Definition at line 4406 of file cortex-m4-def.h.
| #define CAN_BIT_TSEG2_S 12 |
Definition at line 4410 of file cortex-m4-def.h.
| #define CAN_BRPE_BRPE_M 0x0000000F |
Definition at line 4444 of file cortex-m4-def.h.
| #define CAN_BRPE_BRPE_S 0 |
Definition at line 4445 of file cortex-m4-def.h.
| #define CAN_CTL_CCE 0x00000040 |
Definition at line 4362 of file cortex-m4-def.h.
| #define CAN_CTL_DAR 0x00000020 |
Definition at line 4363 of file cortex-m4-def.h.
| #define CAN_CTL_EIE 0x00000008 |
Definition at line 4364 of file cortex-m4-def.h.
| #define CAN_CTL_IE 0x00000002 |
Definition at line 4366 of file cortex-m4-def.h.
| #define CAN_CTL_INIT 0x00000001 |
Definition at line 4367 of file cortex-m4-def.h.
| #define CAN_CTL_SIE 0x00000004 |
Definition at line 4365 of file cortex-m4-def.h.
| #define CAN_CTL_TEST 0x00000080 |
Definition at line 4361 of file cortex-m4-def.h.
| #define CAN_ERR_REC_M 0x00007F00 |
Definition at line 4396 of file cortex-m4-def.h.
| #define CAN_ERR_REC_S 8 |
Definition at line 4398 of file cortex-m4-def.h.
| #define CAN_ERR_RP 0x00008000 |
Definition at line 4395 of file cortex-m4-def.h.
| #define CAN_ERR_TEC_M 0x000000FF |
Definition at line 4397 of file cortex-m4-def.h.
| #define CAN_ERR_TEC_S 0 |
Definition at line 4399 of file cortex-m4-def.h.
| #define CAN_IF1ARB1_ID_M 0x0000FFFF |
Definition at line 4494 of file cortex-m4-def.h.
| #define CAN_IF1ARB1_ID_S 0 |
Definition at line 4495 of file cortex-m4-def.h.
| #define CAN_IF1ARB2_DIR 0x00002000 |
Definition at line 4504 of file cortex-m4-def.h.
| #define CAN_IF1ARB2_ID_M 0x00001FFF |
Definition at line 4505 of file cortex-m4-def.h.
| #define CAN_IF1ARB2_ID_S 0 |
Definition at line 4506 of file cortex-m4-def.h.
| #define CAN_IF1ARB2_MSGVAL 0x00008000 |
Definition at line 4502 of file cortex-m4-def.h.
| #define CAN_IF1ARB2_XTD 0x00004000 |
Definition at line 4503 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_ARB 0x00000020 |
Definition at line 4463 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_CLRINTPND 0x00000008 |
Definition at line 4465 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_CONTROL 0x00000010 |
Definition at line 4464 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_DATAA 0x00000002 |
Definition at line 4468 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_DATAB 0x00000001 |
Definition at line 4469 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_MASK 0x00000040 |
Definition at line 4462 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_NEWDAT 0x00000004 |
Definition at line 4466 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_TXRQST 0x00000004 |
Definition at line 4467 of file cortex-m4-def.h.
| #define CAN_IF1CMSK_WRNRD 0x00000080 |
Definition at line 4461 of file cortex-m4-def.h.
| #define CAN_IF1CRQ_BUSY 0x00008000 |
Definition at line 4452 of file cortex-m4-def.h.
| #define CAN_IF1CRQ_MNUM_M 0x0000003F |
Definition at line 4453 of file cortex-m4-def.h.
| #define CAN_IF1CRQ_MNUM_S 0 |
Definition at line 4454 of file cortex-m4-def.h.
| #define CAN_IF1DA1_DATA_M 0x0000FFFF |
Definition at line 4530 of file cortex-m4-def.h.
| #define CAN_IF1DA1_DATA_S 0 |
Definition at line 4531 of file cortex-m4-def.h.
| #define CAN_IF1DA2_DATA_M 0x0000FFFF |
Definition at line 4538 of file cortex-m4-def.h.
| #define CAN_IF1DA2_DATA_S 0 |
Definition at line 4539 of file cortex-m4-def.h.
| #define CAN_IF1DB1_DATA_M 0x0000FFFF |
Definition at line 4546 of file cortex-m4-def.h.
| #define CAN_IF1DB1_DATA_S 0 |
Definition at line 4547 of file cortex-m4-def.h.
| #define CAN_IF1DB2_DATA_M 0x0000FFFF |
Definition at line 4554 of file cortex-m4-def.h.
| #define CAN_IF1DB2_DATA_S 0 |
Definition at line 4555 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_DLC_M 0x0000000F |
Definition at line 4522 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_DLC_S 0 |
Definition at line 4523 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_EOB 0x00000080 |
Definition at line 4521 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_INTPND 0x00002000 |
Definition at line 4515 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_MSGLST 0x00004000 |
Definition at line 4514 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_NEWDAT 0x00008000 |
Definition at line 4513 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_RMTEN 0x00000200 |
Definition at line 4519 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_RXIE 0x00000400 |
Definition at line 4518 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_TXIE 0x00000800 |
Definition at line 4517 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_TXRQST 0x00000100 |
Definition at line 4520 of file cortex-m4-def.h.
| #define CAN_IF1MCTL_UMASK 0x00001000 |
Definition at line 4516 of file cortex-m4-def.h.
| #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF |
Definition at line 4476 of file cortex-m4-def.h.
| #define CAN_IF1MSK1_IDMSK_S 0 |
Definition at line 4477 of file cortex-m4-def.h.
| #define CAN_IF1MSK2_IDMSK_M 0x00001FFF |
Definition at line 4486 of file cortex-m4-def.h.
| #define CAN_IF1MSK2_IDMSK_S 0 |
Definition at line 4487 of file cortex-m4-def.h.
| #define CAN_IF1MSK2_MDIR 0x00004000 |
Definition at line 4485 of file cortex-m4-def.h.
| #define CAN_IF1MSK2_MXTD 0x00008000 |
Definition at line 4484 of file cortex-m4-def.h.
| #define CAN_IF2ARB1_ID_M 0x0000FFFF |
Definition at line 4604 of file cortex-m4-def.h.
| #define CAN_IF2ARB1_ID_S 0 |
Definition at line 4605 of file cortex-m4-def.h.
| #define CAN_IF2ARB2_DIR 0x00002000 |
Definition at line 4614 of file cortex-m4-def.h.
| #define CAN_IF2ARB2_ID_M 0x00001FFF |
Definition at line 4615 of file cortex-m4-def.h.
| #define CAN_IF2ARB2_ID_S 0 |
Definition at line 4616 of file cortex-m4-def.h.
| #define CAN_IF2ARB2_MSGVAL 0x00008000 |
Definition at line 4612 of file cortex-m4-def.h.
| #define CAN_IF2ARB2_XTD 0x00004000 |
Definition at line 4613 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_ARB 0x00000020 |
Definition at line 4573 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_CLRINTPND 0x00000008 |
Definition at line 4575 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_CONTROL 0x00000010 |
Definition at line 4574 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_DATAA 0x00000002 |
Definition at line 4578 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_DATAB 0x00000001 |
Definition at line 4579 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_MASK 0x00000040 |
Definition at line 4572 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_NEWDAT 0x00000004 |
Definition at line 4576 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_TXRQST 0x00000004 |
Definition at line 4577 of file cortex-m4-def.h.
| #define CAN_IF2CMSK_WRNRD 0x00000080 |
Definition at line 4571 of file cortex-m4-def.h.
| #define CAN_IF2CRQ_BUSY 0x00008000 |
Definition at line 4562 of file cortex-m4-def.h.
| #define CAN_IF2CRQ_MNUM_M 0x0000003F |
Definition at line 4563 of file cortex-m4-def.h.
| #define CAN_IF2CRQ_MNUM_S 0 |
Definition at line 4564 of file cortex-m4-def.h.
| #define CAN_IF2DA1_DATA_M 0x0000FFFF |
Definition at line 4640 of file cortex-m4-def.h.
| #define CAN_IF2DA1_DATA_S 0 |
Definition at line 4641 of file cortex-m4-def.h.
| #define CAN_IF2DA2_DATA_M 0x0000FFFF |
Definition at line 4648 of file cortex-m4-def.h.
| #define CAN_IF2DA2_DATA_S 0 |
Definition at line 4649 of file cortex-m4-def.h.
| #define CAN_IF2DB1_DATA_M 0x0000FFFF |
Definition at line 4656 of file cortex-m4-def.h.
| #define CAN_IF2DB1_DATA_S 0 |
Definition at line 4657 of file cortex-m4-def.h.
| #define CAN_IF2DB2_DATA_M 0x0000FFFF |
Definition at line 4664 of file cortex-m4-def.h.
| #define CAN_IF2DB2_DATA_S 0 |
Definition at line 4665 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_DLC_M 0x0000000F |
Definition at line 4632 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_DLC_S 0 |
Definition at line 4633 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_EOB 0x00000080 |
Definition at line 4631 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_INTPND 0x00002000 |
Definition at line 4625 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_MSGLST 0x00004000 |
Definition at line 4624 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_NEWDAT 0x00008000 |
Definition at line 4623 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_RMTEN 0x00000200 |
Definition at line 4629 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_RXIE 0x00000400 |
Definition at line 4628 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_TXIE 0x00000800 |
Definition at line 4627 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_TXRQST 0x00000100 |
Definition at line 4630 of file cortex-m4-def.h.
| #define CAN_IF2MCTL_UMASK 0x00001000 |
Definition at line 4626 of file cortex-m4-def.h.
| #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF |
Definition at line 4586 of file cortex-m4-def.h.
| #define CAN_IF2MSK1_IDMSK_S 0 |
Definition at line 4587 of file cortex-m4-def.h.
| #define CAN_IF2MSK2_IDMSK_M 0x00001FFF |
Definition at line 4596 of file cortex-m4-def.h.
| #define CAN_IF2MSK2_IDMSK_S 0 |
Definition at line 4597 of file cortex-m4-def.h.
| #define CAN_IF2MSK2_MDIR 0x00004000 |
Definition at line 4595 of file cortex-m4-def.h.
| #define CAN_IF2MSK2_MXTD 0x00008000 |
Definition at line 4594 of file cortex-m4-def.h.
| #define CAN_INT_INTID_M 0x0000FFFF |
Definition at line 4420 of file cortex-m4-def.h.
| #define CAN_INT_INTID_NONE 0x00000000 |
Definition at line 4421 of file cortex-m4-def.h.
| #define CAN_INT_INTID_STATUS 0x00008000 |
Definition at line 4422 of file cortex-m4-def.h.
| #define CAN_MSG1INT_INTPND_M 0x0000FFFF |
Definition at line 4704 of file cortex-m4-def.h.
| #define CAN_MSG1INT_INTPND_S 0 |
Definition at line 4705 of file cortex-m4-def.h.
| #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF |
Definition at line 4720 of file cortex-m4-def.h.
| #define CAN_MSG1VAL_MSGVAL_S 0 |
Definition at line 4721 of file cortex-m4-def.h.
| #define CAN_MSG2INT_INTPND_M 0x0000FFFF |
Definition at line 4712 of file cortex-m4-def.h.
| #define CAN_MSG2INT_INTPND_S 0 |
Definition at line 4713 of file cortex-m4-def.h.
| #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF |
Definition at line 4728 of file cortex-m4-def.h.
| #define CAN_MSG2VAL_MSGVAL_S 0 |
Definition at line 4729 of file cortex-m4-def.h.
| #define CAN_NWDA1_NEWDAT_M 0x0000FFFF |
Definition at line 4688 of file cortex-m4-def.h.
| #define CAN_NWDA1_NEWDAT_S 0 |
Definition at line 4689 of file cortex-m4-def.h.
| #define CAN_NWDA2_NEWDAT_M 0x0000FFFF |
Definition at line 4696 of file cortex-m4-def.h.
| #define CAN_NWDA2_NEWDAT_S 0 |
Definition at line 4697 of file cortex-m4-def.h.
| #define CAN_STS_BOFF 0x00000080 |
Definition at line 4374 of file cortex-m4-def.h.
| #define CAN_STS_EPASS 0x00000020 |
Definition at line 4376 of file cortex-m4-def.h.
| #define CAN_STS_EWARN 0x00000040 |
Definition at line 4375 of file cortex-m4-def.h.
| #define CAN_STS_LEC_ACK 0x00000003 |
Definition at line 4384 of file cortex-m4-def.h.
| #define CAN_STS_LEC_BIT0 0x00000005 |
Definition at line 4386 of file cortex-m4-def.h.
| #define CAN_STS_LEC_BIT1 0x00000004 |
Definition at line 4385 of file cortex-m4-def.h.
| #define CAN_STS_LEC_CRC 0x00000006 |
Definition at line 4387 of file cortex-m4-def.h.
| #define CAN_STS_LEC_FORM 0x00000002 |
Definition at line 4383 of file cortex-m4-def.h.
| #define CAN_STS_LEC_M 0x00000007 |
Definition at line 4380 of file cortex-m4-def.h.
| #define CAN_STS_LEC_NOEVENT 0x00000007 |
Definition at line 4388 of file cortex-m4-def.h.
| #define CAN_STS_LEC_NONE 0x00000000 |
Definition at line 4381 of file cortex-m4-def.h.
| #define CAN_STS_LEC_STUFF 0x00000001 |
Definition at line 4382 of file cortex-m4-def.h.
| #define CAN_STS_RXOK 0x00000010 |
Definition at line 4377 of file cortex-m4-def.h.
| #define CAN_STS_TXOK 0x00000008 |
Definition at line 4378 of file cortex-m4-def.h.
| #define CAN_TST_BASIC 0x00000004 |
Definition at line 4437 of file cortex-m4-def.h.
| #define CAN_TST_LBACK 0x00000010 |
Definition at line 4435 of file cortex-m4-def.h.
| #define CAN_TST_RX 0x00000080 |
Definition at line 4429 of file cortex-m4-def.h.
| #define CAN_TST_SILENT 0x00000008 |
Definition at line 4436 of file cortex-m4-def.h.
| #define CAN_TST_TX_CANCTL 0x00000000 |
Definition at line 4431 of file cortex-m4-def.h.
| #define CAN_TST_TX_DOMINANT 0x00000040 |
Definition at line 4433 of file cortex-m4-def.h.
| #define CAN_TST_TX_M 0x00000060 |
Definition at line 4430 of file cortex-m4-def.h.
| #define CAN_TST_TX_RECESSIVE 0x00000060 |
Definition at line 4434 of file cortex-m4-def.h.
| #define CAN_TST_TX_SAMPLE 0x00000020 |
Definition at line 4432 of file cortex-m4-def.h.
| #define CAN_TXRQ1_TXRQST_M 0x0000FFFF |
Definition at line 4672 of file cortex-m4-def.h.
| #define CAN_TXRQ1_TXRQST_S 0 |
Definition at line 4673 of file cortex-m4-def.h.
| #define CAN_TXRQ2_TXRQST_M 0x0000FFFF |
Definition at line 4680 of file cortex-m4-def.h.
| #define CAN_TXRQ2_TXRQST_S 0 |
Definition at line 4681 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ASRCP_M 0x00000600 |
Definition at line 4294 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ASRCP_PIN 0x00000000 |
Definition at line 4295 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ASRCP_PIN0 0x00000200 |
Definition at line 4296 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ASRCP_REF 0x00000400 |
Definition at line 4297 of file cortex-m4-def.h.
| #define COMP_ACCTL0_CINV 0x00000002 |
Definition at line 4310 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISEN_BOTH 0x0000000C |
Definition at line 4309 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISEN_FALL 0x00000004 |
Definition at line 4307 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISEN_LEVEL 0x00000000 |
Definition at line 4306 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISEN_M 0x0000000C |
Definition at line 4305 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISEN_RISE 0x00000008 |
Definition at line 4308 of file cortex-m4-def.h.
| #define COMP_ACCTL0_ISLVAL 0x00000010 |
Definition at line 4304 of file cortex-m4-def.h.
| #define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024)) |
Definition at line 1117 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TOEN 0x00000800 |
Definition at line 4293 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSEN_BOTH 0x00000060 |
Definition at line 4303 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSEN_FALL 0x00000020 |
Definition at line 4301 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSEN_LEVEL 0x00000000 |
Definition at line 4300 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSEN_M 0x00000060 |
Definition at line 4299 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSEN_RISE 0x00000040 |
Definition at line 4302 of file cortex-m4-def.h.
| #define COMP_ACCTL0_TSLVAL 0x00000080 |
Definition at line 4298 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ASRCP_M 0x00000600 |
Definition at line 4325 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ASRCP_PIN 0x00000000 |
Definition at line 4326 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ASRCP_PIN0 0x00000200 |
Definition at line 4327 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ASRCP_REF 0x00000400 |
Definition at line 4328 of file cortex-m4-def.h.
| #define COMP_ACCTL1_CINV 0x00000002 |
Definition at line 4342 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISEN_BOTH 0x0000000C |
Definition at line 4341 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISEN_FALL 0x00000004 |
Definition at line 4339 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISEN_LEVEL 0x00000000 |
Definition at line 4338 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISEN_M 0x0000000C |
Definition at line 4337 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISEN_RISE 0x00000008 |
Definition at line 4340 of file cortex-m4-def.h.
| #define COMP_ACCTL1_ISLVAL 0x00000010 |
Definition at line 4336 of file cortex-m4-def.h.
| #define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044)) |
Definition at line 1119 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TOEN 0x00000800 |
Definition at line 4324 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSEN_BOTH 0x00000060 |
Definition at line 4335 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSEN_FALL 0x00000020 |
Definition at line 4333 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSEN_LEVEL 0x00000000 |
Definition at line 4332 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSEN_M 0x00000060 |
Definition at line 4331 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSEN_RISE 0x00000040 |
Definition at line 4334 of file cortex-m4-def.h.
| #define COMP_ACCTL1_TSLVAL 0x00000080 |
Definition at line 4330 of file cortex-m4-def.h.
| #define COMP_ACINTEN_IN0 0x00000001 |
Definition at line 4268 of file cortex-m4-def.h.
| #define COMP_ACINTEN_IN1 0x00000002 |
Definition at line 4267 of file cortex-m4-def.h.
| #define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008)) |
Definition at line 1114 of file cortex-m4-def.h.
| #define COMP_ACMIS_IN0 0x00000001 |
Definition at line 4251 of file cortex-m4-def.h.
| #define COMP_ACMIS_IN1 0x00000002 |
Definition at line 4249 of file cortex-m4-def.h.
| #define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000)) |
Definition at line 1112 of file cortex-m4-def.h.
| #define COMP_ACREFCTL_EN 0x00000200 |
Definition at line 4276 of file cortex-m4-def.h.
| #define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010)) |
Definition at line 1115 of file cortex-m4-def.h.
| #define COMP_ACREFCTL_RNG 0x00000100 |
Definition at line 4277 of file cortex-m4-def.h.
| #define COMP_ACREFCTL_VREF_M 0x0000000F |
Definition at line 4278 of file cortex-m4-def.h.
| #define COMP_ACREFCTL_VREF_S 0 |
Definition at line 4279 of file cortex-m4-def.h.
| #define COMP_ACRIS_IN0 0x00000001 |
Definition at line 4260 of file cortex-m4-def.h.
| #define COMP_ACRIS_IN1 0x00000002 |
Definition at line 4259 of file cortex-m4-def.h.
| #define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004)) |
Definition at line 1113 of file cortex-m4-def.h.
| #define COMP_ACSTAT0_OVAL 0x00000002 |
Definition at line 4286 of file cortex-m4-def.h.
| #define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020)) |
Definition at line 1116 of file cortex-m4-def.h.
| #define COMP_ACSTAT1_OVAL 0x00000002 |
Definition at line 4317 of file cortex-m4-def.h.
| #define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040)) |
Definition at line 1118 of file cortex-m4-def.h.
| #define COMP_PP_C0O 0x00010000 |
Definition at line 4351 of file cortex-m4-def.h.
| #define COMP_PP_C1O 0x00020000 |
Definition at line 4350 of file cortex-m4-def.h.
| #define COMP_PP_C2O 0x00040000 |
Definition at line 4349 of file cortex-m4-def.h.
| #define COMP_PP_CMP0 0x00000001 |
Definition at line 4354 of file cortex-m4-def.h.
| #define COMP_PP_CMP1 0x00000002 |
Definition at line 4353 of file cortex-m4-def.h.
| #define COMP_PP_CMP2 0x00000004 |
Definition at line 4352 of file cortex-m4-def.h.
| #define COMP_PP_R (*((volatile unsigned long *)0x4003CFC0)) |
Definition at line 1120 of file cortex-m4-def.h.
| #define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF |
Definition at line 5661 of file cortex-m4-def.h.
| #define EEPROM_EEBLOCK_BLOCK_S 0 |
Definition at line 5662 of file cortex-m4-def.h.
| #define EEPROM_EEBLOCK_R (*((volatile unsigned long *)0x400AF004)) |
Definition at line 1592 of file cortex-m4-def.h.
| #define EEPROM_EEDBGME_KEY_M 0xFFFF0000 |
Definition at line 5788 of file cortex-m4-def.h.
| #define EEPROM_EEDBGME_KEY_S 16 |
Definition at line 5790 of file cortex-m4-def.h.
| #define EEPROM_EEDBGME_ME 0x00000001 |
Definition at line 5789 of file cortex-m4-def.h.
| #define EEPROM_EEDBGME_R (*((volatile unsigned long *)0x400AF080)) |
Definition at line 1605 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_INVPL 0x00000100 |
Definition at line 5700 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_NOPERM 0x00000010 |
Definition at line 5702 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_R (*((volatile unsigned long *)0x400AF018)) |
Definition at line 1596 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_WKCOPY 0x00000008 |
Definition at line 5703 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_WKERASE 0x00000004 |
Definition at line 5704 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_WORKING 0x00000001 |
Definition at line 5705 of file cortex-m4-def.h.
| #define EEPROM_EEDONE_WRBUSY 0x00000020 |
Definition at line 5701 of file cortex-m4-def.h.
| #define EEPROM_EEHIDE_HN_M 0xFFFFFFFE |
Definition at line 5781 of file cortex-m4-def.h.
| #define EEPROM_EEHIDE_R (*((volatile unsigned long *)0x400AF050)) |
Definition at line 1604 of file cortex-m4-def.h.
| #define EEPROM_EEINT_INT 0x00000001 |
Definition at line 5774 of file cortex-m4-def.h.
| #define EEPROM_EEINT_R (*((volatile unsigned long *)0x400AF040)) |
Definition at line 1603 of file cortex-m4-def.h.
| #define EEPROM_EEOFFSET_OFFSET_M 0x0000000F |
Definition at line 5670 of file cortex-m4-def.h.
| #define EEPROM_EEOFFSET_OFFSET_S 0 |
Definition at line 5672 of file cortex-m4-def.h.
| #define EEPROM_EEOFFSET_R (*((volatile unsigned long *)0x400AF008)) |
Definition at line 1593 of file cortex-m4-def.h.
| #define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF |
Definition at line 5750 of file cortex-m4-def.h.
| #define EEPROM_EEPASS0_PASS_S 0 |
Definition at line 5751 of file cortex-m4-def.h.
| #define EEPROM_EEPASS0_R (*((volatile unsigned long *)0x400AF034)) |
Definition at line 1600 of file cortex-m4-def.h.
| #define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF |
Definition at line 5758 of file cortex-m4-def.h.
| #define EEPROM_EEPASS1_PASS_S 0 |
Definition at line 5759 of file cortex-m4-def.h.
| #define EEPROM_EEPASS1_R (*((volatile unsigned long *)0x400AF038)) |
Definition at line 1601 of file cortex-m4-def.h.
| #define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF |
Definition at line 5766 of file cortex-m4-def.h.
| #define EEPROM_EEPASS2_PASS_S 0 |
Definition at line 5767 of file cortex-m4-def.h.
| #define EEPROM_EEPASS2_R (*((volatile unsigned long *)0x400AF03C)) |
Definition at line 1602 of file cortex-m4-def.h.
| #define EEPROM_EEPROMPP_R (*((volatile unsigned long *)0x400AFFC0)) |
Definition at line 10049 of file cortex-m4-def.h.
| #define EEPROM_EEPROMPP_SIZE_M 0x0000001F |
Definition at line 10056 of file cortex-m4-def.h.
| #define EEPROM_EEPROMPP_SIZE_S 0 |
Definition at line 10057 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_ACC 0x00000008 |
Definition at line 5731 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_PROT_M 0x00000007 |
Definition at line 5732 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_PROT_RONPW 0x00000002 |
Definition at line 5741 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_PROT_RWNPW 0x00000000 |
Definition at line 5733 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_PROT_RWPW 0x00000001 |
Definition at line 5738 of file cortex-m4-def.h.
| #define EEPROM_EEPROT_R (*((volatile unsigned long *)0x400AF030)) |
Definition at line 1599 of file cortex-m4-def.h.
| #define EEPROM_EERDWR_R (*((volatile unsigned long *)0x400AF010)) |
Definition at line 1594 of file cortex-m4-def.h.
| #define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF |
Definition at line 5680 of file cortex-m4-def.h.
| #define EEPROM_EERDWR_VALUE_S 0 |
Definition at line 5681 of file cortex-m4-def.h.
| #define EEPROM_EERDWRINC_R (*((volatile unsigned long *)0x400AF014)) |
Definition at line 1595 of file cortex-m4-def.h.
| #define EEPROM_EERDWRINC_VALUE_M 0xFFFFFFFF |
Definition at line 5689 of file cortex-m4-def.h.
| #define EEPROM_EERDWRINC_VALUE_S 0 |
Definition at line 5692 of file cortex-m4-def.h.
| #define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 |
Definition at line 5651 of file cortex-m4-def.h.
| #define EEPROM_EESIZE_BLKCNT_S 16 |
Definition at line 5653 of file cortex-m4-def.h.
| #define EEPROM_EESIZE_R (*((volatile unsigned long *)0x400AF000)) |
Definition at line 1591 of file cortex-m4-def.h.
| #define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF |
Definition at line 5652 of file cortex-m4-def.h.
| #define EEPROM_EESIZE_WORDCNT_S 0 |
Definition at line 5654 of file cortex-m4-def.h.
| #define EEPROM_EESUPP_EREQ 0x00000002 |
Definition at line 5714 of file cortex-m4-def.h.
| #define EEPROM_EESUPP_ERETRY 0x00000004 |
Definition at line 5713 of file cortex-m4-def.h.
| #define EEPROM_EESUPP_PRETRY 0x00000008 |
Definition at line 5712 of file cortex-m4-def.h.
| #define EEPROM_EESUPP_R (*((volatile unsigned long *)0x400AF01C)) |
Definition at line 1597 of file cortex-m4-def.h.
| #define EEPROM_EESUPP_START 0x00000001 |
Definition at line 5715 of file cortex-m4-def.h.
| #define EEPROM_EEUNLOCK_R (*((volatile unsigned long *)0x400AF020)) |
Definition at line 1598 of file cortex-m4-def.h.
| #define EEPROM_EEUNLOCK_UNLOCK_M 0xFFFFFFFF |
Definition at line 5723 of file cortex-m4-def.h.
| #define EEPROM_PP_R (*((volatile unsigned long *)0x400AFFC0)) |
Definition at line 1606 of file cortex-m4-def.h.
| #define EEPROM_PP_SIZE_M 0x0000001F |
Definition at line 5797 of file cortex-m4-def.h.
| #define EEPROM_PP_SIZE_S 0 |
Definition at line 5798 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_DBG0 0x00000001 |
Definition at line 6172 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_DBG1 0x00000002 |
Definition at line 6171 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_EN 0x00000100 |
Definition at line 6170 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_NW 0x80000000 |
Definition at line 6150 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_0 0x00000000 |
Definition at line 6161 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_1 0x00000400 |
Definition at line 6162 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_2 0x00000800 |
Definition at line 6163 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_3 0x00000C00 |
Definition at line 6164 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_4 0x00001000 |
Definition at line 6165 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_5 0x00001400 |
Definition at line 6166 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_6 0x00001800 |
Definition at line 6167 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_7 0x00001C00 |
Definition at line 6168 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PIN_M 0x00001C00 |
Definition at line 6160 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_POL 0x00000200 |
Definition at line 6169 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_A 0x00000000 |
Definition at line 6152 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_B 0x00002000 |
Definition at line 6153 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_C 0x00004000 |
Definition at line 6154 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_D 0x00006000 |
Definition at line 6155 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_E 0x00008000 |
Definition at line 6156 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_F 0x0000A000 |
Definition at line 6157 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_G 0x0000C000 |
Definition at line 6158 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_H 0x0000E000 |
Definition at line 6159 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_PORT_M 0x0000E000 |
Definition at line 6151 of file cortex-m4-def.h.
| #define FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0)) |
Definition at line 1653 of file cortex-m4-def.h.
| #define FLASH_FCIM_AMASK 0x00000001 |
Definition at line 6056 of file cortex-m4-def.h.
| #define FLASH_FCIM_EMASK 0x00000004 |
Definition at line 6054 of file cortex-m4-def.h.
| #define FLASH_FCIM_ERMASK 0x00000800 |
Definition at line 6051 of file cortex-m4-def.h.
| #define FLASH_FCIM_INVDMASK 0x00000400 |
Definition at line 6052 of file cortex-m4-def.h.
| #define FLASH_FCIM_PMASK 0x00000002 |
Definition at line 6055 of file cortex-m4-def.h.
| #define FLASH_FCIM_PROGMASK 0x00002000 |
Definition at line 6050 of file cortex-m4-def.h.
| #define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010)) |
Definition at line 1644 of file cortex-m4-def.h.
| #define FLASH_FCIM_VOLTMASK 0x00000200 |
Definition at line 6053 of file cortex-m4-def.h.
| #define FLASH_FCMISC_AMISC 0x00000001 |
Definition at line 6075 of file cortex-m4-def.h.
| #define FLASH_FCMISC_EMISC 0x00000004 |
Definition at line 6071 of file cortex-m4-def.h.
| #define FLASH_FCMISC_ERMISC 0x00000800 |
Definition at line 6065 of file cortex-m4-def.h.
| #define FLASH_FCMISC_INVDMISC 0x00000400 |
Definition at line 6067 of file cortex-m4-def.h.
| #define FLASH_FCMISC_PMISC 0x00000002 |
Definition at line 6073 of file cortex-m4-def.h.
| #define FLASH_FCMISC_PROGMISC 0x00002000 |
Definition at line 6063 of file cortex-m4-def.h.
| #define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014)) |
Definition at line 1645 of file cortex-m4-def.h.
| #define FLASH_FCMISC_VOLTMISC 0x00000200 |
Definition at line 6069 of file cortex-m4-def.h.
| #define FLASH_FCRIS_ARIS 0x00000001 |
Definition at line 6043 of file cortex-m4-def.h.
| #define FLASH_FCRIS_ERIS 0x00000004 |
Definition at line 6041 of file cortex-m4-def.h.
| #define FLASH_FCRIS_ERRIS 0x00000800 |
Definition at line 6037 of file cortex-m4-def.h.
| #define FLASH_FCRIS_INVDRIS 0x00000400 |
Definition at line 6038 of file cortex-m4-def.h.
| #define FLASH_FCRIS_PRIS 0x00000002 |
Definition at line 6042 of file cortex-m4-def.h.
| #define FLASH_FCRIS_PROGRIS 0x00002000 |
Definition at line 6036 of file cortex-m4-def.h.
| #define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C)) |
Definition at line 1643 of file cortex-m4-def.h.
| #define FLASH_FCRIS_VOLTRIS 0x00000200 |
Definition at line 6040 of file cortex-m4-def.h.
| #define FLASH_FMA_OFFSET_M 0x0003FFFF |
Definition at line 6009 of file cortex-m4-def.h.
| #define FLASH_FMA_OFFSET_S 0 |
Definition at line 6010 of file cortex-m4-def.h.
| #define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000)) |
Definition at line 1640 of file cortex-m4-def.h.
| #define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020)) |
Definition at line 1646 of file cortex-m4-def.h.
| #define FLASH_FMC2_WRBUF 0x00000001 |
Definition at line 6084 of file cortex-m4-def.h.
| #define FLASH_FMC2_WRKEY 0xA4420000 |
Definition at line 6083 of file cortex-m4-def.h.
| #define FLASH_FMC_COMT 0x00000008 |
Definition at line 6026 of file cortex-m4-def.h.
| #define FLASH_FMC_ERASE 0x00000002 |
Definition at line 6028 of file cortex-m4-def.h.
| #define FLASH_FMC_MERASE 0x00000004 |
Definition at line 6027 of file cortex-m4-def.h.
| #define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008)) |
Definition at line 1642 of file cortex-m4-def.h.
| #define FLASH_FMC_WRITE 0x00000001 |
Definition at line 6029 of file cortex-m4-def.h.
| #define FLASH_FMC_WRKEY 0xA4420000 |
Definition at line 6025 of file cortex-m4-def.h.
| #define FLASH_FMD_DATA_M 0xFFFFFFFF |
Definition at line 6017 of file cortex-m4-def.h.
| #define FLASH_FMD_DATA_S 0 |
Definition at line 6018 of file cortex-m4-def.h.
| #define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004)) |
Definition at line 1641 of file cortex-m4-def.h.
| #define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400)) |
Definition at line 1662 of file cortex-m4-def.h.
| #define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404)) |
Definition at line 1663 of file cortex-m4-def.h.
| #define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408)) |
Definition at line 1664 of file cortex-m4-def.h.
| #define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C)) |
Definition at line 1665 of file cortex-m4-def.h.
| #define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200)) |
Definition at line 1658 of file cortex-m4-def.h.
| #define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204)) |
Definition at line 1659 of file cortex-m4-def.h.
| #define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208)) |
Definition at line 1660 of file cortex-m4-def.h.
| #define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C)) |
Definition at line 1661 of file cortex-m4-def.h.
| #define FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0)) |
Definition at line 1649 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_128KB 0x0000003F |
Definition at line 6111 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_16KB 0x00000007 |
Definition at line 6107 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_192KB 0x0000005F |
Definition at line 6112 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_256KB 0x0000007F |
Definition at line 6113 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_32KB 0x0000000F |
Definition at line 6108 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_64KB 0x0000001F |
Definition at line 6109 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_8KB 0x00000003 |
Definition at line 6106 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_96KB 0x0000002F |
Definition at line 6110 of file cortex-m4-def.h.
| #define FLASH_FSIZE_SIZE_M 0x0000FFFF |
Definition at line 6105 of file cortex-m4-def.h.
| #define FLASH_FWBN_DATA_M 0xFFFFFFFF |
Definition at line 6098 of file cortex-m4-def.h.
| #define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100)) |
Definition at line 1648 of file cortex-m4-def.h.
| #define FLASH_FWBVAL_FWB_M 0xFFFFFFFF |
Definition at line 6091 of file cortex-m4-def.h.
| #define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030)) |
Definition at line 1647 of file cortex-m4-def.h.
| #define FLASH_RMCTL_BA 0x00000001 |
Definition at line 6143 of file cortex-m4-def.h.
| #define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0)) |
Definition at line 1652 of file cortex-m4-def.h.
| #define FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC)) |
Definition at line 1651 of file cortex-m4-def.h.
| #define FLASH_ROMSWMAP_SAFERTOS 0x00000001 |
Definition at line 6136 of file cortex-m4-def.h.
| #define FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4)) |
Definition at line 1650 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_12KB 0x0000002F |
Definition at line 6125 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_16KB 0x0000003F |
Definition at line 6126 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_20KB 0x0000004F |
Definition at line 6127 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_24KB 0x0000005F |
Definition at line 6128 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_2KB 0x00000007 |
Definition at line 6121 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_32KB 0x0000007F |
Definition at line 6129 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_4KB 0x0000000F |
Definition at line 6122 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_6KB 0x00000017 |
Definition at line 6123 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_8KB 0x0000001F |
Definition at line 6124 of file cortex-m4-def.h.
| #define FLASH_SSIZE_SIZE_M 0x0000FFFF |
Definition at line 6120 of file cortex-m4-def.h.
| #define FLASH_USERREG0_DATA_M 0xFFFFFFFF |
Definition at line 6179 of file cortex-m4-def.h.
| #define FLASH_USERREG0_DATA_S 0 |
Definition at line 6180 of file cortex-m4-def.h.
| #define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0)) |
Definition at line 1654 of file cortex-m4-def.h.
| #define FLASH_USERREG1_DATA_M 0xFFFFFFFF |
Definition at line 6187 of file cortex-m4-def.h.
| #define FLASH_USERREG1_DATA_S 0 |
Definition at line 6188 of file cortex-m4-def.h.
| #define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4)) |
Definition at line 1655 of file cortex-m4-def.h.
| #define FLASH_USERREG2_DATA_M 0xFFFFFFFF |
Definition at line 6195 of file cortex-m4-def.h.
| #define FLASH_USERREG2_DATA_S 0 |
Definition at line 6196 of file cortex-m4-def.h.
| #define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8)) |
Definition at line 1656 of file cortex-m4-def.h.
| #define FLASH_USERREG3_DATA_M 0xFFFFFFFF |
Definition at line 6203 of file cortex-m4-def.h.
| #define FLASH_USERREG3_DATA_S 0 |
Definition at line 6204 of file cortex-m4-def.h.
| #define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC)) |
Definition at line 1657 of file cortex-m4-def.h.
| #define GPIO_ADCCTL_R_OFF (0x530UL) |
Definition at line 103 of file cortex-m4-def.h.
| #define GPIO_AFSEL_R_OFF (0x420UL) |
Definition at line 90 of file cortex-m4-def.h.
| #define GPIO_AMSEL_R_OFF (0x528UL) |
Definition at line 101 of file cortex-m4-def.h.
| #define GPIO_CR_R_OFF (0x524UL) |
Definition at line 100 of file cortex-m4-def.h.
| #define GPIO_DATA_R_OFF (0x3FCUL) |
Definition at line 81 of file cortex-m4-def.h.
| #define GPIO_DEN_R_OFF (0x51CUL) |
Definition at line 98 of file cortex-m4-def.h.
| #define GPIO_DIR_R_OFF (0x400UL) |
Definition at line 82 of file cortex-m4-def.h.
| #define GPIO_DMACTL_R_OFF (0x534UL) |
Definition at line 104 of file cortex-m4-def.h.
| #define GPIO_DR2R_R_OFF (0x500UL) |
Definition at line 91 of file cortex-m4-def.h.
| #define GPIO_DR4R_R_OFF (0x504UL) |
Definition at line 92 of file cortex-m4-def.h.
| #define GPIO_DR8R_R_OFF (0x508UL) |
Definition at line 93 of file cortex-m4-def.h.
| #define GPIO_IBE_R_OFF (0x408UL) |
Definition at line 84 of file cortex-m4-def.h.
| #define GPIO_ICR_GPIO_M 0x000000FF |
Definition at line 2054 of file cortex-m4-def.h.
| #define GPIO_ICR_GPIO_S 0 |
Definition at line 2055 of file cortex-m4-def.h.
| #define GPIO_ICR_R_OFF (0x41CUL) |
Definition at line 89 of file cortex-m4-def.h.
| #define GPIO_IEV_R_OFF (0x40CUL) |
Definition at line 85 of file cortex-m4-def.h.
| #define GPIO_IM_GPIO_M 0x000000FF |
Definition at line 2030 of file cortex-m4-def.h.
| #define GPIO_IM_GPIO_S 0 |
Definition at line 2031 of file cortex-m4-def.h.
| #define GPIO_IM_R_OFF (0x410UL) |
Definition at line 86 of file cortex-m4-def.h.
| #define GPIO_IS_R_OFF (0x404UL) |
Definition at line 83 of file cortex-m4-def.h.
| #define GPIO_LOCK_KEY 0x4C4F434B |
Definition at line 2067 of file cortex-m4-def.h.
| #define GPIO_LOCK_LOCKED 0x00000001 |
Definition at line 2065 of file cortex-m4-def.h.
| #define GPIO_LOCK_M 0xFFFFFFFF |
Definition at line 2062 of file cortex-m4-def.h.
| #define GPIO_LOCK_R_OFF (0x520UL) |
Definition at line 99 of file cortex-m4-def.h.
| #define GPIO_LOCK_UNLOCKED 0x00000000 |
Definition at line 2063 of file cortex-m4-def.h.
| #define GPIO_MIS_GPIO_M 0x000000FF |
Definition at line 2046 of file cortex-m4-def.h.
| #define GPIO_MIS_GPIO_S 0 |
Definition at line 2047 of file cortex-m4-def.h.
| #define GPIO_MIS_R_OFF (0x418UL) |
Definition at line 88 of file cortex-m4-def.h.
| #define GPIO_ODR_R_OFF (0x50CUL) |
Definition at line 94 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA0_M 0x0000000F |
Definition at line 2096 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA0_U0RX 0x00000001 |
Definition at line 2097 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA1_M 0x000000F0 |
Definition at line 2094 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA1_U0TX 0x00000010 |
Definition at line 2095 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA2_M 0x00000F00 |
Definition at line 2092 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA2_SSI0CLK 0x00000200 |
Definition at line 2093 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA3_M 0x0000F000 |
Definition at line 2090 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA3_SSI0FSS 0x00002000 |
Definition at line 2091 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA4_M 0x000F0000 |
Definition at line 2088 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA4_SSI0RX 0x00020000 |
Definition at line 2089 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA5_M 0x00F00000 |
Definition at line 2086 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA5_SSI0TX 0x00200000 |
Definition at line 2087 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA6_I2C1SCL 0x03000000 |
Definition at line 2085 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA6_M 0x0F000000 |
Definition at line 2084 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA7_I2C1SDA 0x30000000 |
Definition at line 2083 of file cortex-m4-def.h.
| #define GPIO_PCTL_PA7_M 0xF0000000 |
Definition at line 2082 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB0_M 0x0000000F |
Definition at line 2128 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB0_T2CCP0 0x00000007 |
Definition at line 2130 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB0_U1RX 0x00000001 |
Definition at line 2129 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB1_M 0x000000F0 |
Definition at line 2125 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB1_T2CCP1 0x00000070 |
Definition at line 2127 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB1_U1TX 0x00000010 |
Definition at line 2126 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB2_I2C0SCL 0x00000300 |
Definition at line 2123 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB2_M 0x00000F00 |
Definition at line 2122 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB2_T3CCP0 0x00000700 |
Definition at line 2124 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB3_I2C0SDA 0x00003000 |
Definition at line 2120 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB3_M 0x0000F000 |
Definition at line 2119 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB3_T3CCP1 0x00007000 |
Definition at line 2121 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB4_CAN0RX 0x00080000 |
Definition at line 2118 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB4_M 0x000F0000 |
Definition at line 2115 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB4_SSI2CLK 0x00020000 |
Definition at line 2116 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB4_T1CCP0 0x00070000 |
Definition at line 2117 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB5_CAN0TX 0x00800000 |
Definition at line 2114 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB5_M 0x00F00000 |
Definition at line 2111 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB5_SSI2FSS 0x00200000 |
Definition at line 2112 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB5_T1CCP1 0x00700000 |
Definition at line 2113 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB6_M 0x0F000000 |
Definition at line 2108 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB6_SSI2RX 0x02000000 |
Definition at line 2109 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB6_T0CCP0 0x07000000 |
Definition at line 2110 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB7_M 0xF0000000 |
Definition at line 2105 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB7_SSI2TX 0x20000000 |
Definition at line 2106 of file cortex-m4-def.h.
| #define GPIO_PCTL_PB7_T0CCP1 0x70000000 |
Definition at line 2107 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC0_M 0x0000000F |
Definition at line 2163 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC0_T4CCP0 0x00000007 |
Definition at line 2165 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC0_TCK 0x00000001 |
Definition at line 2164 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC1_M 0x000000F0 |
Definition at line 2160 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC1_T4CCP1 0x00000070 |
Definition at line 2162 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC1_TMS 0x00000010 |
Definition at line 2161 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC2_M 0x00000F00 |
Definition at line 2157 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC2_T5CCP0 0x00000700 |
Definition at line 2159 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC2_TDI 0x00000100 |
Definition at line 2158 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC3_M 0x0000F000 |
Definition at line 2154 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC3_T5CCP1 0x00007000 |
Definition at line 2156 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC3_TDO 0x00001000 |
Definition at line 2155 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC4_M 0x000F0000 |
Definition at line 2149 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC4_U1RTS 0x00080000 |
Definition at line 2153 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC4_U1RX 0x00020000 |
Definition at line 2151 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC4_U4RX 0x00010000 |
Definition at line 2150 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC4_WT0CCP0 0x00070000 |
Definition at line 2152 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC5_M 0x00F00000 |
Definition at line 2144 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC5_U1CTS 0x00800000 |
Definition at line 2148 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC5_U1TX 0x00200000 |
Definition at line 2146 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC5_U4TX 0x00100000 |
Definition at line 2145 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC5_WT0CCP1 0x00700000 |
Definition at line 2147 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC6_M 0x0F000000 |
Definition at line 2141 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC6_U3RX 0x01000000 |
Definition at line 2142 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC6_WT1CCP0 0x07000000 |
Definition at line 2143 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC7_M 0xF0000000 |
Definition at line 2138 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC7_U3TX 0x10000000 |
Definition at line 2139 of file cortex-m4-def.h.
| #define GPIO_PCTL_PC7_WT1CCP1 0x70000000 |
Definition at line 2140 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD0_I2C3SCL 0x00000003 |
Definition at line 2202 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD0_M 0x0000000F |
Definition at line 2199 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD0_SSI1CLK 0x00000002 |
Definition at line 2201 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD0_SSI3CLK 0x00000001 |
Definition at line 2200 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD0_WT2CCP0 0x00000007 |
Definition at line 2203 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD1_I2C3SDA 0x00000030 |
Definition at line 2197 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD1_M 0x000000F0 |
Definition at line 2194 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD1_SSI1FSS 0x00000020 |
Definition at line 2196 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD1_SSI3FSS 0x00000010 |
Definition at line 2195 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD1_WT2CCP1 0x00000070 |
Definition at line 2198 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD2_M 0x00000F00 |
Definition at line 2190 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD2_SSI1RX 0x00000200 |
Definition at line 2192 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD2_SSI3RX 0x00000100 |
Definition at line 2191 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD2_WT3CCP0 0x00000700 |
Definition at line 2193 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD3_M 0x0000F000 |
Definition at line 2186 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD3_SSI1TX 0x00002000 |
Definition at line 2188 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD3_SSI3TX 0x00001000 |
Definition at line 2187 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD3_WT3CCP1 0x00007000 |
Definition at line 2189 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD4_M 0x000F0000 |
Definition at line 2183 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD4_U6RX 0x00010000 |
Definition at line 2184 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD4_WT4CCP0 0x00070000 |
Definition at line 2185 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD5_M 0x00F00000 |
Definition at line 2180 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD5_U6TX 0x00100000 |
Definition at line 2181 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD5_WT4CCP1 0x00700000 |
Definition at line 2182 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD6_M 0x0F000000 |
Definition at line 2177 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD6_U2RX 0x01000000 |
Definition at line 2178 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD6_WT5CCP0 0x07000000 |
Definition at line 2179 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD7_M 0xF0000000 |
Definition at line 2173 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD7_NMI 0x80000000 |
Definition at line 2176 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD7_U2TX 0x10000000 |
Definition at line 2174 of file cortex-m4-def.h.
| #define GPIO_PCTL_PD7_WT5CCP1 0x70000000 |
Definition at line 2175 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE0_M 0x0000000F |
Definition at line 2223 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE0_U7RX 0x00000001 |
Definition at line 2224 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE1_M 0x000000F0 |
Definition at line 2221 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE1_U7TX 0x00000010 |
Definition at line 2222 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE2_M 0x00000F00 |
Definition at line 2220 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE3_M 0x0000F000 |
Definition at line 2219 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE4_CAN0RX 0x00080000 |
Definition at line 2218 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE4_I2C2SCL 0x00030000 |
Definition at line 2217 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE4_M 0x000F0000 |
Definition at line 2215 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE4_U5RX 0x00010000 |
Definition at line 2216 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE5_CAN0TX 0x00800000 |
Definition at line 2214 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE5_I2C2SDA 0x00300000 |
Definition at line 2213 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE5_M 0x00F00000 |
Definition at line 2211 of file cortex-m4-def.h.
| #define GPIO_PCTL_PE5_U5TX 0x00100000 |
Definition at line 2212 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_C0O 0x00000009 |
Definition at line 2255 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_CAN0RX 0x00000003 |
Definition at line 2252 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_M 0x0000000F |
Definition at line 2249 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_NMI 0x00000008 |
Definition at line 2254 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_SSI1RX 0x00000002 |
Definition at line 2251 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_T0CCP0 0x00000007 |
Definition at line 2253 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_TRD2 0x0000000E |
Definition at line 2256 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF0_U1RTS 0x00000001 |
Definition at line 2250 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_C1O 0x00000090 |
Definition at line 2247 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_M 0x000000F0 |
Definition at line 2243 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_SSI1TX 0x00000020 |
Definition at line 2245 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_T0CCP1 0x00000070 |
Definition at line 2246 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_TRD1 0x000000E0 |
Definition at line 2248 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF1_U1CTS 0x00000010 |
Definition at line 2244 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF2_M 0x00000F00 |
Definition at line 2239 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF2_SSI1CLK 0x00000200 |
Definition at line 2240 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF2_T1CCP0 0x00000700 |
Definition at line 2241 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF2_TRD0 0x00000E00 |
Definition at line 2242 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF3_CAN0TX 0x00003000 |
Definition at line 2236 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF3_M 0x0000F000 |
Definition at line 2234 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF3_SSI1FSS 0x00002000 |
Definition at line 2235 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF3_T1CCP1 0x00007000 |
Definition at line 2237 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF3_TRCLK 0x0000E000 |
Definition at line 2238 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF4_M 0x000F0000 |
Definition at line 2232 of file cortex-m4-def.h.
| #define GPIO_PCTL_PF4_T2CCP0 0x00070000 |
Definition at line 2233 of file cortex-m4-def.h.
| #define GPIO_PCTL_R_OFF (0x52CUL) |
Definition at line 102 of file cortex-m4-def.h.
| #define GPIO_PDR_R_OFF (0x514UL) |
Definition at line 96 of file cortex-m4-def.h.
| #define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530)) |
Definition at line 135 of file cortex-m4-def.h.
| #define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420)) |
Definition at line 122 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530)) |
Definition at line 1417 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420)) |
Definition at line 1404 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528)) |
Definition at line 1415 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524)) |
Definition at line 1414 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DATA_BITS_R ((volatile unsigned long *)0x40058000) |
Definition at line 1393 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC)) |
Definition at line 1395 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C)) |
Definition at line 1412 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400)) |
Definition at line 1396 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534)) |
Definition at line 1418 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500)) |
Definition at line 1405 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504)) |
Definition at line 1406 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508)) |
Definition at line 1407 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408)) |
Definition at line 1398 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C)) |
Definition at line 1403 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C)) |
Definition at line 1399 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410)) |
Definition at line 1400 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404)) |
Definition at line 1397 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520)) |
Definition at line 1413 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418)) |
Definition at line 1402 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C)) |
Definition at line 1408 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C)) |
Definition at line 1416 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514)) |
Definition at line 1410 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510)) |
Definition at line 1409 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414)) |
Definition at line 1401 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538)) |
Definition at line 1419 of file cortex-m4-def.h.
| #define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518)) |
Definition at line 1411 of file cortex-m4-def.h.
| #define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528)) |
Definition at line 133 of file cortex-m4-def.h.
| #define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524)) |
Definition at line 132 of file cortex-m4-def.h.
| #define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000) |
Definition at line 112 of file cortex-m4-def.h.
| #define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC)) |
Definition at line 113 of file cortex-m4-def.h.
| #define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C)) |
Definition at line 130 of file cortex-m4-def.h.
| #define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400)) |
Definition at line 114 of file cortex-m4-def.h.
| #define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534)) |
Definition at line 136 of file cortex-m4-def.h.
| #define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500)) |
Definition at line 123 of file cortex-m4-def.h.
| #define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504)) |
Definition at line 124 of file cortex-m4-def.h.
| #define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508)) |
Definition at line 125 of file cortex-m4-def.h.
| #define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408)) |
Definition at line 116 of file cortex-m4-def.h.
| #define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C)) |
Definition at line 121 of file cortex-m4-def.h.
| #define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C)) |
Definition at line 117 of file cortex-m4-def.h.
| #define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410)) |
Definition at line 118 of file cortex-m4-def.h.
| #define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404)) |
Definition at line 115 of file cortex-m4-def.h.
| #define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520)) |
Definition at line 131 of file cortex-m4-def.h.
| #define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418)) |
Definition at line 120 of file cortex-m4-def.h.
| #define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C)) |
Definition at line 126 of file cortex-m4-def.h.
| #define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C)) |
Definition at line 134 of file cortex-m4-def.h.
| #define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514)) |
Definition at line 128 of file cortex-m4-def.h.
| #define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510)) |
Definition at line 127 of file cortex-m4-def.h.
| #define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414)) |
Definition at line 119 of file cortex-m4-def.h.
| #define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538)) |
Definition at line 137 of file cortex-m4-def.h.
| #define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518)) |
Definition at line 129 of file cortex-m4-def.h.
| #define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530)) |
Definition at line 167 of file cortex-m4-def.h.
| #define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420)) |
Definition at line 154 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530)) |
Definition at line 1450 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420)) |
Definition at line 1437 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528)) |
Definition at line 1448 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524)) |
Definition at line 1447 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DATA_BITS_R ((volatile unsigned long *)0x40059000) |
Definition at line 1426 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC)) |
Definition at line 1428 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C)) |
Definition at line 1445 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400)) |
Definition at line 1429 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534)) |
Definition at line 1451 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500)) |
Definition at line 1438 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504)) |
Definition at line 1439 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508)) |
Definition at line 1440 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408)) |
Definition at line 1431 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C)) |
Definition at line 1436 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C)) |
Definition at line 1432 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410)) |
Definition at line 1433 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404)) |
Definition at line 1430 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520)) |
Definition at line 1446 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418)) |
Definition at line 1435 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C)) |
Definition at line 1441 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C)) |
Definition at line 1449 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514)) |
Definition at line 1443 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510)) |
Definition at line 1442 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414)) |
Definition at line 1434 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538)) |
Definition at line 1452 of file cortex-m4-def.h.
| #define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518)) |
Definition at line 1444 of file cortex-m4-def.h.
| #define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528)) |
Definition at line 165 of file cortex-m4-def.h.
| #define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524)) |
Definition at line 164 of file cortex-m4-def.h.
| #define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000) |
Definition at line 144 of file cortex-m4-def.h.
| #define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC)) |
Definition at line 145 of file cortex-m4-def.h.
| #define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C)) |
Definition at line 162 of file cortex-m4-def.h.
| #define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400)) |
Definition at line 146 of file cortex-m4-def.h.
| #define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534)) |
Definition at line 168 of file cortex-m4-def.h.
| #define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500)) |
Definition at line 155 of file cortex-m4-def.h.
| #define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504)) |
Definition at line 156 of file cortex-m4-def.h.
| #define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508)) |
Definition at line 157 of file cortex-m4-def.h.
| #define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408)) |
Definition at line 148 of file cortex-m4-def.h.
| #define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C)) |
Definition at line 153 of file cortex-m4-def.h.
| #define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C)) |
Definition at line 149 of file cortex-m4-def.h.
| #define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410)) |
Definition at line 150 of file cortex-m4-def.h.
| #define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404)) |
Definition at line 147 of file cortex-m4-def.h.
| #define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520)) |
Definition at line 163 of file cortex-m4-def.h.
| #define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418)) |
Definition at line 152 of file cortex-m4-def.h.
| #define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C)) |
Definition at line 158 of file cortex-m4-def.h.
| #define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C)) |
Definition at line 166 of file cortex-m4-def.h.
| #define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514)) |
Definition at line 160 of file cortex-m4-def.h.
| #define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510)) |
Definition at line 159 of file cortex-m4-def.h.
| #define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414)) |
Definition at line 151 of file cortex-m4-def.h.
| #define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538)) |
Definition at line 169 of file cortex-m4-def.h.
| #define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518)) |
Definition at line 161 of file cortex-m4-def.h.
| #define GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530)) |
Definition at line 199 of file cortex-m4-def.h.
| #define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420)) |
Definition at line 186 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530)) |
Definition at line 1483 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420)) |
Definition at line 1470 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528)) |
Definition at line 1481 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524)) |
Definition at line 1480 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005A000) |
Definition at line 1459 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC)) |
Definition at line 1461 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C)) |
Definition at line 1478 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400)) |
Definition at line 1462 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534)) |
Definition at line 1484 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500)) |
Definition at line 1471 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504)) |
Definition at line 1472 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508)) |
Definition at line 1473 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408)) |
Definition at line 1464 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C)) |
Definition at line 1469 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C)) |
Definition at line 1465 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410)) |
Definition at line 1466 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404)) |
Definition at line 1463 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520)) |
Definition at line 1479 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418)) |
Definition at line 1468 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C)) |
Definition at line 1474 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C)) |
Definition at line 1482 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514)) |
Definition at line 1476 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510)) |
Definition at line 1475 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414)) |
Definition at line 1467 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538)) |
Definition at line 1485 of file cortex-m4-def.h.
| #define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518)) |
Definition at line 1477 of file cortex-m4-def.h.
| #define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528)) |
Definition at line 197 of file cortex-m4-def.h.
| #define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524)) |
Definition at line 196 of file cortex-m4-def.h.
| #define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000) |
Definition at line 176 of file cortex-m4-def.h.
| #define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC)) |
Definition at line 177 of file cortex-m4-def.h.
| #define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C)) |
Definition at line 194 of file cortex-m4-def.h.
| #define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400)) |
Definition at line 178 of file cortex-m4-def.h.
| #define GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534)) |
Definition at line 200 of file cortex-m4-def.h.
| #define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500)) |
Definition at line 187 of file cortex-m4-def.h.
| #define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504)) |
Definition at line 188 of file cortex-m4-def.h.
| #define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508)) |
Definition at line 189 of file cortex-m4-def.h.
| #define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408)) |
Definition at line 180 of file cortex-m4-def.h.
| #define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C)) |
Definition at line 185 of file cortex-m4-def.h.
| #define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C)) |
Definition at line 181 of file cortex-m4-def.h.
| #define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410)) |
Definition at line 182 of file cortex-m4-def.h.
| #define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404)) |
Definition at line 179 of file cortex-m4-def.h.
| #define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520)) |
Definition at line 195 of file cortex-m4-def.h.
| #define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418)) |
Definition at line 184 of file cortex-m4-def.h.
| #define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C)) |
Definition at line 190 of file cortex-m4-def.h.
| #define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C)) |
Definition at line 198 of file cortex-m4-def.h.
| #define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514)) |
Definition at line 192 of file cortex-m4-def.h.
| #define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510)) |
Definition at line 191 of file cortex-m4-def.h.
| #define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414)) |
Definition at line 183 of file cortex-m4-def.h.
| #define GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538)) |
Definition at line 201 of file cortex-m4-def.h.
| #define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518)) |
Definition at line 193 of file cortex-m4-def.h.
| #define GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530)) |
Definition at line 231 of file cortex-m4-def.h.
| #define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420)) |
Definition at line 218 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530)) |
Definition at line 1516 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420)) |
Definition at line 1503 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528)) |
Definition at line 1514 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524)) |
Definition at line 1513 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005B000) |
Definition at line 1492 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC)) |
Definition at line 1494 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C)) |
Definition at line 1511 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400)) |
Definition at line 1495 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534)) |
Definition at line 1517 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500)) |
Definition at line 1504 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504)) |
Definition at line 1505 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508)) |
Definition at line 1506 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408)) |
Definition at line 1497 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C)) |
Definition at line 1502 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C)) |
Definition at line 1498 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410)) |
Definition at line 1499 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404)) |
Definition at line 1496 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520)) |
Definition at line 1512 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418)) |
Definition at line 1501 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C)) |
Definition at line 1507 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C)) |
Definition at line 1515 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514)) |
Definition at line 1509 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510)) |
Definition at line 1508 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414)) |
Definition at line 1500 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538)) |
Definition at line 1518 of file cortex-m4-def.h.
| #define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518)) |
Definition at line 1510 of file cortex-m4-def.h.
| #define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528)) |
Definition at line 229 of file cortex-m4-def.h.
| #define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524)) |
Definition at line 228 of file cortex-m4-def.h.
| #define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000) |
Definition at line 208 of file cortex-m4-def.h.
| #define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC)) |
Definition at line 209 of file cortex-m4-def.h.
| #define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C)) |
Definition at line 226 of file cortex-m4-def.h.
| #define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400)) |
Definition at line 210 of file cortex-m4-def.h.
| #define GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534)) |
Definition at line 232 of file cortex-m4-def.h.
| #define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500)) |
Definition at line 219 of file cortex-m4-def.h.
| #define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504)) |
Definition at line 220 of file cortex-m4-def.h.
| #define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508)) |
Definition at line 221 of file cortex-m4-def.h.
| #define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408)) |
Definition at line 212 of file cortex-m4-def.h.
| #define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C)) |
Definition at line 217 of file cortex-m4-def.h.
| #define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C)) |
Definition at line 213 of file cortex-m4-def.h.
| #define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410)) |
Definition at line 214 of file cortex-m4-def.h.
| #define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404)) |
Definition at line 211 of file cortex-m4-def.h.
| #define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520)) |
Definition at line 227 of file cortex-m4-def.h.
| #define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418)) |
Definition at line 216 of file cortex-m4-def.h.
| #define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C)) |
Definition at line 222 of file cortex-m4-def.h.
| #define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C)) |
Definition at line 230 of file cortex-m4-def.h.
| #define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514)) |
Definition at line 224 of file cortex-m4-def.h.
| #define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510)) |
Definition at line 223 of file cortex-m4-def.h.
| #define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414)) |
Definition at line 215 of file cortex-m4-def.h.
| #define GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538)) |
Definition at line 233 of file cortex-m4-def.h.
| #define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518)) |
Definition at line 225 of file cortex-m4-def.h.
| #define GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530)) |
Definition at line 683 of file cortex-m4-def.h.
| #define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420)) |
Definition at line 670 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530)) |
Definition at line 1549 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420)) |
Definition at line 1536 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528)) |
Definition at line 1547 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524)) |
Definition at line 1546 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005C000) |
Definition at line 1525 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC)) |
Definition at line 1527 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C)) |
Definition at line 1544 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400)) |
Definition at line 1528 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534)) |
Definition at line 1550 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500)) |
Definition at line 1537 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504)) |
Definition at line 1538 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508)) |
Definition at line 1539 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408)) |
Definition at line 1530 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C)) |
Definition at line 1535 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C)) |
Definition at line 1531 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410)) |
Definition at line 1532 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404)) |
Definition at line 1529 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520)) |
Definition at line 1545 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418)) |
Definition at line 1534 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C)) |
Definition at line 1540 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C)) |
Definition at line 1548 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514)) |
Definition at line 1542 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510)) |
Definition at line 1541 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414)) |
Definition at line 1533 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538)) |
Definition at line 1551 of file cortex-m4-def.h.
| #define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518)) |
Definition at line 1543 of file cortex-m4-def.h.
| #define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528)) |
Definition at line 681 of file cortex-m4-def.h.
| #define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524)) |
Definition at line 680 of file cortex-m4-def.h.
| #define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000) |
Definition at line 660 of file cortex-m4-def.h.
| #define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC)) |
Definition at line 661 of file cortex-m4-def.h.
| #define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C)) |
Definition at line 678 of file cortex-m4-def.h.
| #define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400)) |
Definition at line 662 of file cortex-m4-def.h.
| #define GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534)) |
Definition at line 684 of file cortex-m4-def.h.
| #define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500)) |
Definition at line 671 of file cortex-m4-def.h.
| #define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504)) |
Definition at line 672 of file cortex-m4-def.h.
| #define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508)) |
Definition at line 673 of file cortex-m4-def.h.
| #define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408)) |
Definition at line 664 of file cortex-m4-def.h.
| #define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C)) |
Definition at line 669 of file cortex-m4-def.h.
| #define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C)) |
Definition at line 665 of file cortex-m4-def.h.
| #define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410)) |
Definition at line 666 of file cortex-m4-def.h.
| #define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404)) |
Definition at line 663 of file cortex-m4-def.h.
| #define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520)) |
Definition at line 679 of file cortex-m4-def.h.
| #define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418)) |
Definition at line 668 of file cortex-m4-def.h.
| #define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C)) |
Definition at line 674 of file cortex-m4-def.h.
| #define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C)) |
Definition at line 682 of file cortex-m4-def.h.
| #define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514)) |
Definition at line 676 of file cortex-m4-def.h.
| #define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510)) |
Definition at line 675 of file cortex-m4-def.h.
| #define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414)) |
Definition at line 667 of file cortex-m4-def.h.
| #define GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538)) |
Definition at line 685 of file cortex-m4-def.h.
| #define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518)) |
Definition at line 677 of file cortex-m4-def.h.
| #define GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530)) |
Definition at line 715 of file cortex-m4-def.h.
| #define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420)) |
Definition at line 702 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530)) |
Definition at line 1582 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420)) |
Definition at line 1569 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528)) |
Definition at line 1580 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524)) |
Definition at line 1579 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DATA_BITS_R ((volatile unsigned long *)0x4005D000) |
Definition at line 1558 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC)) |
Definition at line 1560 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C)) |
Definition at line 1577 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400)) |
Definition at line 1561 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534)) |
Definition at line 1583 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500)) |
Definition at line 1570 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504)) |
Definition at line 1571 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508)) |
Definition at line 1572 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408)) |
Definition at line 1563 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C)) |
Definition at line 1568 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C)) |
Definition at line 1564 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410)) |
Definition at line 1565 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404)) |
Definition at line 1562 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520)) |
Definition at line 1578 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418)) |
Definition at line 1567 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C)) |
Definition at line 1573 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C)) |
Definition at line 1581 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514)) |
Definition at line 1575 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510)) |
Definition at line 1574 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414)) |
Definition at line 1566 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538)) |
Definition at line 1584 of file cortex-m4-def.h.
| #define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518)) |
Definition at line 1576 of file cortex-m4-def.h.
| #define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528)) |
Definition at line 713 of file cortex-m4-def.h.
| #define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524)) |
Definition at line 712 of file cortex-m4-def.h.
| #define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000) |
Definition at line 692 of file cortex-m4-def.h.
| #define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC)) |
Definition at line 693 of file cortex-m4-def.h.
| #define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C)) |
Definition at line 710 of file cortex-m4-def.h.
| #define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400)) |
Definition at line 694 of file cortex-m4-def.h.
| #define GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534)) |
Definition at line 716 of file cortex-m4-def.h.
| #define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500)) |
Definition at line 703 of file cortex-m4-def.h.
| #define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504)) |
Definition at line 704 of file cortex-m4-def.h.
| #define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508)) |
Definition at line 705 of file cortex-m4-def.h.
| #define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408)) |
Definition at line 696 of file cortex-m4-def.h.
| #define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C)) |
Definition at line 701 of file cortex-m4-def.h.
| #define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C)) |
Definition at line 697 of file cortex-m4-def.h.
| #define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410)) |
Definition at line 698 of file cortex-m4-def.h.
| #define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404)) |
Definition at line 695 of file cortex-m4-def.h.
| #define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520)) |
Definition at line 711 of file cortex-m4-def.h.
| #define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418)) |
Definition at line 700 of file cortex-m4-def.h.
| #define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C)) |
Definition at line 706 of file cortex-m4-def.h.
| #define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C)) |
Definition at line 714 of file cortex-m4-def.h.
| #define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514)) |
Definition at line 708 of file cortex-m4-def.h.
| #define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510)) |
Definition at line 707 of file cortex-m4-def.h.
| #define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414)) |
Definition at line 699 of file cortex-m4-def.h.
| #define GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538)) |
Definition at line 717 of file cortex-m4-def.h.
| #define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518)) |
Definition at line 709 of file cortex-m4-def.h.
| #define GPIO_PUR_R_OFF (0x510UL) |
Definition at line 95 of file cortex-m4-def.h.
| #define GPIO_RIS_GPIO_M 0x000000FF |
Definition at line 2038 of file cortex-m4-def.h.
| #define GPIO_RIS_GPIO_S 0 |
Definition at line 2039 of file cortex-m4-def.h.
| #define GPIO_RIS_R_OFF (0x414UL) |
Definition at line 87 of file cortex-m4-def.h.
| #define GPIO_SI_R_OFF (0x538UL) |
Definition at line 105 of file cortex-m4-def.h.
| #define GPIO_SI_SUM 0x00000001 |
Definition at line 2074 of file cortex-m4-def.h.
| #define GPIO_SLR_R_OFF (0x518UL) |
Definition at line 97 of file cortex-m4-def.h.
| #define HIB_CTL_BATCHK 0x00000400 |
Definition at line 5914 of file cortex-m4-def.h.
| #define HIB_CTL_BATWKEN 0x00000200 |
Definition at line 5915 of file cortex-m4-def.h.
| #define HIB_CTL_CLK32EN 0x00000040 |
Definition at line 5918 of file cortex-m4-def.h.
| #define HIB_CTL_HIBREQ 0x00000002 |
Definition at line 5922 of file cortex-m4-def.h.
| #define HIB_CTL_LOWBATEN 0x00000020 |
Definition at line 5919 of file cortex-m4-def.h.
| #define HIB_CTL_OSCBYP 0x00010000 |
Definition at line 5907 of file cortex-m4-def.h.
| #define HIB_CTL_OSCDRV 0x00020000 |
Definition at line 5906 of file cortex-m4-def.h.
| #define HIB_CTL_PINWEN 0x00000010 |
Definition at line 5920 of file cortex-m4-def.h.
| #define HIB_CTL_R (*((volatile unsigned long *)0x400FC010)) |
Definition at line 1626 of file cortex-m4-def.h.
| #define HIB_CTL_RTCEN 0x00000001 |
Definition at line 5923 of file cortex-m4-def.h.
| #define HIB_CTL_RTCWEN 0x00000008 |
Definition at line 5921 of file cortex-m4-def.h.
| #define HIB_CTL_VABORT 0x00000080 |
Definition at line 5917 of file cortex-m4-def.h.
| #define HIB_CTL_VBATSEL_1_9V 0x00000000 |
Definition at line 5910 of file cortex-m4-def.h.
| #define HIB_CTL_VBATSEL_2_1V 0x00002000 |
Definition at line 5911 of file cortex-m4-def.h.
| #define HIB_CTL_VBATSEL_2_3V 0x00004000 |
Definition at line 5912 of file cortex-m4-def.h.
| #define HIB_CTL_VBATSEL_2_5V 0x00006000 |
Definition at line 5913 of file cortex-m4-def.h.
| #define HIB_CTL_VBATSEL_M 0x00006000 |
Definition at line 5908 of file cortex-m4-def.h.
| #define HIB_CTL_VDD3ON 0x00000100 |
Definition at line 5916 of file cortex-m4-def.h.
| #define HIB_CTL_WRC 0x80000000 |
Definition at line 5905 of file cortex-m4-def.h.
| #define HIB_DATA_R (*((volatile unsigned long *)0x400FC030)) |
Definition at line 1633 of file cortex-m4-def.h.
| #define HIB_DATA_RTD_M 0xFFFFFFFF |
Definition at line 6001 of file cortex-m4-def.h.
| #define HIB_DATA_RTD_S 0 |
Definition at line 6002 of file cortex-m4-def.h.
| #define HIB_IC_EXTW 0x00000008 |
Definition at line 5971 of file cortex-m4-def.h.
| #define HIB_IC_LOWBAT 0x00000004 |
Definition at line 5973 of file cortex-m4-def.h.
| #define HIB_IC_R (*((volatile unsigned long *)0x400FC020)) |
Definition at line 1630 of file cortex-m4-def.h.
| #define HIB_IC_RTCALT0 0x00000001 |
Definition at line 5975 of file cortex-m4-def.h.
| #define HIB_IC_WC 0x00000010 |
Definition at line 5969 of file cortex-m4-def.h.
| #define HIB_IM_EXTW 0x00000008 |
Definition at line 5932 of file cortex-m4-def.h.
| #define HIB_IM_LOWBAT 0x00000004 |
Definition at line 5933 of file cortex-m4-def.h.
| #define HIB_IM_R (*((volatile unsigned long *)0x400FC014)) |
Definition at line 1627 of file cortex-m4-def.h.
| #define HIB_IM_RTCALT0 0x00000001 |
Definition at line 5935 of file cortex-m4-def.h.
| #define HIB_IM_WC 0x00000010 |
Definition at line 5930 of file cortex-m4-def.h.
| #define HIB_MIS_EXTW 0x00000008 |
Definition at line 5957 of file cortex-m4-def.h.
| #define HIB_MIS_LOWBAT 0x00000004 |
Definition at line 5959 of file cortex-m4-def.h.
| #define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C)) |
Definition at line 1629 of file cortex-m4-def.h.
| #define HIB_MIS_RTCALT0 0x00000001 |
Definition at line 5961 of file cortex-m4-def.h.
| #define HIB_MIS_WC 0x00000010 |
Definition at line 5955 of file cortex-m4-def.h.
| #define HIB_RIS_EXTW 0x00000008 |
Definition at line 5944 of file cortex-m4-def.h.
| #define HIB_RIS_LOWBAT 0x00000004 |
Definition at line 5946 of file cortex-m4-def.h.
| #define HIB_RIS_R (*((volatile unsigned long *)0x400FC018)) |
Definition at line 1628 of file cortex-m4-def.h.
| #define HIB_RIS_RTCALT0 0x00000001 |
Definition at line 5948 of file cortex-m4-def.h.
| #define HIB_RIS_WC 0x00000010 |
Definition at line 5942 of file cortex-m4-def.h.
| #define HIB_RTCC_M 0xFFFFFFFF |
Definition at line 5881 of file cortex-m4-def.h.
| #define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000)) |
Definition at line 1623 of file cortex-m4-def.h.
| #define HIB_RTCC_S 0 |
Definition at line 5882 of file cortex-m4-def.h.
| #define HIB_RTCLD_M 0xFFFFFFFF |
Definition at line 5897 of file cortex-m4-def.h.
| #define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C)) |
Definition at line 1625 of file cortex-m4-def.h.
| #define HIB_RTCLD_S 0 |
Definition at line 5898 of file cortex-m4-def.h.
| #define HIB_RTCM0_M 0xFFFFFFFF |
Definition at line 5889 of file cortex-m4-def.h.
| #define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004)) |
Definition at line 1624 of file cortex-m4-def.h.
| #define HIB_RTCM0_S 0 |
Definition at line 5890 of file cortex-m4-def.h.
| #define HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028)) |
Definition at line 1632 of file cortex-m4-def.h.
| #define HIB_RTCSS_RTCSSC_M 0x00007FFF |
Definition at line 5992 of file cortex-m4-def.h.
| #define HIB_RTCSS_RTCSSC_S 0 |
Definition at line 5994 of file cortex-m4-def.h.
| #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 |
Definition at line 5991 of file cortex-m4-def.h.
| #define HIB_RTCSS_RTCSSM_S 16 |
Definition at line 5993 of file cortex-m4-def.h.
| #define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024)) |
Definition at line 1631 of file cortex-m4-def.h.
| #define HIB_RTCT_TRIM_M 0x0000FFFF |
Definition at line 5983 of file cortex-m4-def.h.
| #define HIB_RTCT_TRIM_S 0 |
Definition at line 5984 of file cortex-m4-def.h.
| #define I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C)) |
Definition at line 542 of file cortex-m4-def.h.
| #define I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024)) |
Definition at line 541 of file cortex-m4-def.h.
| #define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020)) |
Definition at line 540 of file cortex-m4-def.h.
| #define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004)) |
Definition at line 533 of file cortex-m4-def.h.
| #define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008)) |
Definition at line 534 of file cortex-m4-def.h.
| #define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C)) |
Definition at line 539 of file cortex-m4-def.h.
| #define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010)) |
Definition at line 536 of file cortex-m4-def.h.
| #define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018)) |
Definition at line 538 of file cortex-m4-def.h.
| #define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014)) |
Definition at line 537 of file cortex-m4-def.h.
| #define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000)) |
Definition at line 532 of file cortex-m4-def.h.
| #define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C)) |
Definition at line 535 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820)) |
Definition at line 557 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804)) |
Definition at line 550 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808)) |
Definition at line 551 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818)) |
Definition at line 555 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C)) |
Definition at line 552 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814)) |
Definition at line 554 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C)) |
Definition at line 556 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800)) |
Definition at line 549 of file cortex-m4-def.h.
| #define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810)) |
Definition at line 553 of file cortex-m4-def.h.
| #define I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C)) |
Definition at line 574 of file cortex-m4-def.h.
| #define I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024)) |
Definition at line 573 of file cortex-m4-def.h.
| #define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020)) |
Definition at line 572 of file cortex-m4-def.h.
| #define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004)) |
Definition at line 565 of file cortex-m4-def.h.
| #define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008)) |
Definition at line 566 of file cortex-m4-def.h.
| #define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C)) |
Definition at line 571 of file cortex-m4-def.h.
| #define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010)) |
Definition at line 568 of file cortex-m4-def.h.
| #define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018)) |
Definition at line 570 of file cortex-m4-def.h.
| #define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014)) |
Definition at line 569 of file cortex-m4-def.h.
| #define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000)) |
Definition at line 564 of file cortex-m4-def.h.
| #define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C)) |
Definition at line 567 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820)) |
Definition at line 589 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804)) |
Definition at line 582 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808)) |
Definition at line 583 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818)) |
Definition at line 587 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C)) |
Definition at line 584 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814)) |
Definition at line 586 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C)) |
Definition at line 588 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800)) |
Definition at line 581 of file cortex-m4-def.h.
| #define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810)) |
Definition at line 585 of file cortex-m4-def.h.
| #define I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C)) |
Definition at line 606 of file cortex-m4-def.h.
| #define I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024)) |
Definition at line 605 of file cortex-m4-def.h.
| #define I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020)) |
Definition at line 604 of file cortex-m4-def.h.
| #define I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004)) |
Definition at line 597 of file cortex-m4-def.h.
| #define I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008)) |
Definition at line 598 of file cortex-m4-def.h.
| #define I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C)) |
Definition at line 603 of file cortex-m4-def.h.
| #define I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010)) |
Definition at line 600 of file cortex-m4-def.h.
| #define I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018)) |
Definition at line 602 of file cortex-m4-def.h.
| #define I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014)) |
Definition at line 601 of file cortex-m4-def.h.
| #define I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000)) |
Definition at line 596 of file cortex-m4-def.h.
| #define I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C)) |
Definition at line 599 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820)) |
Definition at line 621 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804)) |
Definition at line 614 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808)) |
Definition at line 615 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818)) |
Definition at line 619 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C)) |
Definition at line 616 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814)) |
Definition at line 618 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C)) |
Definition at line 620 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800)) |
Definition at line 613 of file cortex-m4-def.h.
| #define I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810)) |
Definition at line 617 of file cortex-m4-def.h.
| #define I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C)) |
Definition at line 638 of file cortex-m4-def.h.
| #define I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024)) |
Definition at line 637 of file cortex-m4-def.h.
| #define I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020)) |
Definition at line 636 of file cortex-m4-def.h.
| #define I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004)) |
Definition at line 629 of file cortex-m4-def.h.
| #define I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008)) |
Definition at line 630 of file cortex-m4-def.h.
| #define I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C)) |
Definition at line 635 of file cortex-m4-def.h.
| #define I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010)) |
Definition at line 632 of file cortex-m4-def.h.
| #define I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018)) |
Definition at line 634 of file cortex-m4-def.h.
| #define I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014)) |
Definition at line 633 of file cortex-m4-def.h.
| #define I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000)) |
Definition at line 628 of file cortex-m4-def.h.
| #define I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C)) |
Definition at line 631 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820)) |
Definition at line 653 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804)) |
Definition at line 646 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808)) |
Definition at line 647 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818)) |
Definition at line 651 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C)) |
Definition at line 648 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814)) |
Definition at line 650 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C)) |
Definition at line 652 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800)) |
Definition at line 645 of file cortex-m4-def.h.
| #define I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810)) |
Definition at line 649 of file cortex-m4-def.h.
| #define I2C_MBMON_SCL 0x00000001 |
Definition at line 2876 of file cortex-m4-def.h.
| #define I2C_MBMON_SDA 0x00000002 |
Definition at line 2875 of file cortex-m4-def.h.
| #define I2C_MCLKOCNT_CNTL_M 0x000000FF |
Definition at line 2867 of file cortex-m4-def.h.
| #define I2C_MCLKOCNT_CNTL_S 0 |
Definition at line 2868 of file cortex-m4-def.h.
| #define I2C_MCR_LPBK 0x00000001 |
Definition at line 2852 of file cortex-m4-def.h.
| #define I2C_MCR_MFE 0x00000010 |
Definition at line 2851 of file cortex-m4-def.h.
| #define I2C_MCR_SFE 0x00000020 |
Definition at line 2850 of file cortex-m4-def.h.
| #define I2C_MCS_ACK 0x00000008 |
Definition at line 2728 of file cortex-m4-def.h.
| #define I2C_MCS_ADRACK 0x00000004 |
Definition at line 2730 of file cortex-m4-def.h.
| #define I2C_MCS_ARBLST 0x00000010 |
Definition at line 2726 of file cortex-m4-def.h.
| #define I2C_MCS_BUSBSY 0x00000040 |
Definition at line 2724 of file cortex-m4-def.h.
| #define I2C_MCS_BUSY 0x00000001 |
Definition at line 2735 of file cortex-m4-def.h.
| #define I2C_MCS_CLKTO 0x00000080 |
Definition at line 2723 of file cortex-m4-def.h.
| #define I2C_MCS_DATACK 0x00000008 |
Definition at line 2729 of file cortex-m4-def.h.
| #define I2C_MCS_ERROR 0x00000002 |
Definition at line 2732 of file cortex-m4-def.h.
| #define I2C_MCS_HS 0x00000010 |
Definition at line 2727 of file cortex-m4-def.h.
| #define I2C_MCS_IDLE 0x00000020 |
Definition at line 2725 of file cortex-m4-def.h.
| #define I2C_MCS_RUN 0x00000001 |
Definition at line 2734 of file cortex-m4-def.h.
| #define I2C_MCS_START 0x00000002 |
Definition at line 2733 of file cortex-m4-def.h.
| #define I2C_MCS_STOP 0x00000004 |
Definition at line 2731 of file cortex-m4-def.h.
| #define I2C_MDR_DATA_M 0x000000FF |
Definition at line 2750 of file cortex-m4-def.h.
| #define I2C_MDR_DATA_S 0 |
Definition at line 2751 of file cortex-m4-def.h.
| #define I2C_MICR_CLKIC 0x00000002 |
Definition at line 2833 of file cortex-m4-def.h.
| #define I2C_MICR_IC 0x00000001 |
Definition at line 2834 of file cortex-m4-def.h.
| #define I2C_MIMR_CLKIM 0x00000002 |
Definition at line 2787 of file cortex-m4-def.h.
| #define I2C_MIMR_IM 0x00000001 |
Definition at line 2788 of file cortex-m4-def.h.
| #define I2C_MMIS_CLKMIS 0x00000002 |
Definition at line 2824 of file cortex-m4-def.h.
| #define I2C_MMIS_MIS 0x00000001 |
Definition at line 2826 of file cortex-m4-def.h.
| #define I2C_MRIS_CLKRIS 0x00000002 |
Definition at line 2795 of file cortex-m4-def.h.
| #define I2C_MRIS_RIS 0x00000001 |
Definition at line 2797 of file cortex-m4-def.h.
| #define I2C_MSA_RS 0x00000001 |
Definition at line 2696 of file cortex-m4-def.h.
| #define I2C_MSA_SA_M 0x000000FE |
Definition at line 2695 of file cortex-m4-def.h.
| #define I2C_MSA_SA_S 1 |
Definition at line 2697 of file cortex-m4-def.h.
| #define I2C_MTPR_HS 0x00000080 |
Definition at line 2758 of file cortex-m4-def.h.
| #define I2C_MTPR_TPR_M 0x0000007F |
Definition at line 2759 of file cortex-m4-def.h.
| #define I2C_MTPR_TPR_S 0 |
Definition at line 2760 of file cortex-m4-def.h.
| #define I2C_PC_HS 0x00000001 |
Definition at line 2890 of file cortex-m4-def.h.
| #define I2C_PP_HS 0x00000001 |
Definition at line 2883 of file cortex-m4-def.h.
| #define I2C_SACKCTL_ACKOEN 0x00000001 |
Definition at line 2860 of file cortex-m4-def.h.
| #define I2C_SACKCTL_ACKOVAL 0x00000002 |
Definition at line 2859 of file cortex-m4-def.h.
| #define I2C_SCSR_DA 0x00000001 |
Definition at line 2715 of file cortex-m4-def.h.
| #define I2C_SCSR_FBR 0x00000004 |
Definition at line 2713 of file cortex-m4-def.h.
| #define I2C_SCSR_OAR2SEL 0x00000008 |
Definition at line 2712 of file cortex-m4-def.h.
| #define I2C_SCSR_RREQ 0x00000001 |
Definition at line 2716 of file cortex-m4-def.h.
| #define I2C_SCSR_TREQ 0x00000002 |
Definition at line 2714 of file cortex-m4-def.h.
| #define I2C_SDR_DATA_M 0x000000FF |
Definition at line 2742 of file cortex-m4-def.h.
| #define I2C_SDR_DATA_S 0 |
Definition at line 2743 of file cortex-m4-def.h.
| #define I2C_SICR_DATAIC 0x00000001 |
Definition at line 2817 of file cortex-m4-def.h.
| #define I2C_SICR_STARTIC 0x00000002 |
Definition at line 2816 of file cortex-m4-def.h.
| #define I2C_SICR_STOPIC 0x00000004 |
Definition at line 2815 of file cortex-m4-def.h.
| #define I2C_SIMR_DATAIM 0x00000001 |
Definition at line 2769 of file cortex-m4-def.h.
| #define I2C_SIMR_STARTIM 0x00000002 |
Definition at line 2768 of file cortex-m4-def.h.
| #define I2C_SIMR_STOPIM 0x00000004 |
Definition at line 2767 of file cortex-m4-def.h.
| #define I2C_SMIS_DATAMIS 0x00000001 |
Definition at line 2808 of file cortex-m4-def.h.
| #define I2C_SMIS_STARTMIS 0x00000002 |
Definition at line 2806 of file cortex-m4-def.h.
| #define I2C_SMIS_STOPMIS 0x00000004 |
Definition at line 2804 of file cortex-m4-def.h.
| #define I2C_SOAR2_OAR2_M 0x0000007F |
Definition at line 2842 of file cortex-m4-def.h.
| #define I2C_SOAR2_OAR2_S 0 |
Definition at line 2843 of file cortex-m4-def.h.
| #define I2C_SOAR2_OAR2EN 0x00000080 |
Definition at line 2841 of file cortex-m4-def.h.
| #define I2C_SOAR_OAR_M 0x0000007F |
Definition at line 2704 of file cortex-m4-def.h.
| #define I2C_SOAR_OAR_S 0 |
Definition at line 2705 of file cortex-m4-def.h.
| #define I2C_SRIS_DATARIS 0x00000001 |
Definition at line 2780 of file cortex-m4-def.h.
| #define I2C_SRIS_STARTRIS 0x00000002 |
Definition at line 2778 of file cortex-m4-def.h.
| #define I2C_SRIS_STOPRIS 0x00000004 |
Definition at line 2776 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT0 0x00000001 |
Definition at line 8972 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT1 0x00000002 |
Definition at line 8973 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT10 0x00000400 |
Definition at line 8982 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT11 0x00000800 |
Definition at line 8983 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT12 0x00001000 |
Definition at line 8984 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT13 0x00002000 |
Definition at line 8985 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT14 0x00004000 |
Definition at line 8986 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT15 0x00008000 |
Definition at line 8987 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT16 0x00010000 |
Definition at line 8988 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT17 0x00020000 |
Definition at line 8989 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT18 0x00040000 |
Definition at line 8990 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT19 0x00080000 |
Definition at line 8991 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT2 0x00000004 |
Definition at line 8974 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT20 0x00100000 |
Definition at line 8992 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT21 0x00200000 |
Definition at line 8993 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT22 0x00400000 |
Definition at line 8994 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT23 0x00800000 |
Definition at line 8995 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT24 0x01000000 |
Definition at line 8996 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT25 0x02000000 |
Definition at line 8997 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT26 0x04000000 |
Definition at line 8998 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT27 0x08000000 |
Definition at line 8999 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT28 0x10000000 |
Definition at line 9000 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT29 0x20000000 |
Definition at line 9001 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT3 0x00000008 |
Definition at line 8975 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT30 0x40000000 |
Definition at line 9002 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT31 0x80000000 |
Definition at line 9003 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT4 0x00000010 |
Definition at line 8976 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT5 0x00000020 |
Definition at line 8977 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT6 0x00000040 |
Definition at line 8978 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT7 0x00000080 |
Definition at line 8979 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT8 0x00000100 |
Definition at line 8980 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT9 0x00000200 |
Definition at line 8981 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF |
Definition at line 8971 of file cortex-m4-def.h.
| #define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300)) |
Definition at line 1885 of file cortex-m4-def.h.
| #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF |
Definition at line 9010 of file cortex-m4-def.h.
| #define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304)) |
Definition at line 1886 of file cortex-m4-def.h.
| #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF |
Definition at line 9017 of file cortex-m4-def.h.
| #define NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308)) |
Definition at line 1887 of file cortex-m4-def.h.
| #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF |
Definition at line 9024 of file cortex-m4-def.h.
| #define NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C)) |
Definition at line 1888 of file cortex-m4-def.h.
| #define NVIC_ACTIVE4_INT_M 0x000007FF |
Definition at line 9031 of file cortex-m4-def.h.
| #define NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310)) |
Definition at line 1889 of file cortex-m4-def.h.
| #define NVIC_ACTLR_DISFOLD 0x00000004 |
Definition at line 8632 of file cortex-m4-def.h.
| #define NVIC_ACTLR_DISFPCA 0x00000100 |
Definition at line 8631 of file cortex-m4-def.h.
| #define NVIC_ACTLR_DISMCYC 0x00000001 |
Definition at line 8634 of file cortex-m4-def.h.
| #define NVIC_ACTLR_DISOOFP 0x00000200 |
Definition at line 8629 of file cortex-m4-def.h.
| #define NVIC_ACTLR_DISWBUF 0x00000002 |
Definition at line 8633 of file cortex-m4-def.h.
| #define NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008)) |
Definition at line 1860 of file cortex-m4-def.h.
| #define NVIC_APINT_ENDIANESS 0x00008000 |
Definition at line 9593 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_0_8 0x00000700 |
Definition at line 9602 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_1_7 0x00000600 |
Definition at line 9601 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_2_6 0x00000500 |
Definition at line 9600 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_3_5 0x00000400 |
Definition at line 9599 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_4_4 0x00000300 |
Definition at line 9598 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_5_3 0x00000200 |
Definition at line 9597 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_6_2 0x00000100 |
Definition at line 9596 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_7_1 0x00000000 |
Definition at line 9595 of file cortex-m4-def.h.
| #define NVIC_APINT_PRIGROUP_M 0x00000700 |
Definition at line 9594 of file cortex-m4-def.h.
| #define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C)) |
Definition at line 1928 of file cortex-m4-def.h.
| #define NVIC_APINT_SYSRESETREQ 0x00000004 |
Definition at line 9603 of file cortex-m4-def.h.
| #define NVIC_APINT_VECT_CLR_ACT 0x00000002 |
Definition at line 9604 of file cortex-m4-def.h.
| #define NVIC_APINT_VECT_RESET 0x00000001 |
Definition at line 9605 of file cortex-m4-def.h.
| #define NVIC_APINT_VECTKEY 0x05FA0000 |
Definition at line 9592 of file cortex-m4-def.h.
| #define NVIC_APINT_VECTKEY_M 0xFFFF0000 |
Definition at line 9591 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_BASE_THR 0x00000001 |
Definition at line 9628 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 |
Definition at line 9623 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_DIV0 0x00000010 |
Definition at line 9625 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 |
Definition at line 9627 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14)) |
Definition at line 1930 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_STKALIGN 0x00000200 |
Definition at line 9621 of file cortex-m4-def.h.
| #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 |
Definition at line 9626 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP10_DIS 0x00000000 |
Definition at line 9766 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP10_FULL 0x00300000 |
Definition at line 9768 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP10_M 0x00300000 |
Definition at line 9764 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP10_PRIV 0x00100000 |
Definition at line 9767 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP11_DIS 0x00000000 |
Definition at line 9761 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP11_FULL 0x00C00000 |
Definition at line 9763 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP11_M 0x00C00000 |
Definition at line 9759 of file cortex-m4-def.h.
| #define NVIC_CPAC_CP11_PRIV 0x00400000 |
Definition at line 9762 of file cortex-m4-def.h.
| #define NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88)) |
Definition at line 1940 of file cortex-m4-def.h.
| #define NVIC_CPUID_CON_M 0x000F0000 |
Definition at line 9539 of file cortex-m4-def.h.
| #define NVIC_CPUID_IMP_ARM 0x41000000 |
Definition at line 9537 of file cortex-m4-def.h.
| #define NVIC_CPUID_IMP_M 0xFF000000 |
Definition at line 9536 of file cortex-m4-def.h.
| #define NVIC_CPUID_PARTNO_CM4 0x0000C240 |
Definition at line 9541 of file cortex-m4-def.h.
| #define NVIC_CPUID_PARTNO_M 0x0000FFF0 |
Definition at line 9540 of file cortex-m4-def.h.
| #define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00)) |
Definition at line 1925 of file cortex-m4-def.h.
| #define NVIC_CPUID_REV_M 0x0000000F |
Definition at line 9542 of file cortex-m4-def.h.
| #define NVIC_CPUID_VAR_M 0x00F00000 |
Definition at line 9538 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 |
Definition at line 9933 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_C_HALT 0x00000002 |
Definition at line 9932 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 |
Definition at line 9930 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_C_SNAPSTALL 0x00000020 |
Definition at line 9928 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_C_STEP 0x00000004 |
Definition at line 9931 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 |
Definition at line 9918 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 |
Definition at line 9917 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0)) |
Definition at line 1952 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_HALT 0x00020000 |
Definition at line 9926 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 |
Definition at line 9924 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 |
Definition at line 9927 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_RESET_ST 0x02000000 |
Definition at line 9919 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_RETIRE_ST 0x01000000 |
Definition at line 9921 of file cortex-m4-def.h.
| #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 |
Definition at line 9925 of file cortex-m4-def.h.
| #define NVIC_DBG_DATA_M 0xFFFFFFFF |
Definition at line 9969 of file cortex-m4-def.h.
| #define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8)) |
Definition at line 1954 of file cortex-m4-def.h.
| #define NVIC_DBG_DATA_S 0 |
Definition at line 9970 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_BUSERR 0x00000100 |
Definition at line 9979 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_CHKERR 0x00000040 |
Definition at line 9981 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_HARDERR 0x00000400 |
Definition at line 9977 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_INTERR 0x00000200 |
Definition at line 9978 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_MMERR 0x00000010 |
Definition at line 9983 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_NOCPERR 0x00000020 |
Definition at line 9982 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC)) |
Definition at line 1955 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_RESET 0x00000008 |
Definition at line 9984 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 |
Definition at line 9985 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_RSTPENDING 0x00000002 |
Definition at line 9986 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_RSTVCATCH 0x00000001 |
Definition at line 9987 of file cortex-m4-def.h.
| #define NVIC_DBG_INT_STATERR 0x00000080 |
Definition at line 9980 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4)) |
Definition at line 1953 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_CFBP 0x00000014 |
Definition at line 9962 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_DSP 0x00000013 |
Definition at line 9961 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 |
Definition at line 9958 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_MSP 0x00000011 |
Definition at line 9959 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_PSP 0x00000012 |
Definition at line 9960 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R0 0x00000000 |
Definition at line 9942 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R1 0x00000001 |
Definition at line 9943 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R10 0x0000000A |
Definition at line 9952 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R11 0x0000000B |
Definition at line 9953 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R12 0x0000000C |
Definition at line 9954 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R13 0x0000000D |
Definition at line 9955 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R14 0x0000000E |
Definition at line 9956 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R15 0x0000000F |
Definition at line 9957 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R2 0x00000002 |
Definition at line 9944 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R3 0x00000003 |
Definition at line 9945 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R4 0x00000004 |
Definition at line 9946 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R5 0x00000005 |
Definition at line 9947 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R6 0x00000006 |
Definition at line 9948 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R7 0x00000007 |
Definition at line 9949 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R8 0x00000008 |
Definition at line 9950 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_R9 0x00000009 |
Definition at line 9951 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F |
Definition at line 9941 of file cortex-m4-def.h.
| #define NVIC_DBG_XFER_REG_WNR 0x00010000 |
Definition at line 9940 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_BKPT 0x00000002 |
Definition at line 9734 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 |
Definition at line 9733 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 |
Definition at line 9731 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_HALTED 0x00000001 |
Definition at line 9735 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30)) |
Definition at line 1937 of file cortex-m4-def.h.
| #define NVIC_DEBUG_STAT_VCATCH 0x00000008 |
Definition at line 9732 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT0 0x00000001 |
Definition at line 8747 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT1 0x00000002 |
Definition at line 8748 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT10 0x00000400 |
Definition at line 8757 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT11 0x00000800 |
Definition at line 8758 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT12 0x00001000 |
Definition at line 8759 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT13 0x00002000 |
Definition at line 8760 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT14 0x00004000 |
Definition at line 8761 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT15 0x00008000 |
Definition at line 8762 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT16 0x00010000 |
Definition at line 8763 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT17 0x00020000 |
Definition at line 8764 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT18 0x00040000 |
Definition at line 8765 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT19 0x00080000 |
Definition at line 8766 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT2 0x00000004 |
Definition at line 8749 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT20 0x00100000 |
Definition at line 8767 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT21 0x00200000 |
Definition at line 8768 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT22 0x00400000 |
Definition at line 8769 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT23 0x00800000 |
Definition at line 8770 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT24 0x01000000 |
Definition at line 8771 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT25 0x02000000 |
Definition at line 8772 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT26 0x04000000 |
Definition at line 8773 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT27 0x08000000 |
Definition at line 8774 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT28 0x10000000 |
Definition at line 8775 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT29 0x20000000 |
Definition at line 8776 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT3 0x00000008 |
Definition at line 8750 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT30 0x40000000 |
Definition at line 8777 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT31 0x80000000 |
Definition at line 8778 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT4 0x00000010 |
Definition at line 8751 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT5 0x00000020 |
Definition at line 8752 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT6 0x00000040 |
Definition at line 8753 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT7 0x00000080 |
Definition at line 8754 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT8 0x00000100 |
Definition at line 8755 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT9 0x00000200 |
Definition at line 8756 of file cortex-m4-def.h.
| #define NVIC_DIS0_INT_M 0xFFFFFFFF |
Definition at line 8746 of file cortex-m4-def.h.
| #define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180)) |
Definition at line 1870 of file cortex-m4-def.h.
| #define NVIC_DIS1_INT_M 0xFFFFFFFF |
Definition at line 8785 of file cortex-m4-def.h.
| #define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184)) |
Definition at line 1871 of file cortex-m4-def.h.
| #define NVIC_DIS2_INT_M 0xFFFFFFFF |
Definition at line 8792 of file cortex-m4-def.h.
| #define NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188)) |
Definition at line 1872 of file cortex-m4-def.h.
| #define NVIC_DIS3_INT_M 0xFFFFFFFF |
Definition at line 8799 of file cortex-m4-def.h.
| #define NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C)) |
Definition at line 1873 of file cortex-m4-def.h.
| #define NVIC_DIS4_INT_M 0x000007FF |
Definition at line 8806 of file cortex-m4-def.h.
| #define NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190)) |
Definition at line 1874 of file cortex-m4-def.h.
| #define NVIC_EN0_INT0 0x00000001 |
Definition at line 8680 of file cortex-m4-def.h.
| #define NVIC_EN0_INT1 0x00000002 |
Definition at line 8681 of file cortex-m4-def.h.
| #define NVIC_EN0_INT10 0x00000400 |
Definition at line 8690 of file cortex-m4-def.h.
| #define NVIC_EN0_INT11 0x00000800 |
Definition at line 8691 of file cortex-m4-def.h.
| #define NVIC_EN0_INT12 0x00001000 |
Definition at line 8692 of file cortex-m4-def.h.
| #define NVIC_EN0_INT13 0x00002000 |
Definition at line 8693 of file cortex-m4-def.h.
| #define NVIC_EN0_INT14 0x00004000 |
Definition at line 8694 of file cortex-m4-def.h.
| #define NVIC_EN0_INT15 0x00008000 |
Definition at line 8695 of file cortex-m4-def.h.
| #define NVIC_EN0_INT16 0x00010000 |
Definition at line 8696 of file cortex-m4-def.h.
| #define NVIC_EN0_INT17 0x00020000 |
Definition at line 8697 of file cortex-m4-def.h.
| #define NVIC_EN0_INT18 0x00040000 |
Definition at line 8698 of file cortex-m4-def.h.
| #define NVIC_EN0_INT19 0x00080000 |
Definition at line 8699 of file cortex-m4-def.h.
| #define NVIC_EN0_INT2 0x00000004 |
Definition at line 8682 of file cortex-m4-def.h.
| #define NVIC_EN0_INT20 0x00100000 |
Definition at line 8700 of file cortex-m4-def.h.
| #define NVIC_EN0_INT21 0x00200000 |
Definition at line 8701 of file cortex-m4-def.h.
| #define NVIC_EN0_INT22 0x00400000 |
Definition at line 8702 of file cortex-m4-def.h.
| #define NVIC_EN0_INT23 0x00800000 |
Definition at line 8703 of file cortex-m4-def.h.
| #define NVIC_EN0_INT24 0x01000000 |
Definition at line 8704 of file cortex-m4-def.h.
| #define NVIC_EN0_INT25 0x02000000 |
Definition at line 8705 of file cortex-m4-def.h.
| #define NVIC_EN0_INT26 0x04000000 |
Definition at line 8706 of file cortex-m4-def.h.
| #define NVIC_EN0_INT27 0x08000000 |
Definition at line 8707 of file cortex-m4-def.h.
| #define NVIC_EN0_INT28 0x10000000 |
Definition at line 8708 of file cortex-m4-def.h.
| #define NVIC_EN0_INT29 0x20000000 |
Definition at line 8709 of file cortex-m4-def.h.
| #define NVIC_EN0_INT3 0x00000008 |
Definition at line 8683 of file cortex-m4-def.h.
| #define NVIC_EN0_INT30 0x40000000 |
Definition at line 8710 of file cortex-m4-def.h.
| #define NVIC_EN0_INT31 0x80000000 |
Definition at line 8711 of file cortex-m4-def.h.
| #define NVIC_EN0_INT4 0x00000010 |
Definition at line 8684 of file cortex-m4-def.h.
| #define NVIC_EN0_INT5 0x00000020 |
Definition at line 8685 of file cortex-m4-def.h.
| #define NVIC_EN0_INT6 0x00000040 |
Definition at line 8686 of file cortex-m4-def.h.
| #define NVIC_EN0_INT7 0x00000080 |
Definition at line 8687 of file cortex-m4-def.h.
| #define NVIC_EN0_INT8 0x00000100 |
Definition at line 8688 of file cortex-m4-def.h.
| #define NVIC_EN0_INT9 0x00000200 |
Definition at line 8689 of file cortex-m4-def.h.
| #define NVIC_EN0_INT_M 0xFFFFFFFF |
Definition at line 8679 of file cortex-m4-def.h.
| #define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) |
Definition at line 1865 of file cortex-m4-def.h.
| #define NVIC_EN1_INT_M 0xFFFFFFFF |
Definition at line 8718 of file cortex-m4-def.h.
| #define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104)) |
Definition at line 1866 of file cortex-m4-def.h.
| #define NVIC_EN2_INT_M 0xFFFFFFFF |
Definition at line 8725 of file cortex-m4-def.h.
| #define NVIC_EN2_R (*((volatile unsigned long *)0xE000E108)) |
Definition at line 1867 of file cortex-m4-def.h.
| #define NVIC_EN3_INT_M 0xFFFFFFFF |
Definition at line 8732 of file cortex-m4-def.h.
| #define NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C)) |
Definition at line 1868 of file cortex-m4-def.h.
| #define NVIC_EN4_INT_M 0x000007FF |
Definition at line 8739 of file cortex-m4-def.h.
| #define NVIC_EN4_R (*((volatile unsigned long *)0xE000E110)) |
Definition at line 1869 of file cortex-m4-def.h.
| #define NVIC_FAULT_ADDR_M 0xFFFFFFFF |
Definition at line 9751 of file cortex-m4-def.h.
| #define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38)) |
Definition at line 1939 of file cortex-m4-def.h.
| #define NVIC_FAULT_ADDR_S 0 |
Definition at line 9752 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_BFARV 0x00008000 |
Definition at line 9697 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_BLSPERR 0x00002000 |
Definition at line 9698 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_BSTKE 0x00001000 |
Definition at line 9700 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_BUSTKE 0x00000800 |
Definition at line 9701 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_DERR 0x00000002 |
Definition at line 9712 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_DIV0 0x02000000 |
Definition at line 9690 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_IBUS 0x00000100 |
Definition at line 9704 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_IERR 0x00000001 |
Definition at line 9713 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_IMPRE 0x00000400 |
Definition at line 9702 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_INVPC 0x00040000 |
Definition at line 9693 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_INVSTAT 0x00020000 |
Definition at line 9694 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_MLSPERR 0x00000020 |
Definition at line 9707 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_MMARV 0x00000080 |
Definition at line 9705 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_MSTKE 0x00000010 |
Definition at line 9710 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_MUSTKE 0x00000008 |
Definition at line 9711 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_NOCP 0x00080000 |
Definition at line 9692 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_PRECISE 0x00000200 |
Definition at line 9703 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28)) |
Definition at line 1935 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_UNALIGN 0x01000000 |
Definition at line 9691 of file cortex-m4-def.h.
| #define NVIC_FAULT_STAT_UNDEF 0x00010000 |
Definition at line 9695 of file cortex-m4-def.h.
| #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 |
Definition at line 10018 of file cortex-m4-def.h.
| #define NVIC_FPCA_ADDRESS_S 3 |
Definition at line 10019 of file cortex-m4-def.h.
| #define NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38)) |
Definition at line 1958 of file cortex-m4-def.h.
| #define NVIC_FPCC_ASPEN 0x80000000 |
Definition at line 10002 of file cortex-m4-def.h.
| #define NVIC_FPCC_BFRDY 0x00000040 |
Definition at line 10006 of file cortex-m4-def.h.
| #define NVIC_FPCC_HFRDY 0x00000010 |
Definition at line 10008 of file cortex-m4-def.h.
| #define NVIC_FPCC_LSPACT 0x00000001 |
Definition at line 10011 of file cortex-m4-def.h.
| #define NVIC_FPCC_LSPEN 0x40000000 |
Definition at line 10004 of file cortex-m4-def.h.
| #define NVIC_FPCC_MMRDY 0x00000020 |
Definition at line 10007 of file cortex-m4-def.h.
| #define NVIC_FPCC_MONRDY 0x00000100 |
Definition at line 10005 of file cortex-m4-def.h.
| #define NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34)) |
Definition at line 1957 of file cortex-m4-def.h.
| #define NVIC_FPCC_THREAD 0x00000008 |
Definition at line 10009 of file cortex-m4-def.h.
| #define NVIC_FPCC_USER 0x00000002 |
Definition at line 10010 of file cortex-m4-def.h.
| #define NVIC_FPDSC_AHP 0x04000000 |
Definition at line 10026 of file cortex-m4-def.h.
| #define NVIC_FPDSC_DN 0x02000000 |
Definition at line 10027 of file cortex-m4-def.h.
| #define NVIC_FPDSC_FZ 0x01000000 |
Definition at line 10028 of file cortex-m4-def.h.
| #define NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C)) |
Definition at line 1959 of file cortex-m4-def.h.
| #define NVIC_FPDSC_RMODE_M 0x00C00000 |
Definition at line 10029 of file cortex-m4-def.h.
| #define NVIC_FPDSC_RMODE_RM 0x00800000 |
Definition at line 10033 of file cortex-m4-def.h.
| #define NVIC_FPDSC_RMODE_RN 0x00000000 |
Definition at line 10030 of file cortex-m4-def.h.
| #define NVIC_FPDSC_RMODE_RP 0x00400000 |
Definition at line 10031 of file cortex-m4-def.h.
| #define NVIC_FPDSC_RMODE_RZ 0x00C00000 |
Definition at line 10035 of file cortex-m4-def.h.
| #define NVIC_HFAULT_STAT_DBG 0x80000000 |
Definition at line 9721 of file cortex-m4-def.h.
| #define NVIC_HFAULT_STAT_FORCED 0x40000000 |
Definition at line 9722 of file cortex-m4-def.h.
| #define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C)) |
Definition at line 1936 of file cortex-m4-def.h.
| #define NVIC_HFAULT_STAT_VECT 0x00000002 |
Definition at line 9723 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_ISR_PEND 0x00400000 |
Definition at line 9555 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_ISR_PRE 0x00800000 |
Definition at line 9554 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_NMI_SET 0x80000000 |
Definition at line 9549 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_PEND_SV 0x10000000 |
Definition at line 9550 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 |
Definition at line 9553 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_PENDSTSET 0x04000000 |
Definition at line 9552 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04)) |
Definition at line 1926 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_RET_BASE 0x00000800 |
Definition at line 9573 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 |
Definition at line 9551 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF |
Definition at line 9574 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_ACT_S 0 |
Definition at line 9575 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_BUS 0x00005000 |
Definition at line 9563 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_HARD 0x00003000 |
Definition at line 9559 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 |
Definition at line 9556 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_MEM 0x00004000 |
Definition at line 9561 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_NMI 0x00002000 |
Definition at line 9557 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_PNDSV 0x0000E000 |
Definition at line 9569 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_SVC 0x0000B000 |
Definition at line 9567 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_TICK 0x0000F000 |
Definition at line 9571 of file cortex-m4-def.h.
| #define NVIC_INT_CTRL_VEC_PEN_USG 0x00006000 |
Definition at line 9565 of file cortex-m4-def.h.
| #define NVIC_INT_TYPE_LINES_M 0x0000001F |
Definition at line 8621 of file cortex-m4-def.h.
| #define NVIC_INT_TYPE_LINES_S 0 |
Definition at line 8622 of file cortex-m4-def.h.
| #define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004)) |
Definition at line 1859 of file cortex-m4-def.h.
| #define NVIC_MM_ADDR_M 0xFFFFFFFF |
Definition at line 9742 of file cortex-m4-def.h.
| #define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34)) |
Definition at line 1938 of file cortex-m4-def.h.
| #define NVIC_MM_ADDR_S 0 |
Definition at line 9743 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_AP_M 0x07000000 |
Definition at line 9842 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_BUFFRABLE 0x00010000 |
Definition at line 9848 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_CACHEABLE 0x00020000 |
Definition at line 9846 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_ENABLE 0x00000001 |
Definition at line 9852 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8)) |
Definition at line 1947 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_SHAREABLE 0x00040000 |
Definition at line 9844 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E |
Definition at line 9851 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 |
Definition at line 9850 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_TEX_M 0x00380000 |
Definition at line 9843 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR1_XN 0x10000000 |
Definition at line 9841 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_AP_M 0x07000000 |
Definition at line 9871 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_BUFFRABLE 0x00010000 |
Definition at line 9877 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_CACHEABLE 0x00020000 |
Definition at line 9875 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_ENABLE 0x00000001 |
Definition at line 9881 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0)) |
Definition at line 1949 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_SHAREABLE 0x00040000 |
Definition at line 9873 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E |
Definition at line 9880 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 |
Definition at line 9879 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_TEX_M 0x00380000 |
Definition at line 9872 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR2_XN 0x10000000 |
Definition at line 9870 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_AP_M 0x07000000 |
Definition at line 9900 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_BUFFRABLE 0x00010000 |
Definition at line 9906 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_CACHEABLE 0x00020000 |
Definition at line 9904 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_ENABLE 0x00000001 |
Definition at line 9910 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8)) |
Definition at line 1951 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_SHAREABLE 0x00040000 |
Definition at line 9902 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E |
Definition at line 9909 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 |
Definition at line 9908 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_TEX_M 0x00380000 |
Definition at line 9901 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR3_XN 0x10000000 |
Definition at line 9899 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_AP_M 0x07000000 |
Definition at line 9816 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 |
Definition at line 9820 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 |
Definition at line 9819 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_ENABLE 0x00000001 |
Definition at line 9823 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0)) |
Definition at line 1945 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 |
Definition at line 9818 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_SIZE_M 0x0000003E |
Definition at line 9822 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 |
Definition at line 9821 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_TEX_M 0x00380000 |
Definition at line 9817 of file cortex-m4-def.h.
| #define NVIC_MPU_ATTR_XN 0x10000000 |
Definition at line 9815 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 |
Definition at line 9830 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_ADDR_S 5 |
Definition at line 9833 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4)) |
Definition at line 1946 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_REGION_M 0x00000007 |
Definition at line 9832 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_REGION_S 0 |
Definition at line 9834 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE1_VALID 0x00000010 |
Definition at line 9831 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 |
Definition at line 9859 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_ADDR_S 5 |
Definition at line 9862 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC)) |
Definition at line 1948 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_REGION_M 0x00000007 |
Definition at line 9861 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_REGION_S 0 |
Definition at line 9863 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE2_VALID 0x00000010 |
Definition at line 9860 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 |
Definition at line 9888 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_ADDR_S 5 |
Definition at line 9891 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4)) |
Definition at line 1950 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_REGION_M 0x00000007 |
Definition at line 9890 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_REGION_S 0 |
Definition at line 9892 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE3_VALID 0x00000010 |
Definition at line 9889 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 |
Definition at line 9804 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_ADDR_S 5 |
Definition at line 9807 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C)) |
Definition at line 1944 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_REGION_M 0x00000007 |
Definition at line 9806 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_REGION_S 0 |
Definition at line 9808 of file cortex-m4-def.h.
| #define NVIC_MPU_BASE_VALID 0x00000010 |
Definition at line 9805 of file cortex-m4-def.h.
| #define NVIC_MPU_CTRL_ENABLE 0x00000001 |
Definition at line 9788 of file cortex-m4-def.h.
| #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 |
Definition at line 9787 of file cortex-m4-def.h.
| #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 |
Definition at line 9786 of file cortex-m4-def.h.
| #define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94)) |
Definition at line 1942 of file cortex-m4-def.h.
| #define NVIC_MPU_NUMBER_M 0x00000007 |
Definition at line 9796 of file cortex-m4-def.h.
| #define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98)) |
Definition at line 1943 of file cortex-m4-def.h.
| #define NVIC_MPU_NUMBER_S 0 |
Definition at line 9797 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 |
Definition at line 9776 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_DREGION_S 8 |
Definition at line 9779 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 |
Definition at line 9775 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_IREGION_S 16 |
Definition at line 9778 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90)) |
Definition at line 1941 of file cortex-m4-def.h.
| #define NVIC_MPU_TYPE_SEPARATE 0x00000001 |
Definition at line 9777 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT0 0x00000001 |
Definition at line 8814 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT1 0x00000002 |
Definition at line 8815 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT10 0x00000400 |
Definition at line 8824 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT11 0x00000800 |
Definition at line 8825 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT12 0x00001000 |
Definition at line 8826 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT13 0x00002000 |
Definition at line 8827 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT14 0x00004000 |
Definition at line 8828 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT15 0x00008000 |
Definition at line 8829 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT16 0x00010000 |
Definition at line 8830 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT17 0x00020000 |
Definition at line 8831 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT18 0x00040000 |
Definition at line 8832 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT19 0x00080000 |
Definition at line 8833 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT2 0x00000004 |
Definition at line 8816 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT20 0x00100000 |
Definition at line 8834 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT21 0x00200000 |
Definition at line 8835 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT22 0x00400000 |
Definition at line 8836 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT23 0x00800000 |
Definition at line 8837 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT24 0x01000000 |
Definition at line 8838 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT25 0x02000000 |
Definition at line 8839 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT26 0x04000000 |
Definition at line 8840 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT27 0x08000000 |
Definition at line 8841 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT28 0x10000000 |
Definition at line 8842 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT29 0x20000000 |
Definition at line 8843 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT3 0x00000008 |
Definition at line 8817 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT30 0x40000000 |
Definition at line 8844 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT31 0x80000000 |
Definition at line 8845 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT4 0x00000010 |
Definition at line 8818 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT5 0x00000020 |
Definition at line 8819 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT6 0x00000040 |
Definition at line 8820 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT7 0x00000080 |
Definition at line 8821 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT8 0x00000100 |
Definition at line 8822 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT9 0x00000200 |
Definition at line 8823 of file cortex-m4-def.h.
| #define NVIC_PEND0_INT_M 0xFFFFFFFF |
Definition at line 8813 of file cortex-m4-def.h.
| #define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200)) |
Definition at line 1875 of file cortex-m4-def.h.
| #define NVIC_PEND1_INT_M 0xFFFFFFFF |
Definition at line 8852 of file cortex-m4-def.h.
| #define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204)) |
Definition at line 1876 of file cortex-m4-def.h.
| #define NVIC_PEND2_INT_M 0xFFFFFFFF |
Definition at line 8859 of file cortex-m4-def.h.
| #define NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208)) |
Definition at line 1877 of file cortex-m4-def.h.
| #define NVIC_PEND3_INT_M 0xFFFFFFFF |
Definition at line 8866 of file cortex-m4-def.h.
| #define NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C)) |
Definition at line 1878 of file cortex-m4-def.h.
| #define NVIC_PEND4_INT_M 0x000007FF |
Definition at line 8873 of file cortex-m4-def.h.
| #define NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210)) |
Definition at line 1879 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT0_M 0x000000E0 |
Definition at line 9041 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT0_S 5 |
Definition at line 9045 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT1_M 0x0000E000 |
Definition at line 9040 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT1_S 13 |
Definition at line 9044 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT2_M 0x00E00000 |
Definition at line 9039 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT2_S 21 |
Definition at line 9043 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT3_M 0xE0000000 |
Definition at line 9038 of file cortex-m4-def.h.
| #define NVIC_PRI0_INT3_S 29 |
Definition at line 9042 of file cortex-m4-def.h.
| #define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) |
Definition at line 1890 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT40_M 0x000000E0 |
Definition at line 9181 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT40_S 5 |
Definition at line 9185 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT41_M 0x0000E000 |
Definition at line 9180 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT41_S 13 |
Definition at line 9184 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT42_M 0x00E00000 |
Definition at line 9179 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT42_S 21 |
Definition at line 9183 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT43_M 0xE0000000 |
Definition at line 9178 of file cortex-m4-def.h.
| #define NVIC_PRI10_INT43_S 29 |
Definition at line 9182 of file cortex-m4-def.h.
| #define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428)) |
Definition at line 1900 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT44_M 0x000000E0 |
Definition at line 9195 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT44_S 5 |
Definition at line 9199 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT45_M 0x0000E000 |
Definition at line 9194 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT45_S 13 |
Definition at line 9198 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT46_M 0x00E00000 |
Definition at line 9193 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT46_S 21 |
Definition at line 9197 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT47_M 0xE0000000 |
Definition at line 9192 of file cortex-m4-def.h.
| #define NVIC_PRI11_INT47_S 29 |
Definition at line 9196 of file cortex-m4-def.h.
| #define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C)) |
Definition at line 1901 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT48_M 0x000000E0 |
Definition at line 9209 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT48_S 5 |
Definition at line 9213 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT49_M 0x0000E000 |
Definition at line 9208 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT49_S 13 |
Definition at line 9212 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT50_M 0x00E00000 |
Definition at line 9207 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT50_S 21 |
Definition at line 9211 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT51_M 0xE0000000 |
Definition at line 9206 of file cortex-m4-def.h.
| #define NVIC_PRI12_INT51_S 29 |
Definition at line 9210 of file cortex-m4-def.h.
| #define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430)) |
Definition at line 1902 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT52_M 0x000000E0 |
Definition at line 9223 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT52_S 5 |
Definition at line 9227 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT53_M 0x0000E000 |
Definition at line 9222 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT53_S 13 |
Definition at line 9226 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT54_M 0x00E00000 |
Definition at line 9221 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT54_S 21 |
Definition at line 9225 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT55_M 0xE0000000 |
Definition at line 9220 of file cortex-m4-def.h.
| #define NVIC_PRI13_INT55_S 29 |
Definition at line 9224 of file cortex-m4-def.h.
| #define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434)) |
Definition at line 1903 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTA_M 0x000000E0 |
Definition at line 9237 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTA_S 5 |
Definition at line 9241 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTB_M 0x0000E000 |
Definition at line 9236 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTB_S 13 |
Definition at line 9240 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTC_M 0x00E00000 |
Definition at line 9235 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTC_S 21 |
Definition at line 9239 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTD_M 0xE0000000 |
Definition at line 9234 of file cortex-m4-def.h.
| #define NVIC_PRI14_INTD_S 29 |
Definition at line 9238 of file cortex-m4-def.h.
| #define NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438)) |
Definition at line 1904 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTA_M 0x000000E0 |
Definition at line 9251 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTA_S 5 |
Definition at line 9255 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTB_M 0x0000E000 |
Definition at line 9250 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTB_S 13 |
Definition at line 9254 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTC_M 0x00E00000 |
Definition at line 9249 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTC_S 21 |
Definition at line 9253 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTD_M 0xE0000000 |
Definition at line 9248 of file cortex-m4-def.h.
| #define NVIC_PRI15_INTD_S 29 |
Definition at line 9252 of file cortex-m4-def.h.
| #define NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C)) |
Definition at line 1905 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTA_M 0x000000E0 |
Definition at line 9265 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTA_S 5 |
Definition at line 9269 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTB_M 0x0000E000 |
Definition at line 9264 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTB_S 13 |
Definition at line 9268 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTC_M 0x00E00000 |
Definition at line 9263 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTC_S 21 |
Definition at line 9267 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTD_M 0xE0000000 |
Definition at line 9262 of file cortex-m4-def.h.
| #define NVIC_PRI16_INTD_S 29 |
Definition at line 9266 of file cortex-m4-def.h.
| #define NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440)) |
Definition at line 1906 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTA_M 0x000000E0 |
Definition at line 9279 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTA_S 5 |
Definition at line 9283 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTB_M 0x0000E000 |
Definition at line 9278 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTB_S 13 |
Definition at line 9282 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTC_M 0x00E00000 |
Definition at line 9277 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTC_S 21 |
Definition at line 9281 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTD_M 0xE0000000 |
Definition at line 9276 of file cortex-m4-def.h.
| #define NVIC_PRI17_INTD_S 29 |
Definition at line 9280 of file cortex-m4-def.h.
| #define NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444)) |
Definition at line 1907 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTA_M 0x000000E0 |
Definition at line 9293 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTA_S 5 |
Definition at line 9297 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTB_M 0x0000E000 |
Definition at line 9292 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTB_S 13 |
Definition at line 9296 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTC_M 0x00E00000 |
Definition at line 9291 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTC_S 21 |
Definition at line 9295 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTD_M 0xE0000000 |
Definition at line 9290 of file cortex-m4-def.h.
| #define NVIC_PRI18_INTD_S 29 |
Definition at line 9294 of file cortex-m4-def.h.
| #define NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448)) |
Definition at line 1908 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTA_M 0x000000E0 |
Definition at line 9307 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTA_S 5 |
Definition at line 9311 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTB_M 0x0000E000 |
Definition at line 9306 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTB_S 13 |
Definition at line 9310 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTC_M 0x00E00000 |
Definition at line 9305 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTC_S 21 |
Definition at line 9309 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTD_M 0xE0000000 |
Definition at line 9304 of file cortex-m4-def.h.
| #define NVIC_PRI19_INTD_S 29 |
Definition at line 9308 of file cortex-m4-def.h.
| #define NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C)) |
Definition at line 1909 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT4_M 0x000000E0 |
Definition at line 9055 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT4_S 5 |
Definition at line 9059 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT5_M 0x0000E000 |
Definition at line 9054 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT5_S 13 |
Definition at line 9058 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT6_M 0x00E00000 |
Definition at line 9053 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT6_S 21 |
Definition at line 9057 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT7_M 0xE0000000 |
Definition at line 9052 of file cortex-m4-def.h.
| #define NVIC_PRI1_INT7_S 29 |
Definition at line 9056 of file cortex-m4-def.h.
| #define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404)) |
Definition at line 1891 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTA_M 0x000000E0 |
Definition at line 9321 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTA_S 5 |
Definition at line 9325 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTB_M 0x0000E000 |
Definition at line 9320 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTB_S 13 |
Definition at line 9324 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTC_M 0x00E00000 |
Definition at line 9319 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTC_S 21 |
Definition at line 9323 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTD_M 0xE0000000 |
Definition at line 9318 of file cortex-m4-def.h.
| #define NVIC_PRI20_INTD_S 29 |
Definition at line 9322 of file cortex-m4-def.h.
| #define NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450)) |
Definition at line 1910 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTA_M 0x000000E0 |
Definition at line 9335 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTA_S 5 |
Definition at line 9339 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTB_M 0x0000E000 |
Definition at line 9334 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTB_S 13 |
Definition at line 9338 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTC_M 0x00E00000 |
Definition at line 9333 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTC_S 21 |
Definition at line 9337 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTD_M 0xE0000000 |
Definition at line 9332 of file cortex-m4-def.h.
| #define NVIC_PRI21_INTD_S 29 |
Definition at line 9336 of file cortex-m4-def.h.
| #define NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454)) |
Definition at line 1911 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTA_M 0x000000E0 |
Definition at line 9349 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTA_S 5 |
Definition at line 9353 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTB_M 0x0000E000 |
Definition at line 9348 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTB_S 13 |
Definition at line 9352 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTC_M 0x00E00000 |
Definition at line 9347 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTC_S 21 |
Definition at line 9351 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTD_M 0xE0000000 |
Definition at line 9346 of file cortex-m4-def.h.
| #define NVIC_PRI22_INTD_S 29 |
Definition at line 9350 of file cortex-m4-def.h.
| #define NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458)) |
Definition at line 1912 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTA_M 0x000000E0 |
Definition at line 9363 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTA_S 5 |
Definition at line 9367 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTB_M 0x0000E000 |
Definition at line 9362 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTB_S 13 |
Definition at line 9366 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTC_M 0x00E00000 |
Definition at line 9361 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTC_S 21 |
Definition at line 9365 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTD_M 0xE0000000 |
Definition at line 9360 of file cortex-m4-def.h.
| #define NVIC_PRI23_INTD_S 29 |
Definition at line 9364 of file cortex-m4-def.h.
| #define NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C)) |
Definition at line 1913 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTA_M 0x000000E0 |
Definition at line 9377 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTA_S 5 |
Definition at line 9381 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTB_M 0x0000E000 |
Definition at line 9376 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTB_S 13 |
Definition at line 9380 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTC_M 0x00E00000 |
Definition at line 9375 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTC_S 21 |
Definition at line 9379 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTD_M 0xE0000000 |
Definition at line 9374 of file cortex-m4-def.h.
| #define NVIC_PRI24_INTD_S 29 |
Definition at line 9378 of file cortex-m4-def.h.
| #define NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460)) |
Definition at line 1914 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTA_M 0x000000E0 |
Definition at line 9391 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTA_S 5 |
Definition at line 9395 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTB_M 0x0000E000 |
Definition at line 9390 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTB_S 13 |
Definition at line 9394 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTC_M 0x00E00000 |
Definition at line 9389 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTC_S 21 |
Definition at line 9393 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTD_M 0xE0000000 |
Definition at line 9388 of file cortex-m4-def.h.
| #define NVIC_PRI25_INTD_S 29 |
Definition at line 9392 of file cortex-m4-def.h.
| #define NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464)) |
Definition at line 1915 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTA_M 0x000000E0 |
Definition at line 9405 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTA_S 5 |
Definition at line 9409 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTB_M 0x0000E000 |
Definition at line 9404 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTB_S 13 |
Definition at line 9408 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTC_M 0x00E00000 |
Definition at line 9403 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTC_S 21 |
Definition at line 9407 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTD_M 0xE0000000 |
Definition at line 9402 of file cortex-m4-def.h.
| #define NVIC_PRI26_INTD_S 29 |
Definition at line 9406 of file cortex-m4-def.h.
| #define NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468)) |
Definition at line 1916 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTA_M 0x000000E0 |
Definition at line 9419 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTA_S 5 |
Definition at line 9423 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTB_M 0x0000E000 |
Definition at line 9418 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTB_S 13 |
Definition at line 9422 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTC_M 0x00E00000 |
Definition at line 9417 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTC_S 21 |
Definition at line 9421 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTD_M 0xE0000000 |
Definition at line 9416 of file cortex-m4-def.h.
| #define NVIC_PRI27_INTD_S 29 |
Definition at line 9420 of file cortex-m4-def.h.
| #define NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C)) |
Definition at line 1917 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTA_M 0x000000E0 |
Definition at line 9433 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTA_S 5 |
Definition at line 9437 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTB_M 0x0000E000 |
Definition at line 9432 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTB_S 13 |
Definition at line 9436 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTC_M 0x00E00000 |
Definition at line 9431 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTC_S 21 |
Definition at line 9435 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTD_M 0xE0000000 |
Definition at line 9430 of file cortex-m4-def.h.
| #define NVIC_PRI28_INTD_S 29 |
Definition at line 9434 of file cortex-m4-def.h.
| #define NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470)) |
Definition at line 1918 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTA_M 0x000000E0 |
Definition at line 9447 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTA_S 5 |
Definition at line 9451 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTB_M 0x0000E000 |
Definition at line 9446 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTB_S 13 |
Definition at line 9450 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTC_M 0x00E00000 |
Definition at line 9445 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTC_S 21 |
Definition at line 9449 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTD_M 0xE0000000 |
Definition at line 9444 of file cortex-m4-def.h.
| #define NVIC_PRI29_INTD_S 29 |
Definition at line 9448 of file cortex-m4-def.h.
| #define NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474)) |
Definition at line 1919 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT10_M 0x00E00000 |
Definition at line 9067 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT10_S 21 |
Definition at line 9071 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT11_M 0xE0000000 |
Definition at line 9066 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT11_S 29 |
Definition at line 9070 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT8_M 0x000000E0 |
Definition at line 9069 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT8_S 5 |
Definition at line 9073 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT9_M 0x0000E000 |
Definition at line 9068 of file cortex-m4-def.h.
| #define NVIC_PRI2_INT9_S 13 |
Definition at line 9072 of file cortex-m4-def.h.
| #define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408)) |
Definition at line 1892 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTA_M 0x000000E0 |
Definition at line 9461 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTA_S 5 |
Definition at line 9465 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTB_M 0x0000E000 |
Definition at line 9460 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTB_S 13 |
Definition at line 9464 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTC_M 0x00E00000 |
Definition at line 9459 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTC_S 21 |
Definition at line 9463 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTD_M 0xE0000000 |
Definition at line 9458 of file cortex-m4-def.h.
| #define NVIC_PRI30_INTD_S 29 |
Definition at line 9462 of file cortex-m4-def.h.
| #define NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478)) |
Definition at line 1920 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTA_M 0x000000E0 |
Definition at line 9475 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTA_S 5 |
Definition at line 9479 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTB_M 0x0000E000 |
Definition at line 9474 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTB_S 13 |
Definition at line 9478 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTC_M 0x00E00000 |
Definition at line 9473 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTC_S 21 |
Definition at line 9477 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTD_M 0xE0000000 |
Definition at line 9472 of file cortex-m4-def.h.
| #define NVIC_PRI31_INTD_S 29 |
Definition at line 9476 of file cortex-m4-def.h.
| #define NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C)) |
Definition at line 1921 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTA_M 0x000000E0 |
Definition at line 9489 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTA_S 5 |
Definition at line 9493 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTB_M 0x0000E000 |
Definition at line 9488 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTB_S 13 |
Definition at line 9492 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTC_M 0x00E00000 |
Definition at line 9487 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTC_S 21 |
Definition at line 9491 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTD_M 0xE0000000 |
Definition at line 9486 of file cortex-m4-def.h.
| #define NVIC_PRI32_INTD_S 29 |
Definition at line 9490 of file cortex-m4-def.h.
| #define NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480)) |
Definition at line 1922 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTA_M 0x000000E0 |
Definition at line 9506 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTA_S 5 |
Definition at line 9511 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTB_M 0x0000E000 |
Definition at line 9504 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTB_S 13 |
Definition at line 9510 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTC_M 0x00E00000 |
Definition at line 9502 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTC_S 21 |
Definition at line 9509 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTD_M 0xE0000000 |
Definition at line 9500 of file cortex-m4-def.h.
| #define NVIC_PRI33_INTD_S 29 |
Definition at line 9508 of file cortex-m4-def.h.
| #define NVIC_PRI33_R (*((volatile unsigned long *)0xE000E484)) |
Definition at line 1923 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTA_M 0x000000E0 |
Definition at line 9524 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTA_S 5 |
Definition at line 9529 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTB_M 0x0000E000 |
Definition at line 9522 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTB_S 13 |
Definition at line 9528 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTC_M 0x00E00000 |
Definition at line 9520 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTC_S 21 |
Definition at line 9527 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTD_M 0xE0000000 |
Definition at line 9518 of file cortex-m4-def.h.
| #define NVIC_PRI34_INTD_S 29 |
Definition at line 9526 of file cortex-m4-def.h.
| #define NVIC_PRI34_R (*((volatile unsigned long *)0xE000E488)) |
Definition at line 1924 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT12_M 0x000000E0 |
Definition at line 9083 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT12_S 5 |
Definition at line 9087 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT13_M 0x0000E000 |
Definition at line 9082 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT13_S 13 |
Definition at line 9086 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT14_M 0x00E00000 |
Definition at line 9081 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT14_S 21 |
Definition at line 9085 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT15_M 0xE0000000 |
Definition at line 9080 of file cortex-m4-def.h.
| #define NVIC_PRI3_INT15_S 29 |
Definition at line 9084 of file cortex-m4-def.h.
| #define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C)) |
Definition at line 1893 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT16_M 0x000000E0 |
Definition at line 9097 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT16_S 5 |
Definition at line 9101 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT17_M 0x0000E000 |
Definition at line 9096 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT17_S 13 |
Definition at line 9100 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT18_M 0x00E00000 |
Definition at line 9095 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT18_S 21 |
Definition at line 9099 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT19_M 0xE0000000 |
Definition at line 9094 of file cortex-m4-def.h.
| #define NVIC_PRI4_INT19_S 29 |
Definition at line 9098 of file cortex-m4-def.h.
| #define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) |
Definition at line 1894 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT20_M 0x000000E0 |
Definition at line 9111 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT20_S 5 |
Definition at line 9115 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT21_M 0x0000E000 |
Definition at line 9110 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT21_S 13 |
Definition at line 9114 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT22_M 0x00E00000 |
Definition at line 9109 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT22_S 21 |
Definition at line 9113 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT23_M 0xE0000000 |
Definition at line 9108 of file cortex-m4-def.h.
| #define NVIC_PRI5_INT23_S 29 |
Definition at line 9112 of file cortex-m4-def.h.
| #define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414)) |
Definition at line 1895 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT24_M 0x000000E0 |
Definition at line 9125 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT24_S 5 |
Definition at line 9129 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT25_M 0x0000E000 |
Definition at line 9124 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT25_S 13 |
Definition at line 9128 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT26_M 0x00E00000 |
Definition at line 9123 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT26_S 21 |
Definition at line 9127 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT27_M 0xE0000000 |
Definition at line 9122 of file cortex-m4-def.h.
| #define NVIC_PRI6_INT27_S 29 |
Definition at line 9126 of file cortex-m4-def.h.
| #define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418)) |
Definition at line 1896 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT28_M 0x000000E0 |
Definition at line 9139 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT28_S 5 |
Definition at line 9143 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT29_M 0x0000E000 |
Definition at line 9138 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT29_S 13 |
Definition at line 9142 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT30_M 0x00E00000 |
Definition at line 9137 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT30_S 21 |
Definition at line 9141 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT31_M 0xE0000000 |
Definition at line 9136 of file cortex-m4-def.h.
| #define NVIC_PRI7_INT31_S 29 |
Definition at line 9140 of file cortex-m4-def.h.
| #define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C)) |
Definition at line 1897 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT32_M 0x000000E0 |
Definition at line 9153 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT32_S 5 |
Definition at line 9157 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT33_M 0x0000E000 |
Definition at line 9152 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT33_S 13 |
Definition at line 9156 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT34_M 0x00E00000 |
Definition at line 9151 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT34_S 21 |
Definition at line 9155 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT35_M 0xE0000000 |
Definition at line 9150 of file cortex-m4-def.h.
| #define NVIC_PRI8_INT35_S 29 |
Definition at line 9154 of file cortex-m4-def.h.
| #define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420)) |
Definition at line 1898 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT36_M 0x000000E0 |
Definition at line 9167 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT36_S 5 |
Definition at line 9171 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT37_M 0x0000E000 |
Definition at line 9166 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT37_S 13 |
Definition at line 9170 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT38_M 0x00E00000 |
Definition at line 9165 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT38_S 21 |
Definition at line 9169 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT39_M 0xE0000000 |
Definition at line 9164 of file cortex-m4-def.h.
| #define NVIC_PRI9_INT39_S 29 |
Definition at line 9168 of file cortex-m4-def.h.
| #define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424)) |
Definition at line 1899 of file cortex-m4-def.h.
| #define NVIC_ST_CAL_NOREF 0x80000000 |
Definition at line 8669 of file cortex-m4-def.h.
| #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF |
Definition at line 8671 of file cortex-m4-def.h.
| #define NVIC_ST_CAL_ONEMS_S 0 |
Definition at line 8672 of file cortex-m4-def.h.
| #define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C)) |
Definition at line 1864 of file cortex-m4-def.h.
| #define NVIC_ST_CAL_SKEW 0x40000000 |
Definition at line 8670 of file cortex-m4-def.h.
| #define NVIC_ST_CTRL_CLK_SRC 0x00000004 |
Definition at line 8643 of file cortex-m4-def.h.
| #define NVIC_ST_CTRL_COUNT 0x00010000 |
Definition at line 8642 of file cortex-m4-def.h.
| #define NVIC_ST_CTRL_ENABLE 0x00000001 |
Definition at line 8645 of file cortex-m4-def.h.
| #define NVIC_ST_CTRL_INTEN 0x00000002 |
Definition at line 8644 of file cortex-m4-def.h.
| #define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010)) |
Definition at line 1861 of file cortex-m4-def.h.
| #define NVIC_ST_CURRENT_M 0x00FFFFFF |
Definition at line 8661 of file cortex-m4-def.h.
| #define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018)) |
Definition at line 1863 of file cortex-m4-def.h.
| #define NVIC_ST_CURRENT_S 0 |
Definition at line 8662 of file cortex-m4-def.h.
| #define NVIC_ST_RELOAD_M 0x00FFFFFF |
Definition at line 8652 of file cortex-m4-def.h.
| #define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014)) |
Definition at line 1862 of file cortex-m4-def.h.
| #define NVIC_ST_RELOAD_S 0 |
Definition at line 8653 of file cortex-m4-def.h.
| #define NVIC_SW_TRIG_INTID_M 0x000000FF |
Definition at line 9994 of file cortex-m4-def.h.
| #define NVIC_SW_TRIG_INTID_S 0 |
Definition at line 9995 of file cortex-m4-def.h.
| #define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00)) |
Definition at line 1956 of file cortex-m4-def.h.
| #define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10)) |
Definition at line 1929 of file cortex-m4-def.h.
| #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 |
Definition at line 9612 of file cortex-m4-def.h.
| #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 |
Definition at line 9613 of file cortex-m4-def.h.
| #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 |
Definition at line 9614 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_BUS 0x00020000 |
Definition at line 9669 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 |
Definition at line 9681 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 |
Definition at line 9672 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_MEM 0x00010000 |
Definition at line 9670 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 |
Definition at line 9682 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 |
Definition at line 9673 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_MON 0x00000100 |
Definition at line 9678 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 |
Definition at line 9677 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24)) |
Definition at line 1934 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_SVC 0x00008000 |
Definition at line 9671 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 |
Definition at line 9679 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_TICK 0x00000800 |
Definition at line 9676 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 |
Definition at line 9668 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_USAGEP 0x00001000 |
Definition at line 9674 of file cortex-m4-def.h.
| #define NVIC_SYS_HND_CTRL_USGA 0x00000008 |
Definition at line 9680 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_BUS_M 0x0000E000 |
Definition at line 9636 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_BUS_S 13 |
Definition at line 9639 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_MEM_M 0x000000E0 |
Definition at line 9637 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_MEM_S 5 |
Definition at line 9640 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18)) |
Definition at line 1931 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 |
Definition at line 9635 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI1_USAGE_S 21 |
Definition at line 9638 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C)) |
Definition at line 1932 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI2_SVC_M 0xE0000000 |
Definition at line 9647 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI2_SVC_S 29 |
Definition at line 9648 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 |
Definition at line 9657 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_DEBUG_S 5 |
Definition at line 9660 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 |
Definition at line 9656 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_PENDSV_S 21 |
Definition at line 9659 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20)) |
Definition at line 1933 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_TICK_M 0xE0000000 |
Definition at line 9655 of file cortex-m4-def.h.
| #define NVIC_SYS_PRI3_TICK_S 29 |
Definition at line 9658 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT0 0x00000001 |
Definition at line 8881 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT1 0x00000002 |
Definition at line 8882 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT10 0x00000400 |
Definition at line 8891 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT11 0x00000800 |
Definition at line 8892 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT12 0x00001000 |
Definition at line 8893 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT13 0x00002000 |
Definition at line 8894 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT14 0x00004000 |
Definition at line 8895 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT15 0x00008000 |
Definition at line 8896 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT16 0x00010000 |
Definition at line 8897 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT17 0x00020000 |
Definition at line 8898 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT18 0x00040000 |
Definition at line 8899 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT19 0x00080000 |
Definition at line 8900 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT2 0x00000004 |
Definition at line 8883 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT20 0x00100000 |
Definition at line 8901 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT21 0x00200000 |
Definition at line 8902 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT22 0x00400000 |
Definition at line 8903 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT23 0x00800000 |
Definition at line 8904 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT24 0x01000000 |
Definition at line 8905 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT25 0x02000000 |
Definition at line 8906 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT26 0x04000000 |
Definition at line 8907 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT27 0x08000000 |
Definition at line 8908 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT28 0x10000000 |
Definition at line 8909 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT29 0x20000000 |
Definition at line 8910 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT3 0x00000008 |
Definition at line 8884 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT30 0x40000000 |
Definition at line 8911 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT31 0x80000000 |
Definition at line 8912 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT4 0x00000010 |
Definition at line 8885 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT5 0x00000020 |
Definition at line 8886 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT6 0x00000040 |
Definition at line 8887 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT7 0x00000080 |
Definition at line 8888 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT8 0x00000100 |
Definition at line 8889 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT9 0x00000200 |
Definition at line 8890 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_INT_M 0xFFFFFFFF |
Definition at line 8880 of file cortex-m4-def.h.
| #define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280)) |
Definition at line 1880 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT32 0x00000001 |
Definition at line 8920 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT33 0x00000002 |
Definition at line 8921 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT34 0x00000004 |
Definition at line 8922 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT35 0x00000008 |
Definition at line 8923 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT36 0x00000010 |
Definition at line 8924 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT37 0x00000020 |
Definition at line 8925 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT38 0x00000040 |
Definition at line 8926 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT39 0x00000080 |
Definition at line 8927 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT40 0x00000100 |
Definition at line 8928 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT41 0x00000200 |
Definition at line 8929 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT42 0x00000400 |
Definition at line 8930 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT43 0x00000800 |
Definition at line 8931 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT44 0x00001000 |
Definition at line 8932 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT45 0x00002000 |
Definition at line 8933 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT46 0x00004000 |
Definition at line 8934 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT47 0x00008000 |
Definition at line 8935 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT48 0x00010000 |
Definition at line 8936 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT49 0x00020000 |
Definition at line 8937 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT50 0x00040000 |
Definition at line 8938 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT51 0x00080000 |
Definition at line 8939 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT52 0x00100000 |
Definition at line 8940 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT53 0x00200000 |
Definition at line 8941 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT54 0x00400000 |
Definition at line 8942 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT55 0x00800000 |
Definition at line 8943 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_INT_M 0xFFFFFFFF |
Definition at line 8919 of file cortex-m4-def.h.
| #define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284)) |
Definition at line 1881 of file cortex-m4-def.h.
| #define NVIC_UNPEND2_INT_M 0xFFFFFFFF |
Definition at line 8950 of file cortex-m4-def.h.
| #define NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288)) |
Definition at line 1882 of file cortex-m4-def.h.
| #define NVIC_UNPEND3_INT_M 0xFFFFFFFF |
Definition at line 8957 of file cortex-m4-def.h.
| #define NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C)) |
Definition at line 1883 of file cortex-m4-def.h.
| #define NVIC_UNPEND4_INT_M 0x000007FF |
Definition at line 8964 of file cortex-m4-def.h.
| #define NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290)) |
Definition at line 1884 of file cortex-m4-def.h.
| #define NVIC_VTABLE_BASE 0x20000000 |
Definition at line 9582 of file cortex-m4-def.h.
| #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 |
Definition at line 9583 of file cortex-m4-def.h.
| #define NVIC_VTABLE_OFFSET_S 10 |
Definition at line 9584 of file cortex-m4-def.h.
| #define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08)) |
Definition at line 1927 of file cortex-m4-def.h.
| #define SSI0_CC_R (*((volatile unsigned long *)0x40008FC8)) |
Definition at line 250 of file cortex-m4-def.h.
| #define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010)) |
Definition at line 244 of file cortex-m4-def.h.
| #define SSI0_CR0_R (*((volatile unsigned long *)0x40008000)) |
Definition at line 240 of file cortex-m4-def.h.
| #define SSI0_CR1_R (*((volatile unsigned long *)0x40008004)) |
Definition at line 241 of file cortex-m4-def.h.
| #define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024)) |
Definition at line 249 of file cortex-m4-def.h.
| #define SSI0_DR_R (*((volatile unsigned long *)0x40008008)) |
Definition at line 242 of file cortex-m4-def.h.
| #define SSI0_ICR_R (*((volatile unsigned long *)0x40008020)) |
Definition at line 248 of file cortex-m4-def.h.
| #define SSI0_IM_R (*((volatile unsigned long *)0x40008014)) |
Definition at line 245 of file cortex-m4-def.h.
| #define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C)) |
Definition at line 247 of file cortex-m4-def.h.
| #define SSI0_RIS_R (*((volatile unsigned long *)0x40008018)) |
Definition at line 246 of file cortex-m4-def.h.
| #define SSI0_SR_R (*((volatile unsigned long *)0x4000800C)) |
Definition at line 243 of file cortex-m4-def.h.
| #define SSI1_CC_R (*((volatile unsigned long *)0x40009FC8)) |
Definition at line 267 of file cortex-m4-def.h.
| #define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010)) |
Definition at line 261 of file cortex-m4-def.h.
| #define SSI1_CR0_R (*((volatile unsigned long *)0x40009000)) |
Definition at line 257 of file cortex-m4-def.h.
| #define SSI1_CR1_R (*((volatile unsigned long *)0x40009004)) |
Definition at line 258 of file cortex-m4-def.h.
| #define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024)) |
Definition at line 266 of file cortex-m4-def.h.
| #define SSI1_DR_R (*((volatile unsigned long *)0x40009008)) |
Definition at line 259 of file cortex-m4-def.h.
| #define SSI1_ICR_R (*((volatile unsigned long *)0x40009020)) |
Definition at line 265 of file cortex-m4-def.h.
| #define SSI1_IM_R (*((volatile unsigned long *)0x40009014)) |
Definition at line 262 of file cortex-m4-def.h.
| #define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C)) |
Definition at line 264 of file cortex-m4-def.h.
| #define SSI1_RIS_R (*((volatile unsigned long *)0x40009018)) |
Definition at line 263 of file cortex-m4-def.h.
| #define SSI1_SR_R (*((volatile unsigned long *)0x4000900C)) |
Definition at line 260 of file cortex-m4-def.h.
| #define SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8)) |
Definition at line 284 of file cortex-m4-def.h.
| #define SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010)) |
Definition at line 278 of file cortex-m4-def.h.
| #define SSI2_CR0_R (*((volatile unsigned long *)0x4000A000)) |
Definition at line 274 of file cortex-m4-def.h.
| #define SSI2_CR1_R (*((volatile unsigned long *)0x4000A004)) |
Definition at line 275 of file cortex-m4-def.h.
| #define SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024)) |
Definition at line 283 of file cortex-m4-def.h.
| #define SSI2_DR_R (*((volatile unsigned long *)0x4000A008)) |
Definition at line 276 of file cortex-m4-def.h.
| #define SSI2_ICR_R (*((volatile unsigned long *)0x4000A020)) |
Definition at line 282 of file cortex-m4-def.h.
| #define SSI2_IM_R (*((volatile unsigned long *)0x4000A014)) |
Definition at line 279 of file cortex-m4-def.h.
| #define SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C)) |
Definition at line 281 of file cortex-m4-def.h.
| #define SSI2_RIS_R (*((volatile unsigned long *)0x4000A018)) |
Definition at line 280 of file cortex-m4-def.h.
| #define SSI2_SR_R (*((volatile unsigned long *)0x4000A00C)) |
Definition at line 277 of file cortex-m4-def.h.
| #define SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8)) |
Definition at line 301 of file cortex-m4-def.h.
| #define SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010)) |
Definition at line 295 of file cortex-m4-def.h.
| #define SSI3_CR0_R (*((volatile unsigned long *)0x4000B000)) |
Definition at line 291 of file cortex-m4-def.h.
| #define SSI3_CR1_R (*((volatile unsigned long *)0x4000B004)) |
Definition at line 292 of file cortex-m4-def.h.
| #define SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024)) |
Definition at line 300 of file cortex-m4-def.h.
| #define SSI3_DR_R (*((volatile unsigned long *)0x4000B008)) |
Definition at line 293 of file cortex-m4-def.h.
| #define SSI3_ICR_R (*((volatile unsigned long *)0x4000B020)) |
Definition at line 299 of file cortex-m4-def.h.
| #define SSI3_IM_R (*((volatile unsigned long *)0x4000B014)) |
Definition at line 296 of file cortex-m4-def.h.
| #define SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C)) |
Definition at line 298 of file cortex-m4-def.h.
| #define SSI3_RIS_R (*((volatile unsigned long *)0x4000B018)) |
Definition at line 297 of file cortex-m4-def.h.
| #define SSI3_SR_R (*((volatile unsigned long *)0x4000B00C)) |
Definition at line 294 of file cortex-m4-def.h.
| #define SSI_CC_CS_M 0x0000000F |
Definition at line 2389 of file cortex-m4-def.h.
| #define SSI_CC_CS_PIOSC 0x00000005 |
Definition at line 2393 of file cortex-m4-def.h.
| #define SSI_CC_CS_SYSPLL 0x00000000 |
Definition at line 2390 of file cortex-m4-def.h.
| #define SSI_CPSR_CPSDVSR_M 0x000000FF |
Definition at line 2323 of file cortex-m4-def.h.
| #define SSI_CPSR_CPSDVSR_S 0 |
Definition at line 2324 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_10 0x00000009 |
Definition at line 2278 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_11 0x0000000A |
Definition at line 2279 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_12 0x0000000B |
Definition at line 2280 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_13 0x0000000C |
Definition at line 2281 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_14 0x0000000D |
Definition at line 2282 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_15 0x0000000E |
Definition at line 2283 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_16 0x0000000F |
Definition at line 2284 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_4 0x00000003 |
Definition at line 2272 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_5 0x00000004 |
Definition at line 2273 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_6 0x00000005 |
Definition at line 2274 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_7 0x00000006 |
Definition at line 2275 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_8 0x00000007 |
Definition at line 2276 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_9 0x00000008 |
Definition at line 2277 of file cortex-m4-def.h.
| #define SSI_CR0_DSS_M 0x0000000F |
Definition at line 2271 of file cortex-m4-def.h.
| #define SSI_CR0_FRF_M 0x00000030 |
Definition at line 2266 of file cortex-m4-def.h.
| #define SSI_CR0_FRF_MOTO 0x00000000 |
Definition at line 2267 of file cortex-m4-def.h.
| #define SSI_CR0_FRF_NMW 0x00000020 |
Definition at line 2270 of file cortex-m4-def.h.
| #define SSI_CR0_FRF_TI 0x00000010 |
Definition at line 2268 of file cortex-m4-def.h.
| #define SSI_CR0_SCR_M 0x0000FF00 |
Definition at line 2263 of file cortex-m4-def.h.
| #define SSI_CR0_SCR_S 8 |
Definition at line 2285 of file cortex-m4-def.h.
| #define SSI_CR0_SPH 0x00000080 |
Definition at line 2264 of file cortex-m4-def.h.
| #define SSI_CR0_SPO 0x00000040 |
Definition at line 2265 of file cortex-m4-def.h.
| #define SSI_CR1_EOT 0x00000010 |
Definition at line 2292 of file cortex-m4-def.h.
| #define SSI_CR1_LBM 0x00000001 |
Definition at line 2297 of file cortex-m4-def.h.
| #define SSI_CR1_MS 0x00000004 |
Definition at line 2294 of file cortex-m4-def.h.
| #define SSI_CR1_SOD 0x00000008 |
Definition at line 2293 of file cortex-m4-def.h.
| #define SSI_CR1_SSE 0x00000002 |
Definition at line 2295 of file cortex-m4-def.h.
| #define SSI_DMACTL_RXDMAE 0x00000001 |
Definition at line 2382 of file cortex-m4-def.h.
| #define SSI_DMACTL_TXDMAE 0x00000002 |
Definition at line 2381 of file cortex-m4-def.h.
| #define SSI_DR_DATA_M 0x0000FFFF |
Definition at line 2304 of file cortex-m4-def.h.
| #define SSI_DR_DATA_S 0 |
Definition at line 2305 of file cortex-m4-def.h.
| #define SSI_ICR_RORIC 0x00000001 |
Definition at line 2373 of file cortex-m4-def.h.
| #define SSI_ICR_RTIC 0x00000002 |
Definition at line 2371 of file cortex-m4-def.h.
| #define SSI_IM_RORIM 0x00000001 |
Definition at line 2335 of file cortex-m4-def.h.
| #define SSI_IM_RTIM 0x00000002 |
Definition at line 2333 of file cortex-m4-def.h.
| #define SSI_IM_RXIM 0x00000004 |
Definition at line 2332 of file cortex-m4-def.h.
| #define SSI_IM_TXIM 0x00000008 |
Definition at line 2331 of file cortex-m4-def.h.
| #define SSI_MIS_RORMIS 0x00000001 |
Definition at line 2363 of file cortex-m4-def.h.
| #define SSI_MIS_RTMIS 0x00000002 |
Definition at line 2361 of file cortex-m4-def.h.
| #define SSI_MIS_RXMIS 0x00000004 |
Definition at line 2359 of file cortex-m4-def.h.
| #define SSI_MIS_TXMIS 0x00000008 |
Definition at line 2357 of file cortex-m4-def.h.
| #define SSI_RIS_RORRIS 0x00000001 |
Definition at line 2349 of file cortex-m4-def.h.
| #define SSI_RIS_RTRIS 0x00000002 |
Definition at line 2347 of file cortex-m4-def.h.
| #define SSI_RIS_RXRIS 0x00000004 |
Definition at line 2345 of file cortex-m4-def.h.
| #define SSI_RIS_TXRIS 0x00000008 |
Definition at line 2343 of file cortex-m4-def.h.
| #define SSI_SR_BSY 0x00000010 |
Definition at line 2312 of file cortex-m4-def.h.
| #define SSI_SR_RFF 0x00000008 |
Definition at line 2313 of file cortex-m4-def.h.
| #define SSI_SR_RNE 0x00000004 |
Definition at line 2314 of file cortex-m4-def.h.
| #define SSI_SR_TFE 0x00000001 |
Definition at line 2316 of file cortex-m4-def.h.
| #define SSI_SR_TNF 0x00000002 |
Definition at line 2315 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F |
Definition at line 6295 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 |
Definition at line 6291 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_192K 0x0000005F |
Definition at line 6296 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F |
Definition at line 6297 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F |
Definition at line 6292 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F |
Definition at line 6293 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 |
Definition at line 6290 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F |
Definition at line 6294 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF |
Definition at line 6289 of file cortex-m4-def.h.
| #define SYSCTL_DC0_FLASHSZ_S 0 |
Definition at line 6299 of file cortex-m4-def.h.
| #define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008)) |
Definition at line 1674 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 |
Definition at line 6284 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 |
Definition at line 6285 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 |
Definition at line 6286 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 |
Definition at line 6287 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 |
Definition at line 6280 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 |
Definition at line 6288 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 |
Definition at line 6281 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 |
Definition at line 6282 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 |
Definition at line 6283 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 |
Definition at line 6279 of file cortex-m4-def.h.
| #define SYSCTL_DC0_SRAMSZ_S 16 |
Definition at line 6298 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0 0x00010000 |
Definition at line 6312 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0SPD_125K 0x00000000 |
Definition at line 6332 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0SPD_1M 0x00000300 |
Definition at line 6335 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0SPD_250K 0x00000100 |
Definition at line 6333 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0SPD_500K 0x00000200 |
Definition at line 6334 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC0SPD_M 0x00000300 |
Definition at line 6331 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1 0x00020000 |
Definition at line 6311 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1SPD_125K 0x00000000 |
Definition at line 6327 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 |
Definition at line 6330 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1SPD_250K 0x00000400 |
Definition at line 6328 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1SPD_500K 0x00000800 |
Definition at line 6329 of file cortex-m4-def.h.
| #define SYSCTL_DC1_ADC1SPD_M 0x00000C00 |
Definition at line 6326 of file cortex-m4-def.h.
| #define SYSCTL_DC1_CAN0 0x01000000 |
Definition at line 6308 of file cortex-m4-def.h.
| #define SYSCTL_DC1_CAN1 0x02000000 |
Definition at line 6307 of file cortex-m4-def.h.
| #define SYSCTL_DC1_HIB 0x00000040 |
Definition at line 6337 of file cortex-m4-def.h.
| #define SYSCTL_DC1_JTAG 0x00000001 |
Definition at line 6343 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_100 0x00001000 |
Definition at line 6314 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_20 0x00009000 |
Definition at line 6324 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_25 0x00007000 |
Definition at line 6322 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_40 0x00004000 |
Definition at line 6320 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 |
Definition at line 6318 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_66 0x00002000 |
Definition at line 6316 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 |
Definition at line 6313 of file cortex-m4-def.h.
| #define SYSCTL_DC1_MPU 0x00000080 |
Definition at line 6336 of file cortex-m4-def.h.
| #define SYSCTL_DC1_PLL 0x00000010 |
Definition at line 6339 of file cortex-m4-def.h.
| #define SYSCTL_DC1_PWM0 0x00100000 |
Definition at line 6310 of file cortex-m4-def.h.
| #define SYSCTL_DC1_PWM1 0x00200000 |
Definition at line 6309 of file cortex-m4-def.h.
| #define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010)) |
Definition at line 1675 of file cortex-m4-def.h.
| #define SYSCTL_DC1_SWD 0x00000002 |
Definition at line 6342 of file cortex-m4-def.h.
| #define SYSCTL_DC1_SWO 0x00000004 |
Definition at line 6341 of file cortex-m4-def.h.
| #define SYSCTL_DC1_TEMP 0x00000020 |
Definition at line 6338 of file cortex-m4-def.h.
| #define SYSCTL_DC1_WDT0 0x00000008 |
Definition at line 6340 of file cortex-m4-def.h.
| #define SYSCTL_DC1_WDT1 0x10000000 |
Definition at line 6306 of file cortex-m4-def.h.
| #define SYSCTL_DC2_COMP0 0x01000000 |
Definition at line 6354 of file cortex-m4-def.h.
| #define SYSCTL_DC2_COMP1 0x02000000 |
Definition at line 6353 of file cortex-m4-def.h.
| #define SYSCTL_DC2_COMP2 0x04000000 |
Definition at line 6352 of file cortex-m4-def.h.
| #define SYSCTL_DC2_EPI0 0x40000000 |
Definition at line 6350 of file cortex-m4-def.h.
| #define SYSCTL_DC2_I2C0 0x00001000 |
Definition at line 6362 of file cortex-m4-def.h.
| #define SYSCTL_DC2_I2C0HS 0x00002000 |
Definition at line 6361 of file cortex-m4-def.h.
| #define SYSCTL_DC2_I2C1 0x00004000 |
Definition at line 6360 of file cortex-m4-def.h.
| #define SYSCTL_DC2_I2C1HS 0x00008000 |
Definition at line 6359 of file cortex-m4-def.h.
| #define SYSCTL_DC2_I2S0 0x10000000 |
Definition at line 6351 of file cortex-m4-def.h.
| #define SYSCTL_DC2_QEI0 0x00000100 |
Definition at line 6364 of file cortex-m4-def.h.
| #define SYSCTL_DC2_QEI1 0x00000200 |
Definition at line 6363 of file cortex-m4-def.h.
| #define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014)) |
Definition at line 1676 of file cortex-m4-def.h.
| #define SYSCTL_DC2_SSI0 0x00000010 |
Definition at line 6366 of file cortex-m4-def.h.
| #define SYSCTL_DC2_SSI1 0x00000020 |
Definition at line 6365 of file cortex-m4-def.h.
| #define SYSCTL_DC2_TIMER0 0x00010000 |
Definition at line 6358 of file cortex-m4-def.h.
| #define SYSCTL_DC2_TIMER1 0x00020000 |
Definition at line 6357 of file cortex-m4-def.h.
| #define SYSCTL_DC2_TIMER2 0x00040000 |
Definition at line 6356 of file cortex-m4-def.h.
| #define SYSCTL_DC2_TIMER3 0x00080000 |
Definition at line 6355 of file cortex-m4-def.h.
| #define SYSCTL_DC2_UART0 0x00000001 |
Definition at line 6369 of file cortex-m4-def.h.
| #define SYSCTL_DC2_UART1 0x00000002 |
Definition at line 6368 of file cortex-m4-def.h.
| #define SYSCTL_DC2_UART2 0x00000004 |
Definition at line 6367 of file cortex-m4-def.h.
| #define SYSCTL_DC3_32KHZ 0x80000000 |
Definition at line 6376 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN0 0x00010000 |
Definition at line 6390 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN1 0x00020000 |
Definition at line 6389 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN2 0x00040000 |
Definition at line 6388 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN3 0x00080000 |
Definition at line 6387 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN4 0x00100000 |
Definition at line 6386 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN5 0x00200000 |
Definition at line 6385 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN6 0x00400000 |
Definition at line 6384 of file cortex-m4-def.h.
| #define SYSCTL_DC3_ADC0AIN7 0x00800000 |
Definition at line 6383 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C0MINUS 0x00000040 |
Definition at line 6400 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C0O 0x00000100 |
Definition at line 6398 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C0PLUS 0x00000080 |
Definition at line 6399 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C1MINUS 0x00000200 |
Definition at line 6397 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C1O 0x00000800 |
Definition at line 6395 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C1PLUS 0x00000400 |
Definition at line 6396 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C2MINUS 0x00001000 |
Definition at line 6394 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C2O 0x00004000 |
Definition at line 6392 of file cortex-m4-def.h.
| #define SYSCTL_DC3_C2PLUS 0x00002000 |
Definition at line 6393 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP0 0x01000000 |
Definition at line 6382 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP1 0x02000000 |
Definition at line 6381 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP2 0x04000000 |
Definition at line 6380 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP3 0x08000000 |
Definition at line 6379 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP4 0x10000000 |
Definition at line 6378 of file cortex-m4-def.h.
| #define SYSCTL_DC3_CCP5 0x20000000 |
Definition at line 6377 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM0 0x00000001 |
Definition at line 6406 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM1 0x00000002 |
Definition at line 6405 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM2 0x00000004 |
Definition at line 6404 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM3 0x00000008 |
Definition at line 6403 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM4 0x00000010 |
Definition at line 6402 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWM5 0x00000020 |
Definition at line 6401 of file cortex-m4-def.h.
| #define SYSCTL_DC3_PWMFAULT 0x00008000 |
Definition at line 6391 of file cortex-m4-def.h.
| #define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018)) |
Definition at line 1677 of file cortex-m4-def.h.
| #define SYSCTL_DC4_CCP6 0x00004000 |
Definition at line 6418 of file cortex-m4-def.h.
| #define SYSCTL_DC4_CCP7 0x00008000 |
Definition at line 6417 of file cortex-m4-def.h.
| #define SYSCTL_DC4_E1588 0x01000000 |
Definition at line 6415 of file cortex-m4-def.h.
| #define SYSCTL_DC4_EMAC0 0x10000000 |
Definition at line 6414 of file cortex-m4-def.h.
| #define SYSCTL_DC4_EPHY0 0x40000000 |
Definition at line 6413 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOA 0x00000001 |
Definition at line 6429 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOB 0x00000002 |
Definition at line 6428 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOC 0x00000004 |
Definition at line 6427 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOD 0x00000008 |
Definition at line 6426 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOE 0x00000010 |
Definition at line 6425 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOF 0x00000020 |
Definition at line 6424 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOG 0x00000040 |
Definition at line 6423 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOH 0x00000080 |
Definition at line 6422 of file cortex-m4-def.h.
| #define SYSCTL_DC4_GPIOJ 0x00000100 |
Definition at line 6421 of file cortex-m4-def.h.
| #define SYSCTL_DC4_PICAL 0x00040000 |
Definition at line 6416 of file cortex-m4-def.h.
| #define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C)) |
Definition at line 1678 of file cortex-m4-def.h.
| #define SYSCTL_DC4_ROM 0x00001000 |
Definition at line 6420 of file cortex-m4-def.h.
| #define SYSCTL_DC4_UDMA 0x00002000 |
Definition at line 6419 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM0 0x00000001 |
Definition at line 6449 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM1 0x00000002 |
Definition at line 6448 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM2 0x00000004 |
Definition at line 6447 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM3 0x00000008 |
Definition at line 6446 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM4 0x00000010 |
Definition at line 6445 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM5 0x00000020 |
Definition at line 6444 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM6 0x00000040 |
Definition at line 6443 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWM7 0x00000080 |
Definition at line 6442 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMEFLT 0x00200000 |
Definition at line 6440 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMESYNC 0x00100000 |
Definition at line 6441 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMFAULT0 0x01000000 |
Definition at line 6439 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMFAULT1 0x02000000 |
Definition at line 6438 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMFAULT2 0x04000000 |
Definition at line 6437 of file cortex-m4-def.h.
| #define SYSCTL_DC5_PWMFAULT3 0x08000000 |
Definition at line 6436 of file cortex-m4-def.h.
| #define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020)) |
Definition at line 1679 of file cortex-m4-def.h.
| #define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024)) |
Definition at line 1680 of file cortex-m4-def.h.
| #define SYSCTL_DC6_USB0_DEV 0x00000001 |
Definition at line 6458 of file cortex-m4-def.h.
| #define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 |
Definition at line 6459 of file cortex-m4-def.h.
| #define SYSCTL_DC6_USB0_M 0x00000003 |
Definition at line 6457 of file cortex-m4-def.h.
| #define SYSCTL_DC6_USB0_OTG 0x00000003 |
Definition at line 6460 of file cortex-m4-def.h.
| #define SYSCTL_DC6_USB0PHY 0x00000010 |
Definition at line 6456 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH0 0x00000001 |
Definition at line 6497 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH1 0x00000002 |
Definition at line 6496 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH10 0x00000400 |
Definition at line 6487 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH11 0x00000800 |
Definition at line 6486 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH12 0x00001000 |
Definition at line 6485 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH13 0x00002000 |
Definition at line 6484 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH14 0x00004000 |
Definition at line 6483 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH15 0x00008000 |
Definition at line 6482 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH16 0x00010000 |
Definition at line 6481 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH17 0x00020000 |
Definition at line 6480 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH18 0x00040000 |
Definition at line 6479 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH19 0x00080000 |
Definition at line 6478 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH2 0x00000004 |
Definition at line 6495 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH20 0x00100000 |
Definition at line 6477 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH21 0x00200000 |
Definition at line 6476 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH22 0x00400000 |
Definition at line 6475 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH23 0x00800000 |
Definition at line 6474 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH24 0x01000000 |
Definition at line 6473 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH25 0x02000000 |
Definition at line 6472 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH26 0x04000000 |
Definition at line 6471 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH27 0x08000000 |
Definition at line 6470 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH28 0x10000000 |
Definition at line 6469 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH29 0x20000000 |
Definition at line 6468 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH3 0x00000008 |
Definition at line 6494 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH30 0x40000000 |
Definition at line 6467 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH4 0x00000010 |
Definition at line 6493 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH5 0x00000020 |
Definition at line 6492 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH6 0x00000040 |
Definition at line 6491 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH7 0x00000080 |
Definition at line 6490 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH8 0x00000100 |
Definition at line 6489 of file cortex-m4-def.h.
| #define SYSCTL_DC7_DMACH9 0x00000200 |
Definition at line 6488 of file cortex-m4-def.h.
| #define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028)) |
Definition at line 1681 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN0 0x00000001 |
Definition at line 6535 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN1 0x00000002 |
Definition at line 6534 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN10 0x00000400 |
Definition at line 6525 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN11 0x00000800 |
Definition at line 6524 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN12 0x00001000 |
Definition at line 6523 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN13 0x00002000 |
Definition at line 6522 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN14 0x00004000 |
Definition at line 6521 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN15 0x00008000 |
Definition at line 6520 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN2 0x00000004 |
Definition at line 6533 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN3 0x00000008 |
Definition at line 6532 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN4 0x00000010 |
Definition at line 6531 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN5 0x00000020 |
Definition at line 6530 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN6 0x00000040 |
Definition at line 6529 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN7 0x00000080 |
Definition at line 6528 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN8 0x00000100 |
Definition at line 6527 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC0AIN9 0x00000200 |
Definition at line 6526 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN0 0x00010000 |
Definition at line 6519 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN1 0x00020000 |
Definition at line 6518 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN10 0x04000000 |
Definition at line 6509 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN11 0x08000000 |
Definition at line 6508 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN12 0x10000000 |
Definition at line 6507 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN13 0x20000000 |
Definition at line 6506 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN14 0x40000000 |
Definition at line 6505 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN15 0x80000000 |
Definition at line 6504 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN2 0x00040000 |
Definition at line 6517 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN3 0x00080000 |
Definition at line 6516 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN4 0x00100000 |
Definition at line 6515 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN5 0x00200000 |
Definition at line 6514 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN6 0x00400000 |
Definition at line 6513 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN7 0x00800000 |
Definition at line 6512 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN8 0x01000000 |
Definition at line 6511 of file cortex-m4-def.h.
| #define SYSCTL_DC8_ADC1AIN9 0x02000000 |
Definition at line 6510 of file cortex-m4-def.h.
| #define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C)) |
Definition at line 1682 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC0 0x00000001 |
Definition at line 7083 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC1 0x00000002 |
Definition at line 7082 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC2 0x00000004 |
Definition at line 7081 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC3 0x00000008 |
Definition at line 7080 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC4 0x00000010 |
Definition at line 7079 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC5 0x00000020 |
Definition at line 7078 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC6 0x00000040 |
Definition at line 7077 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC0DC7 0x00000080 |
Definition at line 7076 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC0 0x00010000 |
Definition at line 7075 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC1 0x00020000 |
Definition at line 7074 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC2 0x00040000 |
Definition at line 7073 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC3 0x00080000 |
Definition at line 7072 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC4 0x00100000 |
Definition at line 7071 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC5 0x00200000 |
Definition at line 7070 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC6 0x00400000 |
Definition at line 7069 of file cortex-m4-def.h.
| #define SYSCTL_DC9_ADC1DC7 0x00800000 |
Definition at line 7068 of file cortex-m4-def.h.
| #define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190)) |
Definition at line 1711 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_ADC0 0x00010000 |
Definition at line 6936 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_ADC1 0x00020000 |
Definition at line 6935 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_CAN0 0x01000000 |
Definition at line 6933 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_CAN1 0x02000000 |
Definition at line 6932 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_HIB 0x00000040 |
Definition at line 6937 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_PWM0 0x00100000 |
Definition at line 6934 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120)) |
Definition at line 1701 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_WDT0 0x00000008 |
Definition at line 6938 of file cortex-m4-def.h.
| #define SYSCTL_DCGC0_WDT1 0x10000000 |
Definition at line 6931 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_COMP0 0x01000000 |
Definition at line 6947 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_COMP1 0x02000000 |
Definition at line 6946 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_COMP2 0x04000000 |
Definition at line 6945 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_I2C0 0x00001000 |
Definition at line 6953 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_I2C1 0x00004000 |
Definition at line 6952 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_QEI0 0x00000100 |
Definition at line 6955 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_QEI1 0x00000200 |
Definition at line 6954 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124)) |
Definition at line 1702 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_SSI0 0x00000010 |
Definition at line 6957 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_SSI1 0x00000020 |
Definition at line 6956 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_TIMER0 0x00010000 |
Definition at line 6951 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_TIMER1 0x00020000 |
Definition at line 6950 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_TIMER2 0x00040000 |
Definition at line 6949 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_TIMER3 0x00080000 |
Definition at line 6948 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_UART0 0x00000001 |
Definition at line 6960 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_UART1 0x00000002 |
Definition at line 6959 of file cortex-m4-def.h.
| #define SYSCTL_DCGC1_UART2 0x00000004 |
Definition at line 6958 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOA 0x00000001 |
Definition at line 6977 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOB 0x00000002 |
Definition at line 6976 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOC 0x00000004 |
Definition at line 6975 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOD 0x00000008 |
Definition at line 6974 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOE 0x00000010 |
Definition at line 6973 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOF 0x00000020 |
Definition at line 6972 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOG 0x00000040 |
Definition at line 6971 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOH 0x00000080 |
Definition at line 6970 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_GPIOJ 0x00000100 |
Definition at line 6969 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128)) |
Definition at line 1703 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_UDMA 0x00002000 |
Definition at line 6968 of file cortex-m4-def.h.
| #define SYSCTL_DCGC2_USB0 0x00010000 |
Definition at line 6967 of file cortex-m4-def.h.
| #define SYSCTL_DCGCACMP_D0 0x00000001 |
Definition at line 7971 of file cortex-m4-def.h.
| #define SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C)) |
Definition at line 1782 of file cortex-m4-def.h.
| #define SYSCTL_DCGCADC_D0 0x00000001 |
Definition at line 7962 of file cortex-m4-def.h.
| #define SYSCTL_DCGCADC_D1 0x00000002 |
Definition at line 7960 of file cortex-m4-def.h.
| #define SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838)) |
Definition at line 1781 of file cortex-m4-def.h.
| #define SYSCTL_DCGCCAN_D0 0x00000001 |
Definition at line 7952 of file cortex-m4-def.h.
| #define SYSCTL_DCGCCAN_D1 0x00000002 |
Definition at line 7950 of file cortex-m4-def.h.
| #define SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834)) |
Definition at line 1780 of file cortex-m4-def.h.
| #define SYSCTL_DCGCDMA_D0 0x00000001 |
Definition at line 7871 of file cortex-m4-def.h.
| #define SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C)) |
Definition at line 1774 of file cortex-m4-def.h.
| #define SYSCTL_DCGCEEPROM_D0 0x00000001 |
Definition at line 7981 of file cortex-m4-def.h.
| #define SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858)) |
Definition at line 1783 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D0 0x00000001 |
Definition at line 7863 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D1 0x00000002 |
Definition at line 7861 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D10 0x00000400 |
Definition at line 7843 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D11 0x00000800 |
Definition at line 7841 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D12 0x00001000 |
Definition at line 7839 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D13 0x00002000 |
Definition at line 7837 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D14 0x00004000 |
Definition at line 7835 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D2 0x00000004 |
Definition at line 7859 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D3 0x00000008 |
Definition at line 7857 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D4 0x00000010 |
Definition at line 7855 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D5 0x00000020 |
Definition at line 7853 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D6 0x00000040 |
Definition at line 7851 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D7 0x00000080 |
Definition at line 7849 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D8 0x00000100 |
Definition at line 7847 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_D9 0x00000200 |
Definition at line 7845 of file cortex-m4-def.h.
| #define SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808)) |
Definition at line 1773 of file cortex-m4-def.h.
| #define SYSCTL_DCGCHIB_D0 0x00000001 |
Definition at line 7879 of file cortex-m4-def.h.
| #define SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814)) |
Definition at line 1775 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D0 0x00000001 |
Definition at line 7934 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D1 0x00000002 |
Definition at line 7932 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D2 0x00000004 |
Definition at line 7930 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D3 0x00000008 |
Definition at line 7928 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D4 0x00000010 |
Definition at line 7926 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_D5 0x00000020 |
Definition at line 7924 of file cortex-m4-def.h.
| #define SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820)) |
Definition at line 1778 of file cortex-m4-def.h.
| #define SYSCTL_DCGCSSI_D0 0x00000001 |
Definition at line 7916 of file cortex-m4-def.h.
| #define SYSCTL_DCGCSSI_D1 0x00000002 |
Definition at line 7914 of file cortex-m4-def.h.
| #define SYSCTL_DCGCSSI_D2 0x00000004 |
Definition at line 7912 of file cortex-m4-def.h.
| #define SYSCTL_DCGCSSI_D3 0x00000008 |
Definition at line 7910 of file cortex-m4-def.h.
| #define SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C)) |
Definition at line 1777 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D0 0x00000001 |
Definition at line 7826 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D1 0x00000002 |
Definition at line 7824 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D2 0x00000004 |
Definition at line 7822 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D3 0x00000008 |
Definition at line 7820 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D4 0x00000010 |
Definition at line 7818 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_D5 0x00000020 |
Definition at line 7816 of file cortex-m4-def.h.
| #define SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804)) |
Definition at line 1772 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D0 0x00000001 |
Definition at line 7902 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D1 0x00000002 |
Definition at line 7900 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D2 0x00000004 |
Definition at line 7898 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D3 0x00000008 |
Definition at line 7896 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D4 0x00000010 |
Definition at line 7894 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D5 0x00000020 |
Definition at line 7892 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D6 0x00000040 |
Definition at line 7890 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_D7 0x00000080 |
Definition at line 7888 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818)) |
Definition at line 1776 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUSB_D0 0x00000001 |
Definition at line 7942 of file cortex-m4-def.h.
| #define SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828)) |
Definition at line 1779 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWD_D0 0x00000001 |
Definition at line 7807 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWD_D1 0x00000002 |
Definition at line 7805 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800)) |
Definition at line 1771 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D0 0x00000001 |
Definition at line 8000 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D1 0x00000002 |
Definition at line 7998 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D2 0x00000004 |
Definition at line 7996 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D3 0x00000008 |
Definition at line 7994 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D4 0x00000010 |
Definition at line 7992 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_D5 0x00000020 |
Definition at line 7990 of file cortex-m4-def.h.
| #define SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C)) |
Definition at line 1784 of file cortex-m4-def.h.
| #define SYSCTL_DID0_CLASS_BLIZZARD 0x00050000 |
Definition at line 6215 of file cortex-m4-def.h.
| #define SYSCTL_DID0_CLASS_M 0x00FF0000 |
Definition at line 6214 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MAJ_M 0x0000FF00 |
Definition at line 6218 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MAJ_REVA 0x00000000 |
Definition at line 6219 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MAJ_REVB 0x00000100 |
Definition at line 6220 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MAJ_REVC 0x00000200 |
Definition at line 6222 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MIN_0 0x00000000 |
Definition at line 6225 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MIN_1 0x00000001 |
Definition at line 6227 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MIN_2 0x00000002 |
Definition at line 6228 of file cortex-m4-def.h.
| #define SYSCTL_DID0_MIN_M 0x000000FF |
Definition at line 6224 of file cortex-m4-def.h.
| #define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000)) |
Definition at line 1672 of file cortex-m4-def.h.
| #define SYSCTL_DID0_VER_1 0x10000000 |
Definition at line 6212 of file cortex-m4-def.h.
| #define SYSCTL_DID0_VER_M 0x70000000 |
Definition at line 6211 of file cortex-m4-def.h.
| #define SYSCTL_DID1_FAM_M 0x0F000000 |
Definition at line 6241 of file cortex-m4-def.h.
| #define SYSCTL_DID1_FAM_STELLARIS 0x00000000 |
Definition at line 6242 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_100 0x00004000 |
Definition at line 6253 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_144 0x00008000 |
Definition at line 6255 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_157 0x0000A000 |
Definition at line 6256 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_28 0x00000000 |
Definition at line 6251 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_48 0x00002000 |
Definition at line 6252 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_64 0x00006000 |
Definition at line 6254 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PINCNT_M 0x0000E000 |
Definition at line 6250 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PKG_BGA 0x00000010 |
Definition at line 6267 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PKG_M 0x00000018 |
Definition at line 6264 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PKG_QFP 0x00000008 |
Definition at line 6266 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PKG_SOIC 0x00000000 |
Definition at line 6265 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PRTNO_LM4F120H5QR 0x00040000 |
Definition at line 6248 of file cortex-m4-def.h.
| #define SYSCTL_DID1_PRTNO_M 0x00FF0000 |
Definition at line 6247 of file cortex-m4-def.h.
| #define SYSCTL_DID1_QUAL_ES 0x00000000 |
Definition at line 6270 of file cortex-m4-def.h.
| #define SYSCTL_DID1_QUAL_FQ 0x00000002 |
Definition at line 6272 of file cortex-m4-def.h.
| #define SYSCTL_DID1_QUAL_M 0x00000003 |
Definition at line 6269 of file cortex-m4-def.h.
| #define SYSCTL_DID1_QUAL_PP 0x00000001 |
Definition at line 6271 of file cortex-m4-def.h.
| #define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004)) |
Definition at line 1673 of file cortex-m4-def.h.
| #define SYSCTL_DID1_ROHS 0x00000004 |
Definition at line 6268 of file cortex-m4-def.h.
| #define SYSCTL_DID1_TEMP_C 0x00000000 |
Definition at line 6258 of file cortex-m4-def.h.
| #define SYSCTL_DID1_TEMP_E 0x00000040 |
Definition at line 6262 of file cortex-m4-def.h.
| #define SYSCTL_DID1_TEMP_I 0x00000020 |
Definition at line 6260 of file cortex-m4-def.h.
| #define SYSCTL_DID1_TEMP_M 0x000000E0 |
Definition at line 6257 of file cortex-m4-def.h.
| #define SYSCTL_DID1_VER_0 0x00000000 |
Definition at line 6236 of file cortex-m4-def.h.
| #define SYSCTL_DID1_VER_1 0x10000000 |
Definition at line 6239 of file cortex-m4-def.h.
| #define SYSCTL_DID1_VER_M 0xF0000000 |
Definition at line 6235 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_1 0x00000000 |
Definition at line 6986 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_2 0x00800000 |
Definition at line 6987 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_3 0x01000000 |
Definition at line 6988 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_4 0x01800000 |
Definition at line 6989 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 |
Definition at line 6990 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 |
Definition at line 6985 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 |
Definition at line 6994 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 |
Definition at line 6995 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 |
Definition at line 6992 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 |
Definition at line 6993 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_O_M 0x00000070 |
Definition at line 6991 of file cortex-m4-def.h.
| #define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144)) |
Definition at line 1704 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTA 0x00000001 |
Definition at line 6708 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTB 0x00000002 |
Definition at line 6706 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTC 0x00000004 |
Definition at line 6704 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTD 0x00000008 |
Definition at line 6702 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTE 0x00000010 |
Definition at line 6700 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_PORTF 0x00000020 |
Definition at line 6698 of file cortex-m4-def.h.
| #define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C)) |
Definition at line 1692 of file cortex-m4-def.h.
| #define SYSCTL_IMC_BORIM 0x00000002 |
Definition at line 6622 of file cortex-m4-def.h.
| #define SYSCTL_IMC_MOFIM 0x00000008 |
Definition at line 6620 of file cortex-m4-def.h.
| #define SYSCTL_IMC_MOSCPUPIM 0x00000100 |
Definition at line 6617 of file cortex-m4-def.h.
| #define SYSCTL_IMC_PLLLIM 0x00000040 |
Definition at line 6619 of file cortex-m4-def.h.
| #define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054)) |
Definition at line 1688 of file cortex-m4-def.h.
| #define SYSCTL_IMC_USBPLLLIM 0x00000080 |
Definition at line 6618 of file cortex-m4-def.h.
| #define SYSCTL_MISC_BORMIS 0x00000002 |
Definition at line 6636 of file cortex-m4-def.h.
| #define SYSCTL_MISC_MOFMIS 0x00000008 |
Definition at line 6634 of file cortex-m4-def.h.
| #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 |
Definition at line 6629 of file cortex-m4-def.h.
| #define SYSCTL_MISC_PLLLMIS 0x00000040 |
Definition at line 6633 of file cortex-m4-def.h.
| #define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058)) |
Definition at line 1689 of file cortex-m4-def.h.
| #define SYSCTL_MISC_USBPLLLMIS 0x00000080 |
Definition at line 6631 of file cortex-m4-def.h.
| #define SYSCTL_MOSCCTL_CVAL 0x00000001 |
Definition at line 6802 of file cortex-m4-def.h.
| #define SYSCTL_MOSCCTL_MOSCIM 0x00000002 |
Definition at line 6801 of file cortex-m4-def.h.
| #define SYSCTL_MOSCCTL_NOXTAL 0x00000004 |
Definition at line 6800 of file cortex-m4-def.h.
| #define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C)) |
Definition at line 1694 of file cortex-m4-def.h.
| #define SYSCTL_NVMSTAT_FWB 0x00000001 |
Definition at line 7091 of file cortex-m4-def.h.
| #define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0)) |
Definition at line 1712 of file cortex-m4-def.h.
| #define SYSCTL_NVMSTAT_TPSW 0x00000010 |
Definition at line 7090 of file cortex-m4-def.h.
| #define SYSCTL_PBORCTL_BORIOR 0x00000002 |
Definition at line 6542 of file cortex-m4-def.h.
| #define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030)) |
Definition at line 1683 of file cortex-m4-def.h.
| #define SYSCTL_PCACMP_P0 0x00000001 |
Definition at line 8122 of file cortex-m4-def.h.
| #define SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C)) |
Definition at line 1796 of file cortex-m4-def.h.
| #define SYSCTL_PCADC_P0 0x00000001 |
Definition at line 8115 of file cortex-m4-def.h.
| #define SYSCTL_PCADC_P1 0x00000002 |
Definition at line 8114 of file cortex-m4-def.h.
| #define SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938)) |
Definition at line 1795 of file cortex-m4-def.h.
| #define SYSCTL_PCCAN_P0 0x00000001 |
Definition at line 8107 of file cortex-m4-def.h.
| #define SYSCTL_PCCAN_P1 0x00000002 |
Definition at line 8106 of file cortex-m4-def.h.
| #define SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934)) |
Definition at line 1794 of file cortex-m4-def.h.
| #define SYSCTL_PCDMA_P0 0x00000001 |
Definition at line 8049 of file cortex-m4-def.h.
| #define SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C)) |
Definition at line 1788 of file cortex-m4-def.h.
| #define SYSCTL_PCEEPROM_P0 0x00000001 |
Definition at line 8131 of file cortex-m4-def.h.
| #define SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958)) |
Definition at line 1797 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P0 0x00000001 |
Definition at line 8042 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P1 0x00000002 |
Definition at line 8041 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P10 0x00000400 |
Definition at line 8032 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P11 0x00000800 |
Definition at line 8031 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P12 0x00001000 |
Definition at line 8030 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P13 0x00002000 |
Definition at line 8029 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P14 0x00004000 |
Definition at line 8028 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P2 0x00000004 |
Definition at line 8040 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P3 0x00000008 |
Definition at line 8039 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P4 0x00000010 |
Definition at line 8038 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P5 0x00000020 |
Definition at line 8037 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P6 0x00000040 |
Definition at line 8036 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P7 0x00000080 |
Definition at line 8035 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P8 0x00000100 |
Definition at line 8034 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_P9 0x00000200 |
Definition at line 8033 of file cortex-m4-def.h.
| #define SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908)) |
Definition at line 1787 of file cortex-m4-def.h.
| #define SYSCTL_PCHIB_P0 0x00000001 |
Definition at line 8056 of file cortex-m4-def.h.
| #define SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914)) |
Definition at line 1789 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P0 0x00000001 |
Definition at line 8092 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P1 0x00000002 |
Definition at line 8091 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P2 0x00000004 |
Definition at line 8090 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P3 0x00000008 |
Definition at line 8089 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P4 0x00000010 |
Definition at line 8088 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_P5 0x00000020 |
Definition at line 8087 of file cortex-m4-def.h.
| #define SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920)) |
Definition at line 1792 of file cortex-m4-def.h.
| #define SYSCTL_PCSSI_P0 0x00000001 |
Definition at line 8080 of file cortex-m4-def.h.
| #define SYSCTL_PCSSI_P1 0x00000002 |
Definition at line 8079 of file cortex-m4-def.h.
| #define SYSCTL_PCSSI_P2 0x00000004 |
Definition at line 8078 of file cortex-m4-def.h.
| #define SYSCTL_PCSSI_P3 0x00000008 |
Definition at line 8077 of file cortex-m4-def.h.
| #define SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C)) |
Definition at line 1791 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P0 0x00000001 |
Definition at line 8021 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P1 0x00000002 |
Definition at line 8020 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P2 0x00000004 |
Definition at line 8019 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P3 0x00000008 |
Definition at line 8018 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P4 0x00000010 |
Definition at line 8017 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_P5 0x00000020 |
Definition at line 8016 of file cortex-m4-def.h.
| #define SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904)) |
Definition at line 1786 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P0 0x00000001 |
Definition at line 8070 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P1 0x00000002 |
Definition at line 8069 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P2 0x00000004 |
Definition at line 8068 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P3 0x00000008 |
Definition at line 8067 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P4 0x00000010 |
Definition at line 8066 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P5 0x00000020 |
Definition at line 8065 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P6 0x00000040 |
Definition at line 8064 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_P7 0x00000080 |
Definition at line 8063 of file cortex-m4-def.h.
| #define SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918)) |
Definition at line 1790 of file cortex-m4-def.h.
| #define SYSCTL_PCUSB_P0 0x00000001 |
Definition at line 8099 of file cortex-m4-def.h.
| #define SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928)) |
Definition at line 1793 of file cortex-m4-def.h.
| #define SYSCTL_PCWD_P0 0x00000001 |
Definition at line 8009 of file cortex-m4-def.h.
| #define SYSCTL_PCWD_P1 0x00000002 |
Definition at line 8008 of file cortex-m4-def.h.
| #define SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900)) |
Definition at line 1785 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P0 0x00000001 |
Definition at line 8144 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P1 0x00000002 |
Definition at line 8143 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P2 0x00000004 |
Definition at line 8142 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P3 0x00000008 |
Definition at line 8141 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P4 0x00000010 |
Definition at line 8140 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_P5 0x00000020 |
Definition at line 8139 of file cortex-m4-def.h.
| #define SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C)) |
Definition at line 1798 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_CAL 0x00000200 |
Definition at line 7011 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150)) |
Definition at line 1706 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 |
Definition at line 7012 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_UT_M 0x0000007F |
Definition at line 7013 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_UT_S 0 |
Definition at line 7014 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCCAL_UTEN 0x80000000 |
Definition at line 7010 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 |
Definition at line 7023 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 |
Definition at line 7028 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 |
Definition at line 7024 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 |
Definition at line 7026 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F |
Definition at line 7030 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_CT_S 0 |
Definition at line 7032 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 |
Definition at line 7022 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_DT_S 16 |
Definition at line 7031 of file cortex-m4-def.h.
| #define SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154)) |
Definition at line 1707 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 |
Definition at line 7040 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ0_MFRAC_S 10 |
Definition at line 7042 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ0_MINT_M 0x000003FF |
Definition at line 7041 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ0_MINT_S 0 |
Definition at line 7043 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160)) |
Definition at line 1708 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ1_N_M 0x0000001F |
Definition at line 7052 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ1_N_S 0 |
Definition at line 7054 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ1_Q_M 0x00001F00 |
Definition at line 7051 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ1_Q_S 8 |
Definition at line 7053 of file cortex-m4-def.h.
| #define SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164)) |
Definition at line 1709 of file cortex-m4-def.h.
| #define SYSCTL_PLLSTAT_LOCK 0x00000001 |
Definition at line 7061 of file cortex-m4-def.h.
| #define SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168)) |
Definition at line 1710 of file cortex-m4-def.h.
| #define SYSCTL_PPACMP_P0 0x00000001 |
Definition at line 7213 of file cortex-m4-def.h.
| #define SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C)) |
Definition at line 1724 of file cortex-m4-def.h.
| #define SYSCTL_PPADC_P0 0x00000001 |
Definition at line 7206 of file cortex-m4-def.h.
| #define SYSCTL_PPADC_P1 0x00000002 |
Definition at line 7205 of file cortex-m4-def.h.
| #define SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338)) |
Definition at line 1723 of file cortex-m4-def.h.
| #define SYSCTL_PPCAN_P0 0x00000001 |
Definition at line 7198 of file cortex-m4-def.h.
| #define SYSCTL_PPCAN_P1 0x00000002 |
Definition at line 7197 of file cortex-m4-def.h.
| #define SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334)) |
Definition at line 1722 of file cortex-m4-def.h.
| #define SYSCTL_PPDMA_P0 0x00000001 |
Definition at line 7140 of file cortex-m4-def.h.
| #define SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C)) |
Definition at line 1716 of file cortex-m4-def.h.
| #define SYSCTL_PPEEPROM_P0 0x00000001 |
Definition at line 7237 of file cortex-m4-def.h.
| #define SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358)) |
Definition at line 1727 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P0 0x00000001 |
Definition at line 7133 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P1 0x00000002 |
Definition at line 7132 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P10 0x00000400 |
Definition at line 7123 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P11 0x00000800 |
Definition at line 7122 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P12 0x00001000 |
Definition at line 7121 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P13 0x00002000 |
Definition at line 7120 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P14 0x00004000 |
Definition at line 7119 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P2 0x00000004 |
Definition at line 7131 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P3 0x00000008 |
Definition at line 7130 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P4 0x00000010 |
Definition at line 7129 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P5 0x00000020 |
Definition at line 7128 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P6 0x00000040 |
Definition at line 7127 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P7 0x00000080 |
Definition at line 7126 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P8 0x00000100 |
Definition at line 7125 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_P9 0x00000200 |
Definition at line 7124 of file cortex-m4-def.h.
| #define SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308)) |
Definition at line 1715 of file cortex-m4-def.h.
| #define SYSCTL_PPHIB_P0 0x00000001 |
Definition at line 7147 of file cortex-m4-def.h.
| #define SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314)) |
Definition at line 1717 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P0 0x00000001 |
Definition at line 7183 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P1 0x00000002 |
Definition at line 7182 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P2 0x00000004 |
Definition at line 7181 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P3 0x00000008 |
Definition at line 7180 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P4 0x00000010 |
Definition at line 7179 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_P5 0x00000020 |
Definition at line 7178 of file cortex-m4-def.h.
| #define SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320)) |
Definition at line 1720 of file cortex-m4-def.h.
| #define SYSCTL_PPPWM_P0 0x00000001 |
Definition at line 7221 of file cortex-m4-def.h.
| #define SYSCTL_PPPWM_P1 0x00000002 |
Definition at line 7220 of file cortex-m4-def.h.
| #define SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340)) |
Definition at line 1725 of file cortex-m4-def.h.
| #define SYSCTL_PPQEI_P0 0x00000001 |
Definition at line 7229 of file cortex-m4-def.h.
| #define SYSCTL_PPQEI_P1 0x00000002 |
Definition at line 7228 of file cortex-m4-def.h.
| #define SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344)) |
Definition at line 1726 of file cortex-m4-def.h.
| #define SYSCTL_PPSSI_P0 0x00000001 |
Definition at line 7171 of file cortex-m4-def.h.
| #define SYSCTL_PPSSI_P1 0x00000002 |
Definition at line 7170 of file cortex-m4-def.h.
| #define SYSCTL_PPSSI_P2 0x00000004 |
Definition at line 7169 of file cortex-m4-def.h.
| #define SYSCTL_PPSSI_P3 0x00000008 |
Definition at line 7168 of file cortex-m4-def.h.
| #define SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C)) |
Definition at line 1719 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P0 0x00000001 |
Definition at line 7112 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P1 0x00000002 |
Definition at line 7111 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P2 0x00000004 |
Definition at line 7110 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P3 0x00000008 |
Definition at line 7109 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P4 0x00000010 |
Definition at line 7108 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_P5 0x00000020 |
Definition at line 7107 of file cortex-m4-def.h.
| #define SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304)) |
Definition at line 1714 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P0 0x00000001 |
Definition at line 7161 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P1 0x00000002 |
Definition at line 7160 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P2 0x00000004 |
Definition at line 7159 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P3 0x00000008 |
Definition at line 7158 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P4 0x00000010 |
Definition at line 7157 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P5 0x00000020 |
Definition at line 7156 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P6 0x00000040 |
Definition at line 7155 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_P7 0x00000080 |
Definition at line 7154 of file cortex-m4-def.h.
| #define SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318)) |
Definition at line 1718 of file cortex-m4-def.h.
| #define SYSCTL_PPUSB_P0 0x00000001 |
Definition at line 7190 of file cortex-m4-def.h.
| #define SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328)) |
Definition at line 1721 of file cortex-m4-def.h.
| #define SYSCTL_PPWD_P0 0x00000001 |
Definition at line 7100 of file cortex-m4-def.h.
| #define SYSCTL_PPWD_P1 0x00000002 |
Definition at line 7099 of file cortex-m4-def.h.
| #define SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300)) |
Definition at line 1713 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P0 0x00000001 |
Definition at line 7250 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P1 0x00000002 |
Definition at line 7249 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P2 0x00000004 |
Definition at line 7248 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P3 0x00000008 |
Definition at line 7247 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P4 0x00000010 |
Definition at line 7246 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_P5 0x00000020 |
Definition at line 7245 of file cortex-m4-def.h.
| #define SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C)) |
Definition at line 1728 of file cortex-m4-def.h.
| #define SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C)) |
Definition at line 1810 of file cortex-m4-def.h.
| #define SYSCTL_PRACMP_R0 0x00000001 |
Definition at line 8268 of file cortex-m4-def.h.
| #define SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38)) |
Definition at line 1809 of file cortex-m4-def.h.
| #define SYSCTL_PRADC_R0 0x00000001 |
Definition at line 8261 of file cortex-m4-def.h.
| #define SYSCTL_PRADC_R1 0x00000002 |
Definition at line 8260 of file cortex-m4-def.h.
| #define SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34)) |
Definition at line 1808 of file cortex-m4-def.h.
| #define SYSCTL_PRCAN_R0 0x00000001 |
Definition at line 8253 of file cortex-m4-def.h.
| #define SYSCTL_PRCAN_R1 0x00000002 |
Definition at line 8252 of file cortex-m4-def.h.
| #define SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C)) |
Definition at line 1802 of file cortex-m4-def.h.
| #define SYSCTL_PRDMA_R0 0x00000001 |
Definition at line 8194 of file cortex-m4-def.h.
| #define SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58)) |
Definition at line 1811 of file cortex-m4-def.h.
| #define SYSCTL_PREEPROM_R0 0x00000001 |
Definition at line 8277 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08)) |
Definition at line 1801 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R0 0x00000001 |
Definition at line 8187 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R1 0x00000002 |
Definition at line 8186 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R10 0x00000400 |
Definition at line 8177 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R11 0x00000800 |
Definition at line 8176 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R12 0x00001000 |
Definition at line 8175 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R13 0x00002000 |
Definition at line 8174 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R14 0x00004000 |
Definition at line 8173 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R2 0x00000004 |
Definition at line 8185 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R3 0x00000008 |
Definition at line 8184 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R4 0x00000010 |
Definition at line 8183 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R5 0x00000020 |
Definition at line 8182 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R6 0x00000040 |
Definition at line 8181 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R7 0x00000080 |
Definition at line 8180 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R8 0x00000100 |
Definition at line 8179 of file cortex-m4-def.h.
| #define SYSCTL_PRGPIO_R9 0x00000200 |
Definition at line 8178 of file cortex-m4-def.h.
| #define SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14)) |
Definition at line 1803 of file cortex-m4-def.h.
| #define SYSCTL_PRHIB_R0 0x00000001 |
Definition at line 8201 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20)) |
Definition at line 1806 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R0 0x00000001 |
Definition at line 8238 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R1 0x00000002 |
Definition at line 8237 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R2 0x00000004 |
Definition at line 8236 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R3 0x00000008 |
Definition at line 8235 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R4 0x00000010 |
Definition at line 8234 of file cortex-m4-def.h.
| #define SYSCTL_PRI2C_R5 0x00000020 |
Definition at line 8233 of file cortex-m4-def.h.
| #define SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C)) |
Definition at line 1805 of file cortex-m4-def.h.
| #define SYSCTL_PRSSI_R0 0x00000001 |
Definition at line 8226 of file cortex-m4-def.h.
| #define SYSCTL_PRSSI_R1 0x00000002 |
Definition at line 8225 of file cortex-m4-def.h.
| #define SYSCTL_PRSSI_R2 0x00000004 |
Definition at line 8224 of file cortex-m4-def.h.
| #define SYSCTL_PRSSI_R3 0x00000008 |
Definition at line 8223 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04)) |
Definition at line 1800 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R0 0x00000001 |
Definition at line 8166 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R1 0x00000002 |
Definition at line 8165 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R2 0x00000004 |
Definition at line 8164 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R3 0x00000008 |
Definition at line 8163 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R4 0x00000010 |
Definition at line 8162 of file cortex-m4-def.h.
| #define SYSCTL_PRTIMER_R5 0x00000020 |
Definition at line 8161 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18)) |
Definition at line 1804 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R0 0x00000001 |
Definition at line 8216 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R1 0x00000002 |
Definition at line 8215 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R2 0x00000004 |
Definition at line 8214 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R3 0x00000008 |
Definition at line 8213 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R4 0x00000010 |
Definition at line 8212 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R5 0x00000020 |
Definition at line 8211 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R6 0x00000040 |
Definition at line 8210 of file cortex-m4-def.h.
| #define SYSCTL_PRUART_R7 0x00000080 |
Definition at line 8209 of file cortex-m4-def.h.
| #define SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28)) |
Definition at line 1807 of file cortex-m4-def.h.
| #define SYSCTL_PRUSB_R0 0x00000001 |
Definition at line 8245 of file cortex-m4-def.h.
| #define SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00)) |
Definition at line 1799 of file cortex-m4-def.h.
| #define SYSCTL_PRWD_R0 0x00000001 |
Definition at line 8153 of file cortex-m4-def.h.
| #define SYSCTL_PRWD_R1 0x00000002 |
Definition at line 8151 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C)) |
Definition at line 1812 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R0 0x00000001 |
Definition at line 8290 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R1 0x00000002 |
Definition at line 8289 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R2 0x00000004 |
Definition at line 8288 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R3 0x00000008 |
Definition at line 8287 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R4 0x00000010 |
Definition at line 8286 of file cortex-m4-def.h.
| #define SYSCTL_PRWTIMER_R5 0x00000020 |
Definition at line 8285 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_BYPASS2 0x00000800 |
Definition at line 6786 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_DIV400 0x40000000 |
Definition at line 6717 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_30 0x00000030 |
Definition at line 6791 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_32 0x00000070 |
Definition at line 6792 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 |
Definition at line 6789 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 |
Definition at line 6790 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_M 0x00000070 |
Definition at line 6787 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 |
Definition at line 6788 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_PWRDN2 0x00002000 |
Definition at line 6785 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070)) |
Definition at line 1693 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_10 0x04800000 |
Definition at line 6728 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_11 0x05000000 |
Definition at line 6729 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_12 0x05800000 |
Definition at line 6730 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_13 0x06000000 |
Definition at line 6731 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_14 0x06800000 |
Definition at line 6732 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_15 0x07000000 |
Definition at line 6733 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_16 0x07800000 |
Definition at line 6734 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_17 0x08000000 |
Definition at line 6735 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_18 0x08800000 |
Definition at line 6736 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_19 0x09000000 |
Definition at line 6737 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_2 0x00800000 |
Definition at line 6720 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_20 0x09800000 |
Definition at line 6738 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 |
Definition at line 6739 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 |
Definition at line 6740 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 |
Definition at line 6741 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 |
Definition at line 6742 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 |
Definition at line 6743 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 |
Definition at line 6744 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 |
Definition at line 6745 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 |
Definition at line 6746 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 |
Definition at line 6747 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_3 0x01000000 |
Definition at line 6721 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 |
Definition at line 6748 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 |
Definition at line 6749 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 |
Definition at line 6750 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_33 0x10000000 |
Definition at line 6751 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_34 0x10800000 |
Definition at line 6752 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_35 0x11000000 |
Definition at line 6753 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_36 0x11800000 |
Definition at line 6754 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_37 0x12000000 |
Definition at line 6755 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_38 0x12800000 |
Definition at line 6756 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_39 0x13000000 |
Definition at line 6757 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_4 0x01800000 |
Definition at line 6722 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_40 0x13800000 |
Definition at line 6758 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_41 0x14000000 |
Definition at line 6759 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_42 0x14800000 |
Definition at line 6760 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_43 0x15000000 |
Definition at line 6761 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_44 0x15800000 |
Definition at line 6762 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_45 0x16000000 |
Definition at line 6763 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_46 0x16800000 |
Definition at line 6764 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_47 0x17000000 |
Definition at line 6765 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_48 0x17800000 |
Definition at line 6766 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_49 0x18000000 |
Definition at line 6767 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_5 0x02000000 |
Definition at line 6723 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_50 0x18800000 |
Definition at line 6768 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_51 0x19000000 |
Definition at line 6769 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_52 0x19800000 |
Definition at line 6770 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 |
Definition at line 6771 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 |
Definition at line 6772 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 |
Definition at line 6773 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 |
Definition at line 6774 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 |
Definition at line 6775 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 |
Definition at line 6776 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 |
Definition at line 6777 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_6 0x02800000 |
Definition at line 6724 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 |
Definition at line 6778 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 |
Definition at line 6779 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 |
Definition at line 6780 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 |
Definition at line 6781 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 |
Definition at line 6782 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_7 0x03000000 |
Definition at line 6725 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_8 0x03800000 |
Definition at line 6726 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_9 0x04000000 |
Definition at line 6727 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 |
Definition at line 6719 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2_S 23 |
Definition at line 6793 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 |
Definition at line 6783 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_USBPWRDN 0x00004000 |
Definition at line 6784 of file cortex-m4-def.h.
| #define SYSCTL_RCC2_USERCC2 0x80000000 |
Definition at line 6716 of file cortex-m4-def.h.
| #define SYSCTL_RCC_ACG 0x08000000 |
Definition at line 6656 of file cortex-m4-def.h.
| #define SYSCTL_RCC_BYPASS 0x00000800 |
Definition at line 6660 of file cortex-m4-def.h.
| #define SYSCTL_RCC_IOSCDIS 0x00000002 |
Definition at line 6688 of file cortex-m4-def.h.
| #define SYSCTL_RCC_MOSCDIS 0x00000001 |
Definition at line 6689 of file cortex-m4-def.h.
| #define SYSCTL_RCC_OSCSRC_30 0x00000030 |
Definition at line 6687 of file cortex-m4-def.h.
| #define SYSCTL_RCC_OSCSRC_INT 0x00000010 |
Definition at line 6685 of file cortex-m4-def.h.
| #define SYSCTL_RCC_OSCSRC_INT4 0x00000020 |
Definition at line 6686 of file cortex-m4-def.h.
| #define SYSCTL_RCC_OSCSRC_M 0x00000030 |
Definition at line 6683 of file cortex-m4-def.h.
| #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 |
Definition at line 6684 of file cortex-m4-def.h.
| #define SYSCTL_RCC_PWRDN 0x00002000 |
Definition at line 6659 of file cortex-m4-def.h.
| #define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060)) |
Definition at line 1691 of file cortex-m4-def.h.
| #define SYSCTL_RCC_SYSDIV_M 0x07800000 |
Definition at line 6657 of file cortex-m4-def.h.
| #define SYSCTL_RCC_SYSDIV_S 23 |
Definition at line 6690 of file cortex-m4-def.h.
| #define SYSCTL_RCC_USESYSDIV 0x00400000 |
Definition at line 6658 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_10MHZ 0x00000400 |
Definition at line 6672 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 |
Definition at line 6674 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_12MHZ 0x00000440 |
Definition at line 6673 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 |
Definition at line 6675 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 |
Definition at line 6676 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 |
Definition at line 6678 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_16MHZ 0x00000540 |
Definition at line 6677 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 |
Definition at line 6679 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_20MHZ 0x00000600 |
Definition at line 6680 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_24MHZ 0x00000640 |
Definition at line 6681 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_25MHZ 0x00000680 |
Definition at line 6682 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 |
Definition at line 6663 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 |
Definition at line 6664 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_4MHZ 0x00000180 |
Definition at line 6662 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 |
Definition at line 6666 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 |
Definition at line 6665 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 |
Definition at line 6668 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 |
Definition at line 6667 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 |
Definition at line 6669 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 |
Definition at line 6671 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 |
Definition at line 6670 of file cortex-m4-def.h.
| #define SYSCTL_RCC_XTAL_M 0x000007C0 |
Definition at line 6661 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0 0x00010000 |
Definition at line 6814 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0SPD_125K 0x00000000 |
Definition at line 6824 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 |
Definition at line 6830 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0SPD_250K 0x00000100 |
Definition at line 6826 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0SPD_500K 0x00000200 |
Definition at line 6828 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 |
Definition at line 6823 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1 0x00020000 |
Definition at line 6813 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1SPD_125K 0x00000000 |
Definition at line 6816 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 |
Definition at line 6822 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1SPD_250K 0x00000400 |
Definition at line 6818 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1SPD_500K 0x00000800 |
Definition at line 6820 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 |
Definition at line 6815 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_CAN0 0x01000000 |
Definition at line 6811 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_CAN1 0x02000000 |
Definition at line 6810 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_HIB 0x00000040 |
Definition at line 6831 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_PWM0 0x00100000 |
Definition at line 6812 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100)) |
Definition at line 1695 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_WDT0 0x00000008 |
Definition at line 6832 of file cortex-m4-def.h.
| #define SYSCTL_RCGC0_WDT1 0x10000000 |
Definition at line 6809 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_COMP0 0x01000000 |
Definition at line 6841 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_COMP1 0x02000000 |
Definition at line 6840 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_COMP2 0x04000000 |
Definition at line 6839 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_I2C0 0x00001000 |
Definition at line 6847 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_I2C1 0x00004000 |
Definition at line 6846 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_QEI0 0x00000100 |
Definition at line 6849 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_QEI1 0x00000200 |
Definition at line 6848 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) |
Definition at line 1696 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_SSI0 0x00000010 |
Definition at line 6851 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_SSI1 0x00000020 |
Definition at line 6850 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_TIMER0 0x00010000 |
Definition at line 6845 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_TIMER1 0x00020000 |
Definition at line 6844 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_TIMER2 0x00040000 |
Definition at line 6843 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_TIMER3 0x00080000 |
Definition at line 6842 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_UART0 0x00000001 |
Definition at line 6854 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_UART1 0x00000002 |
Definition at line 6853 of file cortex-m4-def.h.
| #define SYSCTL_RCGC1_UART2 0x00000004 |
Definition at line 6852 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOA 0x00000001 |
Definition at line 6871 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOB 0x00000002 |
Definition at line 6870 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOC 0x00000004 |
Definition at line 6869 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOD 0x00000008 |
Definition at line 6868 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOE 0x00000010 |
Definition at line 6867 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOF 0x00000020 |
Definition at line 6866 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOG 0x00000040 |
Definition at line 6865 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOH 0x00000080 |
Definition at line 6864 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_GPIOJ 0x00000100 |
Definition at line 6863 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108)) |
Definition at line 1697 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_UDMA 0x00002000 |
Definition at line 6862 of file cortex-m4-def.h.
| #define SYSCTL_RCGC2_USB0 0x00010000 |
Definition at line 6861 of file cortex-m4-def.h.
| #define SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C)) |
Definition at line 1754 of file cortex-m4-def.h.
| #define SYSCTL_RCGCACMP_R0 0x00000001 |
Definition at line 7567 of file cortex-m4-def.h.
| #define SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638)) |
Definition at line 1753 of file cortex-m4-def.h.
| #define SYSCTL_RCGCADC_R0 0x00000001 |
Definition at line 7558 of file cortex-m4-def.h.
| #define SYSCTL_RCGCADC_R1 0x00000002 |
Definition at line 7556 of file cortex-m4-def.h.
| #define SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634)) |
Definition at line 1752 of file cortex-m4-def.h.
| #define SYSCTL_RCGCCAN_R0 0x00000001 |
Definition at line 7548 of file cortex-m4-def.h.
| #define SYSCTL_RCGCCAN_R1 0x00000002 |
Definition at line 7546 of file cortex-m4-def.h.
| #define SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C)) |
Definition at line 1746 of file cortex-m4-def.h.
| #define SYSCTL_RCGCDMA_R0 0x00000001 |
Definition at line 7467 of file cortex-m4-def.h.
| #define SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658)) |
Definition at line 1755 of file cortex-m4-def.h.
| #define SYSCTL_RCGCEEPROM_R0 0x00000001 |
Definition at line 7576 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608)) |
Definition at line 1745 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R0 0x00000001 |
Definition at line 7459 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R1 0x00000002 |
Definition at line 7457 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R10 0x00000400 |
Definition at line 7439 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R11 0x00000800 |
Definition at line 7437 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R12 0x00001000 |
Definition at line 7435 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R13 0x00002000 |
Definition at line 7433 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R14 0x00004000 |
Definition at line 7431 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R2 0x00000004 |
Definition at line 7455 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R3 0x00000008 |
Definition at line 7453 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R4 0x00000010 |
Definition at line 7451 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R5 0x00000020 |
Definition at line 7449 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R6 0x00000040 |
Definition at line 7447 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R7 0x00000080 |
Definition at line 7445 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R8 0x00000100 |
Definition at line 7443 of file cortex-m4-def.h.
| #define SYSCTL_RCGCGPIO_R9 0x00000200 |
Definition at line 7441 of file cortex-m4-def.h.
| #define SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614)) |
Definition at line 1747 of file cortex-m4-def.h.
| #define SYSCTL_RCGCHIB_R0 0x00000001 |
Definition at line 7475 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620)) |
Definition at line 1750 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R0 0x00000001 |
Definition at line 7530 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R1 0x00000002 |
Definition at line 7528 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R2 0x00000004 |
Definition at line 7526 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R3 0x00000008 |
Definition at line 7524 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R4 0x00000010 |
Definition at line 7522 of file cortex-m4-def.h.
| #define SYSCTL_RCGCI2C_R5 0x00000020 |
Definition at line 7520 of file cortex-m4-def.h.
| #define SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C)) |
Definition at line 1749 of file cortex-m4-def.h.
| #define SYSCTL_RCGCSSI_R0 0x00000001 |
Definition at line 7512 of file cortex-m4-def.h.
| #define SYSCTL_RCGCSSI_R1 0x00000002 |
Definition at line 7510 of file cortex-m4-def.h.
| #define SYSCTL_RCGCSSI_R2 0x00000004 |
Definition at line 7508 of file cortex-m4-def.h.
| #define SYSCTL_RCGCSSI_R3 0x00000008 |
Definition at line 7506 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604)) |
Definition at line 1744 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R0 0x00000001 |
Definition at line 7422 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R1 0x00000002 |
Definition at line 7420 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R2 0x00000004 |
Definition at line 7418 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R3 0x00000008 |
Definition at line 7416 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R4 0x00000010 |
Definition at line 7414 of file cortex-m4-def.h.
| #define SYSCTL_RCGCTIMER_R5 0x00000020 |
Definition at line 7412 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618)) |
Definition at line 1748 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R0 0x00000001 |
Definition at line 7498 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R1 0x00000002 |
Definition at line 7496 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R2 0x00000004 |
Definition at line 7494 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R3 0x00000008 |
Definition at line 7492 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R4 0x00000010 |
Definition at line 7490 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R5 0x00000020 |
Definition at line 7488 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R6 0x00000040 |
Definition at line 7486 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUART_R7 0x00000080 |
Definition at line 7484 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628)) |
Definition at line 1751 of file cortex-m4-def.h.
| #define SYSCTL_RCGCUSB_R0 0x00000001 |
Definition at line 7538 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600)) |
Definition at line 1743 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWD_R0 0x00000001 |
Definition at line 7403 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWD_R1 0x00000002 |
Definition at line 7401 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C)) |
Definition at line 1756 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R0 0x00000001 |
Definition at line 7595 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R1 0x00000002 |
Definition at line 7593 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R2 0x00000004 |
Definition at line 7591 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R3 0x00000008 |
Definition at line 7589 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R4 0x00000010 |
Definition at line 7587 of file cortex-m4-def.h.
| #define SYSCTL_RCGCWTIMER_R5 0x00000020 |
Definition at line 7585 of file cortex-m4-def.h.
| #define SYSCTL_RESC_BOR 0x00000004 |
Definition at line 6647 of file cortex-m4-def.h.
| #define SYSCTL_RESC_EXT 0x00000001 |
Definition at line 6649 of file cortex-m4-def.h.
| #define SYSCTL_RESC_MOSCFAIL 0x00010000 |
Definition at line 6643 of file cortex-m4-def.h.
| #define SYSCTL_RESC_POR 0x00000002 |
Definition at line 6648 of file cortex-m4-def.h.
| #define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C)) |
Definition at line 1690 of file cortex-m4-def.h.
| #define SYSCTL_RESC_SW 0x00000010 |
Definition at line 6645 of file cortex-m4-def.h.
| #define SYSCTL_RESC_WDT0 0x00000008 |
Definition at line 6646 of file cortex-m4-def.h.
| #define SYSCTL_RESC_WDT1 0x00000020 |
Definition at line 6644 of file cortex-m4-def.h.
| #define SYSCTL_RIS_BORRIS 0x00000002 |
Definition at line 6609 of file cortex-m4-def.h.
| #define SYSCTL_RIS_MOFRIS 0x00000008 |
Definition at line 6607 of file cortex-m4-def.h.
| #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 |
Definition at line 6602 of file cortex-m4-def.h.
| #define SYSCTL_RIS_PLLLRIS 0x00000040 |
Definition at line 6606 of file cortex-m4-def.h.
| #define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050)) |
Definition at line 1687 of file cortex-m4-def.h.
| #define SYSCTL_RIS_USBPLLLRIS 0x00000080 |
Definition at line 6604 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_ADC0 0x00010000 |
Definition at line 6883 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_ADC1 0x00020000 |
Definition at line 6882 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_CAN0 0x01000000 |
Definition at line 6880 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_CAN1 0x02000000 |
Definition at line 6879 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_HIB 0x00000040 |
Definition at line 6884 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_PWM0 0x00100000 |
Definition at line 6881 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110)) |
Definition at line 1698 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_WDT0 0x00000008 |
Definition at line 6885 of file cortex-m4-def.h.
| #define SYSCTL_SCGC0_WDT1 0x10000000 |
Definition at line 6878 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_COMP0 0x01000000 |
Definition at line 6894 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_COMP1 0x02000000 |
Definition at line 6893 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_COMP2 0x04000000 |
Definition at line 6892 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_I2C0 0x00001000 |
Definition at line 6900 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_I2C1 0x00004000 |
Definition at line 6899 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_QEI0 0x00000100 |
Definition at line 6902 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_QEI1 0x00000200 |
Definition at line 6901 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114)) |
Definition at line 1699 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_SSI0 0x00000010 |
Definition at line 6904 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_SSI1 0x00000020 |
Definition at line 6903 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_TIMER0 0x00010000 |
Definition at line 6898 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_TIMER1 0x00020000 |
Definition at line 6897 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_TIMER2 0x00040000 |
Definition at line 6896 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_TIMER3 0x00080000 |
Definition at line 6895 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_UART0 0x00000001 |
Definition at line 6907 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_UART1 0x00000002 |
Definition at line 6906 of file cortex-m4-def.h.
| #define SYSCTL_SCGC1_UART2 0x00000004 |
Definition at line 6905 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOA 0x00000001 |
Definition at line 6924 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOB 0x00000002 |
Definition at line 6923 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOC 0x00000004 |
Definition at line 6922 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOD 0x00000008 |
Definition at line 6921 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOE 0x00000010 |
Definition at line 6920 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOF 0x00000020 |
Definition at line 6919 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOG 0x00000040 |
Definition at line 6918 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOH 0x00000080 |
Definition at line 6917 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_GPIOJ 0x00000100 |
Definition at line 6916 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118)) |
Definition at line 1700 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_UDMA 0x00002000 |
Definition at line 6915 of file cortex-m4-def.h.
| #define SYSCTL_SCGC2_USB0 0x00010000 |
Definition at line 6914 of file cortex-m4-def.h.
| #define SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C)) |
Definition at line 1768 of file cortex-m4-def.h.
| #define SYSCTL_SCGCACMP_S0 0x00000001 |
Definition at line 7769 of file cortex-m4-def.h.
| #define SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738)) |
Definition at line 1767 of file cortex-m4-def.h.
| #define SYSCTL_SCGCADC_S0 0x00000001 |
Definition at line 7760 of file cortex-m4-def.h.
| #define SYSCTL_SCGCADC_S1 0x00000002 |
Definition at line 7758 of file cortex-m4-def.h.
| #define SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734)) |
Definition at line 1766 of file cortex-m4-def.h.
| #define SYSCTL_SCGCCAN_S0 0x00000001 |
Definition at line 7750 of file cortex-m4-def.h.
| #define SYSCTL_SCGCCAN_S1 0x00000002 |
Definition at line 7748 of file cortex-m4-def.h.
| #define SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C)) |
Definition at line 1760 of file cortex-m4-def.h.
| #define SYSCTL_SCGCDMA_S0 0x00000001 |
Definition at line 7669 of file cortex-m4-def.h.
| #define SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758)) |
Definition at line 1769 of file cortex-m4-def.h.
| #define SYSCTL_SCGCEEPROM_S0 0x00000001 |
Definition at line 7778 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708)) |
Definition at line 1759 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S0 0x00000001 |
Definition at line 7661 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S1 0x00000002 |
Definition at line 7659 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S10 0x00000400 |
Definition at line 7641 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S11 0x00000800 |
Definition at line 7639 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S12 0x00001000 |
Definition at line 7637 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S13 0x00002000 |
Definition at line 7635 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S14 0x00004000 |
Definition at line 7633 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S2 0x00000004 |
Definition at line 7657 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S3 0x00000008 |
Definition at line 7655 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S4 0x00000010 |
Definition at line 7653 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S5 0x00000020 |
Definition at line 7651 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S6 0x00000040 |
Definition at line 7649 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S7 0x00000080 |
Definition at line 7647 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S8 0x00000100 |
Definition at line 7645 of file cortex-m4-def.h.
| #define SYSCTL_SCGCGPIO_S9 0x00000200 |
Definition at line 7643 of file cortex-m4-def.h.
| #define SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714)) |
Definition at line 1761 of file cortex-m4-def.h.
| #define SYSCTL_SCGCHIB_S0 0x00000001 |
Definition at line 7677 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720)) |
Definition at line 1764 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S0 0x00000001 |
Definition at line 7732 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S1 0x00000002 |
Definition at line 7730 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S2 0x00000004 |
Definition at line 7728 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S3 0x00000008 |
Definition at line 7726 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S4 0x00000010 |
Definition at line 7724 of file cortex-m4-def.h.
| #define SYSCTL_SCGCI2C_S5 0x00000020 |
Definition at line 7722 of file cortex-m4-def.h.
| #define SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C)) |
Definition at line 1763 of file cortex-m4-def.h.
| #define SYSCTL_SCGCSSI_S0 0x00000001 |
Definition at line 7714 of file cortex-m4-def.h.
| #define SYSCTL_SCGCSSI_S1 0x00000002 |
Definition at line 7712 of file cortex-m4-def.h.
| #define SYSCTL_SCGCSSI_S2 0x00000004 |
Definition at line 7710 of file cortex-m4-def.h.
| #define SYSCTL_SCGCSSI_S3 0x00000008 |
Definition at line 7708 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704)) |
Definition at line 1758 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S0 0x00000001 |
Definition at line 7624 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S1 0x00000002 |
Definition at line 7622 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S2 0x00000004 |
Definition at line 7620 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S3 0x00000008 |
Definition at line 7618 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S4 0x00000010 |
Definition at line 7616 of file cortex-m4-def.h.
| #define SYSCTL_SCGCTIMER_S5 0x00000020 |
Definition at line 7614 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718)) |
Definition at line 1762 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S0 0x00000001 |
Definition at line 7700 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S1 0x00000002 |
Definition at line 7698 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S2 0x00000004 |
Definition at line 7696 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S3 0x00000008 |
Definition at line 7694 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S4 0x00000010 |
Definition at line 7692 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S5 0x00000020 |
Definition at line 7690 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S6 0x00000040 |
Definition at line 7688 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUART_S7 0x00000080 |
Definition at line 7686 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728)) |
Definition at line 1765 of file cortex-m4-def.h.
| #define SYSCTL_SCGCUSB_S0 0x00000001 |
Definition at line 7740 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700)) |
Definition at line 1757 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWD_S0 0x00000001 |
Definition at line 7605 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWD_S1 0x00000002 |
Definition at line 7603 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C)) |
Definition at line 1770 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S0 0x00000001 |
Definition at line 7797 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S1 0x00000002 |
Definition at line 7795 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S2 0x00000004 |
Definition at line 7793 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S3 0x00000008 |
Definition at line 7791 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S4 0x00000010 |
Definition at line 7789 of file cortex-m4-def.h.
| #define SYSCTL_SCGCWTIMER_S5 0x00000020 |
Definition at line 7787 of file cortex-m4-def.h.
| #define SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C)) |
Definition at line 1740 of file cortex-m4-def.h.
| #define SYSCTL_SRACMP_R0 0x00000001 |
Definition at line 7372 of file cortex-m4-def.h.
| #define SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538)) |
Definition at line 1739 of file cortex-m4-def.h.
| #define SYSCTL_SRADC_R0 0x00000001 |
Definition at line 7365 of file cortex-m4-def.h.
| #define SYSCTL_SRADC_R1 0x00000002 |
Definition at line 7364 of file cortex-m4-def.h.
| #define SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534)) |
Definition at line 1738 of file cortex-m4-def.h.
| #define SYSCTL_SRCAN_R0 0x00000001 |
Definition at line 7357 of file cortex-m4-def.h.
| #define SYSCTL_SRCAN_R1 0x00000002 |
Definition at line 7356 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_ADC0 0x00010000 |
Definition at line 6554 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_ADC1 0x00020000 |
Definition at line 6553 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_CAN0 0x01000000 |
Definition at line 6551 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_CAN1 0x02000000 |
Definition at line 6550 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_HIB 0x00000040 |
Definition at line 6555 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_PWM0 0x00100000 |
Definition at line 6552 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040)) |
Definition at line 1684 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_WDT0 0x00000008 |
Definition at line 6556 of file cortex-m4-def.h.
| #define SYSCTL_SRCR0_WDT1 0x10000000 |
Definition at line 6549 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_COMP0 0x01000000 |
Definition at line 6565 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_COMP1 0x02000000 |
Definition at line 6564 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_COMP2 0x04000000 |
Definition at line 6563 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_I2C0 0x00001000 |
Definition at line 6571 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_I2C1 0x00004000 |
Definition at line 6570 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_QEI0 0x00000100 |
Definition at line 6573 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_QEI1 0x00000200 |
Definition at line 6572 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044)) |
Definition at line 1685 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_SSI0 0x00000010 |
Definition at line 6575 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_SSI1 0x00000020 |
Definition at line 6574 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_TIMER0 0x00010000 |
Definition at line 6569 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_TIMER1 0x00020000 |
Definition at line 6568 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_TIMER2 0x00040000 |
Definition at line 6567 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_TIMER3 0x00080000 |
Definition at line 6566 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_UART0 0x00000001 |
Definition at line 6578 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_UART1 0x00000002 |
Definition at line 6577 of file cortex-m4-def.h.
| #define SYSCTL_SRCR1_UART2 0x00000004 |
Definition at line 6576 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOA 0x00000001 |
Definition at line 6595 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOB 0x00000002 |
Definition at line 6594 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOC 0x00000004 |
Definition at line 6593 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOD 0x00000008 |
Definition at line 6592 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOE 0x00000010 |
Definition at line 6591 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOF 0x00000020 |
Definition at line 6590 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOG 0x00000040 |
Definition at line 6589 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOH 0x00000080 |
Definition at line 6588 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_GPIOJ 0x00000100 |
Definition at line 6587 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048)) |
Definition at line 1686 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_UDMA 0x00002000 |
Definition at line 6586 of file cortex-m4-def.h.
| #define SYSCTL_SRCR2_USB0 0x00010000 |
Definition at line 6585 of file cortex-m4-def.h.
| #define SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C)) |
Definition at line 1732 of file cortex-m4-def.h.
| #define SYSCTL_SRDMA_R0 0x00000001 |
Definition at line 7298 of file cortex-m4-def.h.
| #define SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558)) |
Definition at line 1741 of file cortex-m4-def.h.
| #define SYSCTL_SREEPROM_R0 0x00000001 |
Definition at line 7381 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508)) |
Definition at line 1731 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R0 0x00000001 |
Definition at line 7291 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R1 0x00000002 |
Definition at line 7290 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R10 0x00000400 |
Definition at line 7281 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R11 0x00000800 |
Definition at line 7280 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R12 0x00001000 |
Definition at line 7279 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R13 0x00002000 |
Definition at line 7278 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R14 0x00004000 |
Definition at line 7277 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R2 0x00000004 |
Definition at line 7289 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R3 0x00000008 |
Definition at line 7288 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R4 0x00000010 |
Definition at line 7287 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R5 0x00000020 |
Definition at line 7286 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R6 0x00000040 |
Definition at line 7285 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R7 0x00000080 |
Definition at line 7284 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R8 0x00000100 |
Definition at line 7283 of file cortex-m4-def.h.
| #define SYSCTL_SRGPIO_R9 0x00000200 |
Definition at line 7282 of file cortex-m4-def.h.
| #define SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514)) |
Definition at line 1733 of file cortex-m4-def.h.
| #define SYSCTL_SRHIB_R0 0x00000001 |
Definition at line 7305 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520)) |
Definition at line 1736 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R0 0x00000001 |
Definition at line 7342 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R1 0x00000002 |
Definition at line 7341 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R2 0x00000004 |
Definition at line 7340 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R3 0x00000008 |
Definition at line 7339 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R4 0x00000010 |
Definition at line 7338 of file cortex-m4-def.h.
| #define SYSCTL_SRI2C_R5 0x00000020 |
Definition at line 7337 of file cortex-m4-def.h.
| #define SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C)) |
Definition at line 1735 of file cortex-m4-def.h.
| #define SYSCTL_SRSSI_R0 0x00000001 |
Definition at line 7330 of file cortex-m4-def.h.
| #define SYSCTL_SRSSI_R1 0x00000002 |
Definition at line 7329 of file cortex-m4-def.h.
| #define SYSCTL_SRSSI_R2 0x00000004 |
Definition at line 7328 of file cortex-m4-def.h.
| #define SYSCTL_SRSSI_R3 0x00000008 |
Definition at line 7327 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504)) |
Definition at line 1730 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R0 0x00000001 |
Definition at line 7270 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R1 0x00000002 |
Definition at line 7269 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R2 0x00000004 |
Definition at line 7268 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R3 0x00000008 |
Definition at line 7267 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R4 0x00000010 |
Definition at line 7266 of file cortex-m4-def.h.
| #define SYSCTL_SRTIMER_R5 0x00000020 |
Definition at line 7265 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518)) |
Definition at line 1734 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R0 0x00000001 |
Definition at line 7320 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R1 0x00000002 |
Definition at line 7319 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R2 0x00000004 |
Definition at line 7318 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R3 0x00000008 |
Definition at line 7317 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R4 0x00000010 |
Definition at line 7316 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R5 0x00000020 |
Definition at line 7315 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R6 0x00000040 |
Definition at line 7314 of file cortex-m4-def.h.
| #define SYSCTL_SRUART_R7 0x00000080 |
Definition at line 7313 of file cortex-m4-def.h.
| #define SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528)) |
Definition at line 1737 of file cortex-m4-def.h.
| #define SYSCTL_SRUSB_R0 0x00000001 |
Definition at line 7349 of file cortex-m4-def.h.
| #define SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500)) |
Definition at line 1729 of file cortex-m4-def.h.
| #define SYSCTL_SRWD_R0 0x00000001 |
Definition at line 7258 of file cortex-m4-def.h.
| #define SYSCTL_SRWD_R1 0x00000002 |
Definition at line 7257 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C)) |
Definition at line 1742 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R0 0x00000001 |
Definition at line 7394 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R1 0x00000002 |
Definition at line 7393 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R2 0x00000004 |
Definition at line 7392 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R3 0x00000008 |
Definition at line 7391 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R4 0x00000010 |
Definition at line 7390 of file cortex-m4-def.h.
| #define SYSCTL_SRWTIMER_R5 0x00000020 |
Definition at line 7389 of file cortex-m4-def.h.
| #define SYSCTL_SYSPROP_FPU 0x00000001 |
Definition at line 7002 of file cortex-m4-def.h.
| #define SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C)) |
Definition at line 1705 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPDZCIC 0x00000002 |
Definition at line 5871 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPIDCIC 0x00000001 |
Definition at line 5873 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPIOCIC 0x00000004 |
Definition at line 5869 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPIXCIC 0x00000020 |
Definition at line 5863 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPOFCIC 0x00000010 |
Definition at line 5865 of file cortex-m4-def.h.
| #define SYSEXC_IC_FPUFCIC 0x00000008 |
Definition at line 5867 of file cortex-m4-def.h.
| #define SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C)) |
Definition at line 1616 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPDZCIM 0x00000002 |
Definition at line 5831 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPIDCIM 0x00000001 |
Definition at line 5833 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPIOCIM 0x00000004 |
Definition at line 5829 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPIXCIM 0x00000020 |
Definition at line 5823 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPOFCIM 0x00000010 |
Definition at line 5825 of file cortex-m4-def.h.
| #define SYSEXC_IM_FPUFCIM 0x00000008 |
Definition at line 5827 of file cortex-m4-def.h.
| #define SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004)) |
Definition at line 1614 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPDZCMIS 0x00000002 |
Definition at line 5851 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPIDCMIS 0x00000001 |
Definition at line 5854 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPIOCMIS 0x00000004 |
Definition at line 5849 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPIXCMIS 0x00000020 |
Definition at line 5841 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPOFCMIS 0x00000010 |
Definition at line 5843 of file cortex-m4-def.h.
| #define SYSEXC_MIS_FPUFCMIS 0x00000008 |
Definition at line 5846 of file cortex-m4-def.h.
| #define SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008)) |
Definition at line 1615 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPDZCRIS 0x00000002 |
Definition at line 5813 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPIDCRIS 0x00000001 |
Definition at line 5815 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPIOCRIS 0x00000004 |
Definition at line 5811 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPIXCRIS 0x00000020 |
Definition at line 5805 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPOFCRIS 0x00000010 |
Definition at line 5807 of file cortex-m4-def.h.
| #define SYSEXC_RIS_FPUFCRIS 0x00000008 |
Definition at line 5809 of file cortex-m4-def.h.
| #define SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000)) |
Definition at line 1613 of file cortex-m4-def.h.
| #define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) |
Definition at line 724 of file cortex-m4-def.h.
| #define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) |
Definition at line 727 of file cortex-m4-def.h.
| #define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) |
Definition at line 732 of file cortex-m4-def.h.
| #define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) |
Definition at line 729 of file cortex-m4-def.h.
| #define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) |
Definition at line 731 of file cortex-m4-def.h.
| #define TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0)) |
Definition at line 750 of file cortex-m4-def.h.
| #define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C)) |
Definition at line 730 of file cortex-m4-def.h.
| #define TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058)) |
Definition at line 745 of file cortex-m4-def.h.
| #define TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010)) |
Definition at line 728 of file cortex-m4-def.h.
| #define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) |
Definition at line 733 of file cortex-m4-def.h.
| #define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030)) |
Definition at line 735 of file cortex-m4-def.h.
| #define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) |
Definition at line 725 of file cortex-m4-def.h.
| #define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040)) |
Definition at line 739 of file cortex-m4-def.h.
| #define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) |
Definition at line 737 of file cortex-m4-def.h.
| #define TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C)) |
Definition at line 746 of file cortex-m4-def.h.
| #define TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064)) |
Definition at line 748 of file cortex-m4-def.h.
| #define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) |
Definition at line 741 of file cortex-m4-def.h.
| #define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050)) |
Definition at line 743 of file cortex-m4-def.h.
| #define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C)) |
Definition at line 734 of file cortex-m4-def.h.
| #define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034)) |
Definition at line 736 of file cortex-m4-def.h.
| #define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008)) |
Definition at line 726 of file cortex-m4-def.h.
| #define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044)) |
Definition at line 740 of file cortex-m4-def.h.
| #define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C)) |
Definition at line 738 of file cortex-m4-def.h.
| #define TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060)) |
Definition at line 747 of file cortex-m4-def.h.
| #define TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068)) |
Definition at line 749 of file cortex-m4-def.h.
| #define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C)) |
Definition at line 742 of file cortex-m4-def.h.
| #define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054)) |
Definition at line 744 of file cortex-m4-def.h.
| #define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000)) |
Definition at line 757 of file cortex-m4-def.h.
| #define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C)) |
Definition at line 760 of file cortex-m4-def.h.
| #define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024)) |
Definition at line 765 of file cortex-m4-def.h.
| #define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018)) |
Definition at line 762 of file cortex-m4-def.h.
| #define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020)) |
Definition at line 764 of file cortex-m4-def.h.
| #define TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0)) |
Definition at line 783 of file cortex-m4-def.h.
| #define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C)) |
Definition at line 763 of file cortex-m4-def.h.
| #define TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058)) |
Definition at line 778 of file cortex-m4-def.h.
| #define TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010)) |
Definition at line 761 of file cortex-m4-def.h.
| #define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028)) |
Definition at line 766 of file cortex-m4-def.h.
| #define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030)) |
Definition at line 768 of file cortex-m4-def.h.
| #define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004)) |
Definition at line 758 of file cortex-m4-def.h.
| #define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040)) |
Definition at line 772 of file cortex-m4-def.h.
| #define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038)) |
Definition at line 770 of file cortex-m4-def.h.
| #define TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C)) |
Definition at line 779 of file cortex-m4-def.h.
| #define TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064)) |
Definition at line 781 of file cortex-m4-def.h.
| #define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048)) |
Definition at line 774 of file cortex-m4-def.h.
| #define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050)) |
Definition at line 776 of file cortex-m4-def.h.
| #define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C)) |
Definition at line 767 of file cortex-m4-def.h.
| #define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034)) |
Definition at line 769 of file cortex-m4-def.h.
| #define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008)) |
Definition at line 759 of file cortex-m4-def.h.
| #define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044)) |
Definition at line 773 of file cortex-m4-def.h.
| #define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C)) |
Definition at line 771 of file cortex-m4-def.h.
| #define TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060)) |
Definition at line 780 of file cortex-m4-def.h.
| #define TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068)) |
Definition at line 782 of file cortex-m4-def.h.
| #define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C)) |
Definition at line 775 of file cortex-m4-def.h.
| #define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054)) |
Definition at line 777 of file cortex-m4-def.h.
| #define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000)) |
Definition at line 790 of file cortex-m4-def.h.
| #define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C)) |
Definition at line 793 of file cortex-m4-def.h.
| #define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024)) |
Definition at line 798 of file cortex-m4-def.h.
| #define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018)) |
Definition at line 795 of file cortex-m4-def.h.
| #define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020)) |
Definition at line 797 of file cortex-m4-def.h.
| #define TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0)) |
Definition at line 816 of file cortex-m4-def.h.
| #define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C)) |
Definition at line 796 of file cortex-m4-def.h.
| #define TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058)) |
Definition at line 811 of file cortex-m4-def.h.
| #define TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010)) |
Definition at line 794 of file cortex-m4-def.h.
| #define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028)) |
Definition at line 799 of file cortex-m4-def.h.
| #define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030)) |
Definition at line 801 of file cortex-m4-def.h.
| #define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004)) |
Definition at line 791 of file cortex-m4-def.h.
| #define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040)) |
Definition at line 805 of file cortex-m4-def.h.
| #define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038)) |
Definition at line 803 of file cortex-m4-def.h.
| #define TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C)) |
Definition at line 812 of file cortex-m4-def.h.
| #define TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064)) |
Definition at line 814 of file cortex-m4-def.h.
| #define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048)) |
Definition at line 807 of file cortex-m4-def.h.
| #define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050)) |
Definition at line 809 of file cortex-m4-def.h.
| #define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C)) |
Definition at line 800 of file cortex-m4-def.h.
| #define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034)) |
Definition at line 802 of file cortex-m4-def.h.
| #define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008)) |
Definition at line 792 of file cortex-m4-def.h.
| #define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044)) |
Definition at line 806 of file cortex-m4-def.h.
| #define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C)) |
Definition at line 804 of file cortex-m4-def.h.
| #define TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060)) |
Definition at line 813 of file cortex-m4-def.h.
| #define TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068)) |
Definition at line 815 of file cortex-m4-def.h.
| #define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C)) |
Definition at line 808 of file cortex-m4-def.h.
| #define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054)) |
Definition at line 810 of file cortex-m4-def.h.
| #define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000)) |
Definition at line 823 of file cortex-m4-def.h.
| #define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C)) |
Definition at line 826 of file cortex-m4-def.h.
| #define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024)) |
Definition at line 831 of file cortex-m4-def.h.
| #define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018)) |
Definition at line 828 of file cortex-m4-def.h.
| #define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020)) |
Definition at line 830 of file cortex-m4-def.h.
| #define TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0)) |
Definition at line 849 of file cortex-m4-def.h.
| #define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C)) |
Definition at line 829 of file cortex-m4-def.h.
| #define TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058)) |
Definition at line 844 of file cortex-m4-def.h.
| #define TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010)) |
Definition at line 827 of file cortex-m4-def.h.
| #define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028)) |
Definition at line 832 of file cortex-m4-def.h.
| #define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030)) |
Definition at line 834 of file cortex-m4-def.h.
| #define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004)) |
Definition at line 824 of file cortex-m4-def.h.
| #define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040)) |
Definition at line 838 of file cortex-m4-def.h.
| #define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038)) |
Definition at line 836 of file cortex-m4-def.h.
| #define TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C)) |
Definition at line 845 of file cortex-m4-def.h.
| #define TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064)) |
Definition at line 847 of file cortex-m4-def.h.
| #define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048)) |
Definition at line 840 of file cortex-m4-def.h.
| #define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050)) |
Definition at line 842 of file cortex-m4-def.h.
| #define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C)) |
Definition at line 833 of file cortex-m4-def.h.
| #define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034)) |
Definition at line 835 of file cortex-m4-def.h.
| #define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008)) |
Definition at line 825 of file cortex-m4-def.h.
| #define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044)) |
Definition at line 839 of file cortex-m4-def.h.
| #define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C)) |
Definition at line 837 of file cortex-m4-def.h.
| #define TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060)) |
Definition at line 846 of file cortex-m4-def.h.
| #define TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068)) |
Definition at line 848 of file cortex-m4-def.h.
| #define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C)) |
Definition at line 841 of file cortex-m4-def.h.
| #define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054)) |
Definition at line 843 of file cortex-m4-def.h.
| #define TIMER4_CFG_R (*((volatile unsigned long *)0x40034000)) |
Definition at line 856 of file cortex-m4-def.h.
| #define TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C)) |
Definition at line 859 of file cortex-m4-def.h.
| #define TIMER4_ICR_R (*((volatile unsigned long *)0x40034024)) |
Definition at line 864 of file cortex-m4-def.h.
| #define TIMER4_IMR_R (*((volatile unsigned long *)0x40034018)) |
Definition at line 861 of file cortex-m4-def.h.
| #define TIMER4_MIS_R (*((volatile unsigned long *)0x40034020)) |
Definition at line 863 of file cortex-m4-def.h.
| #define TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0)) |
Definition at line 882 of file cortex-m4-def.h.
| #define TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C)) |
Definition at line 862 of file cortex-m4-def.h.
| #define TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058)) |
Definition at line 877 of file cortex-m4-def.h.
| #define TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010)) |
Definition at line 860 of file cortex-m4-def.h.
| #define TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028)) |
Definition at line 865 of file cortex-m4-def.h.
| #define TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030)) |
Definition at line 867 of file cortex-m4-def.h.
| #define TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004)) |
Definition at line 857 of file cortex-m4-def.h.
| #define TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040)) |
Definition at line 871 of file cortex-m4-def.h.
| #define TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038)) |
Definition at line 869 of file cortex-m4-def.h.
| #define TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C)) |
Definition at line 878 of file cortex-m4-def.h.
| #define TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064)) |
Definition at line 880 of file cortex-m4-def.h.
| #define TIMER4_TAR_R (*((volatile unsigned long *)0x40034048)) |
Definition at line 873 of file cortex-m4-def.h.
| #define TIMER4_TAV_R (*((volatile unsigned long *)0x40034050)) |
Definition at line 875 of file cortex-m4-def.h.
| #define TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C)) |
Definition at line 866 of file cortex-m4-def.h.
| #define TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034)) |
Definition at line 868 of file cortex-m4-def.h.
| #define TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008)) |
Definition at line 858 of file cortex-m4-def.h.
| #define TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044)) |
Definition at line 872 of file cortex-m4-def.h.
| #define TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C)) |
Definition at line 870 of file cortex-m4-def.h.
| #define TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060)) |
Definition at line 879 of file cortex-m4-def.h.
| #define TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068)) |
Definition at line 881 of file cortex-m4-def.h.
| #define TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C)) |
Definition at line 874 of file cortex-m4-def.h.
| #define TIMER4_TBV_R (*((volatile unsigned long *)0x40034054)) |
Definition at line 876 of file cortex-m4-def.h.
| #define TIMER5_CFG_R (*((volatile unsigned long *)0x40035000)) |
Definition at line 889 of file cortex-m4-def.h.
| #define TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C)) |
Definition at line 892 of file cortex-m4-def.h.
| #define TIMER5_ICR_R (*((volatile unsigned long *)0x40035024)) |
Definition at line 897 of file cortex-m4-def.h.
| #define TIMER5_IMR_R (*((volatile unsigned long *)0x40035018)) |
Definition at line 894 of file cortex-m4-def.h.
| #define TIMER5_MIS_R (*((volatile unsigned long *)0x40035020)) |
Definition at line 896 of file cortex-m4-def.h.
| #define TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0)) |
Definition at line 915 of file cortex-m4-def.h.
| #define TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C)) |
Definition at line 895 of file cortex-m4-def.h.
| #define TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058)) |
Definition at line 910 of file cortex-m4-def.h.
| #define TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010)) |
Definition at line 893 of file cortex-m4-def.h.
| #define TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028)) |
Definition at line 898 of file cortex-m4-def.h.
| #define TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030)) |
Definition at line 900 of file cortex-m4-def.h.
| #define TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004)) |
Definition at line 890 of file cortex-m4-def.h.
| #define TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040)) |
Definition at line 904 of file cortex-m4-def.h.
| #define TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038)) |
Definition at line 902 of file cortex-m4-def.h.
| #define TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C)) |
Definition at line 911 of file cortex-m4-def.h.
| #define TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064)) |
Definition at line 913 of file cortex-m4-def.h.
| #define TIMER5_TAR_R (*((volatile unsigned long *)0x40035048)) |
Definition at line 906 of file cortex-m4-def.h.
| #define TIMER5_TAV_R (*((volatile unsigned long *)0x40035050)) |
Definition at line 908 of file cortex-m4-def.h.
| #define TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C)) |
Definition at line 899 of file cortex-m4-def.h.
| #define TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034)) |
Definition at line 901 of file cortex-m4-def.h.
| #define TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008)) |
Definition at line 891 of file cortex-m4-def.h.
| #define TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044)) |
Definition at line 905 of file cortex-m4-def.h.
| #define TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C)) |
Definition at line 903 of file cortex-m4-def.h.
| #define TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060)) |
Definition at line 912 of file cortex-m4-def.h.
| #define TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068)) |
Definition at line 914 of file cortex-m4-def.h.
| #define TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C)) |
Definition at line 907 of file cortex-m4-def.h.
| #define TIMER5_TBV_R (*((volatile unsigned long *)0x40035054)) |
Definition at line 909 of file cortex-m4-def.h.
| #define TIMER_CFG_16_BIT 0x00000004 |
Definition at line 2901 of file cortex-m4-def.h.
| #define TIMER_CFG_32_BIT_RTC 0x00000001 |
Definition at line 2899 of file cortex-m4-def.h.
| #define TIMER_CFG_32_BIT_TIMER 0x00000000 |
Definition at line 2898 of file cortex-m4-def.h.
| #define TIMER_CFG_M 0x00000007 |
Definition at line 2897 of file cortex-m4-def.h.
| #define TIMER_CTL_RTCEN 0x00000010 |
Definition at line 2972 of file cortex-m4-def.h.
| #define TIMER_CTL_TAEN 0x00000001 |
Definition at line 2978 of file cortex-m4-def.h.
| #define TIMER_CTL_TAEVENT_BOTH 0x0000000C |
Definition at line 2976 of file cortex-m4-def.h.
| #define TIMER_CTL_TAEVENT_M 0x0000000C |
Definition at line 2973 of file cortex-m4-def.h.
| #define TIMER_CTL_TAEVENT_NEG 0x00000004 |
Definition at line 2975 of file cortex-m4-def.h.
| #define TIMER_CTL_TAEVENT_POS 0x00000000 |
Definition at line 2974 of file cortex-m4-def.h.
| #define TIMER_CTL_TAOTE 0x00000020 |
Definition at line 2970 of file cortex-m4-def.h.
| #define TIMER_CTL_TAPWML 0x00000040 |
Definition at line 2969 of file cortex-m4-def.h.
| #define TIMER_CTL_TASTALL 0x00000002 |
Definition at line 2977 of file cortex-m4-def.h.
| #define TIMER_CTL_TBEN 0x00000100 |
Definition at line 2968 of file cortex-m4-def.h.
| #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 |
Definition at line 2966 of file cortex-m4-def.h.
| #define TIMER_CTL_TBEVENT_M 0x00000C00 |
Definition at line 2963 of file cortex-m4-def.h.
| #define TIMER_CTL_TBEVENT_NEG 0x00000400 |
Definition at line 2965 of file cortex-m4-def.h.
| #define TIMER_CTL_TBEVENT_POS 0x00000000 |
Definition at line 2964 of file cortex-m4-def.h.
| #define TIMER_CTL_TBOTE 0x00002000 |
Definition at line 2961 of file cortex-m4-def.h.
| #define TIMER_CTL_TBPWML 0x00004000 |
Definition at line 2960 of file cortex-m4-def.h.
| #define TIMER_CTL_TBSTALL 0x00000200 |
Definition at line 2967 of file cortex-m4-def.h.
| #define TIMER_ICR_CAECINT 0x00000004 |
Definition at line 3233 of file cortex-m4-def.h.
| #define TIMER_ICR_CAMCINT 0x00000002 |
Definition at line 3235 of file cortex-m4-def.h.
| #define TIMER_ICR_CBECINT 0x00000400 |
Definition at line 3224 of file cortex-m4-def.h.
| #define TIMER_ICR_CBMCINT 0x00000200 |
Definition at line 3226 of file cortex-m4-def.h.
| #define TIMER_ICR_RTCCINT 0x00000008 |
Definition at line 3232 of file cortex-m4-def.h.
| #define TIMER_ICR_TAMCINT 0x00000010 |
Definition at line 3230 of file cortex-m4-def.h.
| #define TIMER_ICR_TATOCINT 0x00000001 |
Definition at line 3237 of file cortex-m4-def.h.
| #define TIMER_ICR_TBMCINT 0x00000800 |
Definition at line 3222 of file cortex-m4-def.h.
| #define TIMER_ICR_TBTOCINT 0x00000100 |
Definition at line 3228 of file cortex-m4-def.h.
| #define TIMER_ICR_WUECINT 0x00010000 |
Definition at line 3220 of file cortex-m4-def.h.
| #define TIMER_IMR_CAEIM 0x00000004 |
Definition at line 3160 of file cortex-m4-def.h.
| #define TIMER_IMR_CAMIM 0x00000002 |
Definition at line 3162 of file cortex-m4-def.h.
| #define TIMER_IMR_CBEIM 0x00000400 |
Definition at line 3151 of file cortex-m4-def.h.
| #define TIMER_IMR_CBMIM 0x00000200 |
Definition at line 3153 of file cortex-m4-def.h.
| #define TIMER_IMR_RTCIM 0x00000008 |
Definition at line 3159 of file cortex-m4-def.h.
| #define TIMER_IMR_TAMIM 0x00000010 |
Definition at line 3157 of file cortex-m4-def.h.
| #define TIMER_IMR_TATOIM 0x00000001 |
Definition at line 3164 of file cortex-m4-def.h.
| #define TIMER_IMR_TBMIM 0x00000800 |
Definition at line 3149 of file cortex-m4-def.h.
| #define TIMER_IMR_TBTOIM 0x00000100 |
Definition at line 3155 of file cortex-m4-def.h.
| #define TIMER_IMR_WUEIM 0x00010000 |
Definition at line 3147 of file cortex-m4-def.h.
| #define TIMER_MIS_CAEMIS 0x00000004 |
Definition at line 3208 of file cortex-m4-def.h.
| #define TIMER_MIS_CAMMIS 0x00000002 |
Definition at line 3210 of file cortex-m4-def.h.
| #define TIMER_MIS_CBEMIS 0x00000400 |
Definition at line 3199 of file cortex-m4-def.h.
| #define TIMER_MIS_CBMMIS 0x00000200 |
Definition at line 3201 of file cortex-m4-def.h.
| #define TIMER_MIS_RTCMIS 0x00000008 |
Definition at line 3207 of file cortex-m4-def.h.
| #define TIMER_MIS_TAMMIS 0x00000010 |
Definition at line 3205 of file cortex-m4-def.h.
| #define TIMER_MIS_TATOMIS 0x00000001 |
Definition at line 3212 of file cortex-m4-def.h.
| #define TIMER_MIS_TBMMIS 0x00000800 |
Definition at line 3197 of file cortex-m4-def.h.
| #define TIMER_MIS_TBTOMIS 0x00000100 |
Definition at line 3203 of file cortex-m4-def.h.
| #define TIMER_MIS_WUEMIS 0x00010000 |
Definition at line 3195 of file cortex-m4-def.h.
| #define TIMER_PP_SIZE_16 0x00000000 |
Definition at line 3396 of file cortex-m4-def.h.
| #define TIMER_PP_SIZE_32 0x00000001 |
Definition at line 3399 of file cortex-m4-def.h.
| #define TIMER_PP_SIZE_M 0x0000000F |
Definition at line 3395 of file cortex-m4-def.h.
| #define TIMER_RIS_CAERIS 0x00000004 |
Definition at line 3183 of file cortex-m4-def.h.
| #define TIMER_RIS_CAMRIS 0x00000002 |
Definition at line 3185 of file cortex-m4-def.h.
| #define TIMER_RIS_CBERIS 0x00000400 |
Definition at line 3175 of file cortex-m4-def.h.
| #define TIMER_RIS_CBMRIS 0x00000200 |
Definition at line 3177 of file cortex-m4-def.h.
| #define TIMER_RIS_RTCRIS 0x00000008 |
Definition at line 3182 of file cortex-m4-def.h.
| #define TIMER_RIS_TAMRIS 0x00000010 |
Definition at line 3181 of file cortex-m4-def.h.
| #define TIMER_RIS_TATORIS 0x00000001 |
Definition at line 3187 of file cortex-m4-def.h.
| #define TIMER_RIS_TBMRIS 0x00000800 |
Definition at line 3174 of file cortex-m4-def.h.
| #define TIMER_RIS_TBTORIS 0x00000100 |
Definition at line 3179 of file cortex-m4-def.h.
| #define TIMER_RIS_WUERIS 0x00010000 |
Definition at line 3172 of file cortex-m4-def.h.
| #define TIMER_RTCPD_RTCPD_M 0x0000FFFF |
Definition at line 3355 of file cortex-m4-def.h.
| #define TIMER_RTCPD_RTCPD_S 0 |
Definition at line 3356 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT0_M 0x00000003 |
Definition at line 3128 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT0_NONE 0x00000000 |
Definition at line 3130 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT0_TA 0x00000001 |
Definition at line 3132 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT0_TATB 0x00000003 |
Definition at line 3138 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT0_TB 0x00000002 |
Definition at line 3135 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT1_M 0x0000000C |
Definition at line 3115 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT1_NONE 0x00000000 |
Definition at line 3117 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT1_TA 0x00000004 |
Definition at line 3119 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT1_TATB 0x0000000C |
Definition at line 3125 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT1_TB 0x00000008 |
Definition at line 3122 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT2_M 0x00000030 |
Definition at line 3102 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT2_NONE 0x00000000 |
Definition at line 3104 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT2_TA 0x00000010 |
Definition at line 3106 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT2_TATB 0x00000030 |
Definition at line 3112 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT2_TB 0x00000020 |
Definition at line 3109 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT3_M 0x000000C0 |
Definition at line 3089 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT3_NONE 0x00000000 |
Definition at line 3091 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT3_TA 0x00000040 |
Definition at line 3093 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT3_TATB 0x000000C0 |
Definition at line 3099 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT3_TB 0x00000080 |
Definition at line 3096 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT4_M 0x00000300 |
Definition at line 3076 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT4_NONE 0x00000000 |
Definition at line 3078 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT4_TA 0x00000100 |
Definition at line 3080 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT4_TATB 0x00000300 |
Definition at line 3086 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT4_TB 0x00000200 |
Definition at line 3083 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT5_M 0x00000C00 |
Definition at line 3063 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT5_NONE 0x00000000 |
Definition at line 3065 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT5_TA 0x00000400 |
Definition at line 3067 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT5_TATB 0x00000C00 |
Definition at line 3073 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCT5_TB 0x00000800 |
Definition at line 3070 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT0_M 0x00003000 |
Definition at line 3050 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT0_NONE 0x00000000 |
Definition at line 3052 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT0_TA 0x00001000 |
Definition at line 3054 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT0_TATB 0x00003000 |
Definition at line 3060 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT0_TB 0x00002000 |
Definition at line 3057 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT1_M 0x0000C000 |
Definition at line 3037 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT1_NONE 0x00000000 |
Definition at line 3039 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT1_TA 0x00004000 |
Definition at line 3041 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 |
Definition at line 3047 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT1_TB 0x00008000 |
Definition at line 3044 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT2_M 0x00030000 |
Definition at line 3024 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT2_NONE 0x00000000 |
Definition at line 3026 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT2_TA 0x00010000 |
Definition at line 3028 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT2_TATB 0x00030000 |
Definition at line 3034 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT2_TB 0x00020000 |
Definition at line 3031 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT3_M 0x000C0000 |
Definition at line 3011 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT3_NONE 0x00000000 |
Definition at line 3013 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT3_TA 0x00040000 |
Definition at line 3015 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 |
Definition at line 3021 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT3_TB 0x00080000 |
Definition at line 3018 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT4_M 0x00300000 |
Definition at line 2998 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT4_NONE 0x00000000 |
Definition at line 3000 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT4_TA 0x00100000 |
Definition at line 3002 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT4_TATB 0x00300000 |
Definition at line 3008 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT4_TB 0x00200000 |
Definition at line 3005 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT5_M 0x00C00000 |
Definition at line 2985 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT5_NONE 0x00000000 |
Definition at line 2987 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT5_TA 0x00400000 |
Definition at line 2989 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 |
Definition at line 2995 of file cortex-m4-def.h.
| #define TIMER_SYNC_SYNCWT5_TB 0x00800000 |
Definition at line 2992 of file cortex-m4-def.h.
| #define TIMER_TAILR_M 0xFFFFFFFF |
Definition at line 3245 of file cortex-m4-def.h.
| #define TIMER_TAILR_S 0 |
Definition at line 3247 of file cortex-m4-def.h.
| #define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF |
Definition at line 3264 of file cortex-m4-def.h.
| #define TIMER_TAMATCHR_TAMR_S 0 |
Definition at line 3265 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAAMS 0x00000008 |
Definition at line 2922 of file cortex-m4-def.h.
| #define TIMER_TAMR_TACDIR 0x00000010 |
Definition at line 2921 of file cortex-m4-def.h.
| #define TIMER_TAMR_TACMR 0x00000004 |
Definition at line 2924 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAILD 0x00000100 |
Definition at line 2916 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMIE 0x00000020 |
Definition at line 2919 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 |
Definition at line 2926 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMR_CAP 0x00000003 |
Definition at line 2928 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMR_M 0x00000003 |
Definition at line 2925 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMR_PERIOD 0x00000002 |
Definition at line 2927 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAMRSU 0x00000400 |
Definition at line 2912 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAPLO 0x00000800 |
Definition at line 2910 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAPWMIE 0x00000200 |
Definition at line 2914 of file cortex-m4-def.h.
| #define TIMER_TAMR_TASNAPS 0x00000080 |
Definition at line 2917 of file cortex-m4-def.h.
| #define TIMER_TAMR_TAWOT 0x00000040 |
Definition at line 2918 of file cortex-m4-def.h.
| #define TIMER_TAPMR_TAPSMR_M 0x000000FF |
Definition at line 3303 of file cortex-m4-def.h.
| #define TIMER_TAPMR_TAPSMR_S 0 |
Definition at line 3305 of file cortex-m4-def.h.
| #define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 |
Definition at line 3301 of file cortex-m4-def.h.
| #define TIMER_TAPMR_TAPSMRH_S 8 |
Definition at line 3304 of file cortex-m4-def.h.
| #define TIMER_TAPR_TAPSR_M 0x000000FF |
Definition at line 3282 of file cortex-m4-def.h.
| #define TIMER_TAPR_TAPSR_S 0 |
Definition at line 3284 of file cortex-m4-def.h.
| #define TIMER_TAPR_TAPSRH_M 0x0000FF00 |
Definition at line 3281 of file cortex-m4-def.h.
| #define TIMER_TAPR_TAPSRH_S 8 |
Definition at line 3283 of file cortex-m4-def.h.
| #define TIMER_TAPS_PSS_M 0x0000FFFF |
Definition at line 3363 of file cortex-m4-def.h.
| #define TIMER_TAPS_PSS_S 0 |
Definition at line 3364 of file cortex-m4-def.h.
| #define TIMER_TAPV_PSV_M 0x0000FFFF |
Definition at line 3379 of file cortex-m4-def.h.
| #define TIMER_TAPV_PSV_S 0 |
Definition at line 3380 of file cortex-m4-def.h.
| #define TIMER_TAR_M 0xFFFFFFFF |
Definition at line 3323 of file cortex-m4-def.h.
| #define TIMER_TAR_S 0 |
Definition at line 3324 of file cortex-m4-def.h.
| #define TIMER_TAV_M 0xFFFFFFFF |
Definition at line 3339 of file cortex-m4-def.h.
| #define TIMER_TAV_S 0 |
Definition at line 3340 of file cortex-m4-def.h.
| #define TIMER_TBILR_M 0xFFFFFFFF |
Definition at line 3254 of file cortex-m4-def.h.
| #define TIMER_TBILR_S 0 |
Definition at line 3256 of file cortex-m4-def.h.
| #define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF |
Definition at line 3273 of file cortex-m4-def.h.
| #define TIMER_TBMATCHR_TBMR_S 0 |
Definition at line 3274 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBAMS 0x00000008 |
Definition at line 2947 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBCDIR 0x00000010 |
Definition at line 2946 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBCMR 0x00000004 |
Definition at line 2949 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBILD 0x00000100 |
Definition at line 2941 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMIE 0x00000020 |
Definition at line 2944 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 |
Definition at line 2951 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMR_CAP 0x00000003 |
Definition at line 2953 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMR_M 0x00000003 |
Definition at line 2950 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMR_PERIOD 0x00000002 |
Definition at line 2952 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBMRSU 0x00000400 |
Definition at line 2937 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBPLO 0x00000800 |
Definition at line 2935 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBPWMIE 0x00000200 |
Definition at line 2939 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBSNAPS 0x00000080 |
Definition at line 2942 of file cortex-m4-def.h.
| #define TIMER_TBMR_TBWOT 0x00000040 |
Definition at line 2943 of file cortex-m4-def.h.
| #define TIMER_TBPMR_TBPSMR_M 0x000000FF |
Definition at line 3314 of file cortex-m4-def.h.
| #define TIMER_TBPMR_TBPSMR_S 0 |
Definition at line 3316 of file cortex-m4-def.h.
| #define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 |
Definition at line 3312 of file cortex-m4-def.h.
| #define TIMER_TBPMR_TBPSMRH_S 8 |
Definition at line 3315 of file cortex-m4-def.h.
| #define TIMER_TBPR_TBPSR_M 0x000000FF |
Definition at line 3292 of file cortex-m4-def.h.
| #define TIMER_TBPR_TBPSR_S 0 |
Definition at line 3294 of file cortex-m4-def.h.
| #define TIMER_TBPR_TBPSRH_M 0x0000FF00 |
Definition at line 3291 of file cortex-m4-def.h.
| #define TIMER_TBPR_TBPSRH_S 8 |
Definition at line 3293 of file cortex-m4-def.h.
| #define TIMER_TBPS_PSS_M 0x0000FFFF |
Definition at line 3371 of file cortex-m4-def.h.
| #define TIMER_TBPS_PSS_S 0 |
Definition at line 3372 of file cortex-m4-def.h.
| #define TIMER_TBPV_PSV_M 0x0000FFFF |
Definition at line 3387 of file cortex-m4-def.h.
| #define TIMER_TBPV_PSV_S 0 |
Definition at line 3388 of file cortex-m4-def.h.
| #define TIMER_TBR_M 0xFFFFFFFF |
Definition at line 3331 of file cortex-m4-def.h.
| #define TIMER_TBR_S 0 |
Definition at line 3332 of file cortex-m4-def.h.
| #define TIMER_TBV_M 0xFFFFFFFF |
Definition at line 3347 of file cortex-m4-def.h.
| #define TIMER_TBV_S 0 |
Definition at line 3348 of file cortex-m4-def.h.
| #define UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4)) |
Definition at line 326 of file cortex-m4-def.h.
| #define UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8)) |
Definition at line 327 of file cortex-m4-def.h.
| #define UART0_CC_R (*((volatile unsigned long *)0x4000CFC8)) |
Definition at line 329 of file cortex-m4-def.h.
| #define UART0_CTL_R (*((volatile unsigned long *)0x4000C030)) |
Definition at line 316 of file cortex-m4-def.h.
| #define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048)) |
Definition at line 322 of file cortex-m4-def.h.
| #define UART0_DR_R (*((volatile unsigned long *)0x4000C000)) |
Definition at line 308 of file cortex-m4-def.h.
| #define UART0_ECR_R (*((volatile unsigned long *)0x4000C004)) |
Definition at line 310 of file cortex-m4-def.h.
| #define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028)) |
Definition at line 314 of file cortex-m4-def.h.
| #define UART0_FR_R (*((volatile unsigned long *)0x4000C018)) |
Definition at line 311 of file cortex-m4-def.h.
| #define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024)) |
Definition at line 313 of file cortex-m4-def.h.
| #define UART0_ICR_R (*((volatile unsigned long *)0x4000C044)) |
Definition at line 321 of file cortex-m4-def.h.
| #define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034)) |
Definition at line 317 of file cortex-m4-def.h.
| #define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020)) |
Definition at line 312 of file cortex-m4-def.h.
| #define UART0_IM_R (*((volatile unsigned long *)0x4000C038)) |
Definition at line 318 of file cortex-m4-def.h.
| #define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C)) |
Definition at line 315 of file cortex-m4-def.h.
| #define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090)) |
Definition at line 323 of file cortex-m4-def.h.
| #define UART0_LSS_R (*((volatile unsigned long *)0x4000C094)) |
Definition at line 324 of file cortex-m4-def.h.
| #define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098)) |
Definition at line 325 of file cortex-m4-def.h.
| #define UART0_MIS_R (*((volatile unsigned long *)0x4000C040)) |
Definition at line 320 of file cortex-m4-def.h.
| #define UART0_PP_R (*((volatile unsigned long *)0x4000CFC0)) |
Definition at line 328 of file cortex-m4-def.h.
| #define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C)) |
Definition at line 319 of file cortex-m4-def.h.
| #define UART0_RSR_R (*((volatile unsigned long *)0x4000C004)) |
Definition at line 309 of file cortex-m4-def.h.
| #define UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4)) |
Definition at line 354 of file cortex-m4-def.h.
| #define UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8)) |
Definition at line 355 of file cortex-m4-def.h.
| #define UART1_CC_R (*((volatile unsigned long *)0x4000DFC8)) |
Definition at line 357 of file cortex-m4-def.h.
| #define UART1_CTL_R (*((volatile unsigned long *)0x4000D030)) |
Definition at line 344 of file cortex-m4-def.h.
| #define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048)) |
Definition at line 350 of file cortex-m4-def.h.
| #define UART1_DR_R (*((volatile unsigned long *)0x4000D000)) |
Definition at line 336 of file cortex-m4-def.h.
| #define UART1_ECR_R (*((volatile unsigned long *)0x4000D004)) |
Definition at line 338 of file cortex-m4-def.h.
| #define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028)) |
Definition at line 342 of file cortex-m4-def.h.
| #define UART1_FR_R (*((volatile unsigned long *)0x4000D018)) |
Definition at line 339 of file cortex-m4-def.h.
| #define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024)) |
Definition at line 341 of file cortex-m4-def.h.
| #define UART1_ICR_R (*((volatile unsigned long *)0x4000D044)) |
Definition at line 349 of file cortex-m4-def.h.
| #define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034)) |
Definition at line 345 of file cortex-m4-def.h.
| #define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020)) |
Definition at line 340 of file cortex-m4-def.h.
| #define UART1_IM_R (*((volatile unsigned long *)0x4000D038)) |
Definition at line 346 of file cortex-m4-def.h.
| #define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C)) |
Definition at line 343 of file cortex-m4-def.h.
| #define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090)) |
Definition at line 351 of file cortex-m4-def.h.
| #define UART1_LSS_R (*((volatile unsigned long *)0x4000D094)) |
Definition at line 352 of file cortex-m4-def.h.
| #define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098)) |
Definition at line 353 of file cortex-m4-def.h.
| #define UART1_MIS_R (*((volatile unsigned long *)0x4000D040)) |
Definition at line 348 of file cortex-m4-def.h.
| #define UART1_PP_R (*((volatile unsigned long *)0x4000DFC0)) |
Definition at line 356 of file cortex-m4-def.h.
| #define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C)) |
Definition at line 347 of file cortex-m4-def.h.
| #define UART1_RSR_R (*((volatile unsigned long *)0x4000D004)) |
Definition at line 337 of file cortex-m4-def.h.
| #define UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4)) |
Definition at line 382 of file cortex-m4-def.h.
| #define UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8)) |
Definition at line 383 of file cortex-m4-def.h.
| #define UART2_CC_R (*((volatile unsigned long *)0x4000EFC8)) |
Definition at line 385 of file cortex-m4-def.h.
| #define UART2_CTL_R (*((volatile unsigned long *)0x4000E030)) |
Definition at line 372 of file cortex-m4-def.h.
| #define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048)) |
Definition at line 378 of file cortex-m4-def.h.
| #define UART2_DR_R (*((volatile unsigned long *)0x4000E000)) |
Definition at line 364 of file cortex-m4-def.h.
| #define UART2_ECR_R (*((volatile unsigned long *)0x4000E004)) |
Definition at line 366 of file cortex-m4-def.h.
| #define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028)) |
Definition at line 370 of file cortex-m4-def.h.
| #define UART2_FR_R (*((volatile unsigned long *)0x4000E018)) |
Definition at line 367 of file cortex-m4-def.h.
| #define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024)) |
Definition at line 369 of file cortex-m4-def.h.
| #define UART2_ICR_R (*((volatile unsigned long *)0x4000E044)) |
Definition at line 377 of file cortex-m4-def.h.
| #define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034)) |
Definition at line 373 of file cortex-m4-def.h.
| #define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020)) |
Definition at line 368 of file cortex-m4-def.h.
| #define UART2_IM_R (*((volatile unsigned long *)0x4000E038)) |
Definition at line 374 of file cortex-m4-def.h.
| #define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C)) |
Definition at line 371 of file cortex-m4-def.h.
| #define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090)) |
Definition at line 379 of file cortex-m4-def.h.
| #define UART2_LSS_R (*((volatile unsigned long *)0x4000E094)) |
Definition at line 380 of file cortex-m4-def.h.
| #define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098)) |
Definition at line 381 of file cortex-m4-def.h.
| #define UART2_MIS_R (*((volatile unsigned long *)0x4000E040)) |
Definition at line 376 of file cortex-m4-def.h.
| #define UART2_PP_R (*((volatile unsigned long *)0x4000EFC0)) |
Definition at line 384 of file cortex-m4-def.h.
| #define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C)) |
Definition at line 375 of file cortex-m4-def.h.
| #define UART2_RSR_R (*((volatile unsigned long *)0x4000E004)) |
Definition at line 365 of file cortex-m4-def.h.
| #define UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4)) |
Definition at line 410 of file cortex-m4-def.h.
| #define UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8)) |
Definition at line 411 of file cortex-m4-def.h.
| #define UART3_CC_R (*((volatile unsigned long *)0x4000FFC8)) |
Definition at line 413 of file cortex-m4-def.h.
| #define UART3_CTL_R (*((volatile unsigned long *)0x4000F030)) |
Definition at line 400 of file cortex-m4-def.h.
| #define UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048)) |
Definition at line 406 of file cortex-m4-def.h.
| #define UART3_DR_R (*((volatile unsigned long *)0x4000F000)) |
Definition at line 392 of file cortex-m4-def.h.
| #define UART3_ECR_R (*((volatile unsigned long *)0x4000F004)) |
Definition at line 394 of file cortex-m4-def.h.
| #define UART3_FBRD_R (*((volatile unsigned long *)0x4000F028)) |
Definition at line 398 of file cortex-m4-def.h.
| #define UART3_FR_R (*((volatile unsigned long *)0x4000F018)) |
Definition at line 395 of file cortex-m4-def.h.
| #define UART3_IBRD_R (*((volatile unsigned long *)0x4000F024)) |
Definition at line 397 of file cortex-m4-def.h.
| #define UART3_ICR_R (*((volatile unsigned long *)0x4000F044)) |
Definition at line 405 of file cortex-m4-def.h.
| #define UART3_IFLS_R (*((volatile unsigned long *)0x4000F034)) |
Definition at line 401 of file cortex-m4-def.h.
| #define UART3_ILPR_R (*((volatile unsigned long *)0x4000F020)) |
Definition at line 396 of file cortex-m4-def.h.
| #define UART3_IM_R (*((volatile unsigned long *)0x4000F038)) |
Definition at line 402 of file cortex-m4-def.h.
| #define UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C)) |
Definition at line 399 of file cortex-m4-def.h.
| #define UART3_LCTL_R (*((volatile unsigned long *)0x4000F090)) |
Definition at line 407 of file cortex-m4-def.h.
| #define UART3_LSS_R (*((volatile unsigned long *)0x4000F094)) |
Definition at line 408 of file cortex-m4-def.h.
| #define UART3_LTIM_R (*((volatile unsigned long *)0x4000F098)) |
Definition at line 409 of file cortex-m4-def.h.
| #define UART3_MIS_R (*((volatile unsigned long *)0x4000F040)) |
Definition at line 404 of file cortex-m4-def.h.
| #define UART3_PP_R (*((volatile unsigned long *)0x4000FFC0)) |
Definition at line 412 of file cortex-m4-def.h.
| #define UART3_RIS_R (*((volatile unsigned long *)0x4000F03C)) |
Definition at line 403 of file cortex-m4-def.h.
| #define UART3_RSR_R (*((volatile unsigned long *)0x4000F004)) |
Definition at line 393 of file cortex-m4-def.h.
| #define UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4)) |
Definition at line 438 of file cortex-m4-def.h.
| #define UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8)) |
Definition at line 439 of file cortex-m4-def.h.
| #define UART4_CC_R (*((volatile unsigned long *)0x40010FC8)) |
Definition at line 441 of file cortex-m4-def.h.
| #define UART4_CTL_R (*((volatile unsigned long *)0x40010030)) |
Definition at line 428 of file cortex-m4-def.h.
| #define UART4_DMACTL_R (*((volatile unsigned long *)0x40010048)) |
Definition at line 434 of file cortex-m4-def.h.
| #define UART4_DR_R (*((volatile unsigned long *)0x40010000)) |
Definition at line 420 of file cortex-m4-def.h.
| #define UART4_ECR_R (*((volatile unsigned long *)0x40010004)) |
Definition at line 422 of file cortex-m4-def.h.
| #define UART4_FBRD_R (*((volatile unsigned long *)0x40010028)) |
Definition at line 426 of file cortex-m4-def.h.
| #define UART4_FR_R (*((volatile unsigned long *)0x40010018)) |
Definition at line 423 of file cortex-m4-def.h.
| #define UART4_IBRD_R (*((volatile unsigned long *)0x40010024)) |
Definition at line 425 of file cortex-m4-def.h.
| #define UART4_ICR_R (*((volatile unsigned long *)0x40010044)) |
Definition at line 433 of file cortex-m4-def.h.
| #define UART4_IFLS_R (*((volatile unsigned long *)0x40010034)) |
Definition at line 429 of file cortex-m4-def.h.
| #define UART4_ILPR_R (*((volatile unsigned long *)0x40010020)) |
Definition at line 424 of file cortex-m4-def.h.
| #define UART4_IM_R (*((volatile unsigned long *)0x40010038)) |
Definition at line 430 of file cortex-m4-def.h.
| #define UART4_LCRH_R (*((volatile unsigned long *)0x4001002C)) |
Definition at line 427 of file cortex-m4-def.h.
| #define UART4_LCTL_R (*((volatile unsigned long *)0x40010090)) |
Definition at line 435 of file cortex-m4-def.h.
| #define UART4_LSS_R (*((volatile unsigned long *)0x40010094)) |
Definition at line 436 of file cortex-m4-def.h.
| #define UART4_LTIM_R (*((volatile unsigned long *)0x40010098)) |
Definition at line 437 of file cortex-m4-def.h.
| #define UART4_MIS_R (*((volatile unsigned long *)0x40010040)) |
Definition at line 432 of file cortex-m4-def.h.
| #define UART4_PP_R (*((volatile unsigned long *)0x40010FC0)) |
Definition at line 440 of file cortex-m4-def.h.
| #define UART4_RIS_R (*((volatile unsigned long *)0x4001003C)) |
Definition at line 431 of file cortex-m4-def.h.
| #define UART4_RSR_R (*((volatile unsigned long *)0x40010004)) |
Definition at line 421 of file cortex-m4-def.h.
| #define UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4)) |
Definition at line 466 of file cortex-m4-def.h.
| #define UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8)) |
Definition at line 467 of file cortex-m4-def.h.
| #define UART5_CC_R (*((volatile unsigned long *)0x40011FC8)) |
Definition at line 469 of file cortex-m4-def.h.
| #define UART5_CTL_R (*((volatile unsigned long *)0x40011030)) |
Definition at line 456 of file cortex-m4-def.h.
| #define UART5_DMACTL_R (*((volatile unsigned long *)0x40011048)) |
Definition at line 462 of file cortex-m4-def.h.
| #define UART5_DR_R (*((volatile unsigned long *)0x40011000)) |
Definition at line 448 of file cortex-m4-def.h.
| #define UART5_ECR_R (*((volatile unsigned long *)0x40011004)) |
Definition at line 450 of file cortex-m4-def.h.
| #define UART5_FBRD_R (*((volatile unsigned long *)0x40011028)) |
Definition at line 454 of file cortex-m4-def.h.
| #define UART5_FR_R (*((volatile unsigned long *)0x40011018)) |
Definition at line 451 of file cortex-m4-def.h.
| #define UART5_IBRD_R (*((volatile unsigned long *)0x40011024)) |
Definition at line 453 of file cortex-m4-def.h.
| #define UART5_ICR_R (*((volatile unsigned long *)0x40011044)) |
Definition at line 461 of file cortex-m4-def.h.
| #define UART5_IFLS_R (*((volatile unsigned long *)0x40011034)) |
Definition at line 457 of file cortex-m4-def.h.
| #define UART5_ILPR_R (*((volatile unsigned long *)0x40011020)) |
Definition at line 452 of file cortex-m4-def.h.
| #define UART5_IM_R (*((volatile unsigned long *)0x40011038)) |
Definition at line 458 of file cortex-m4-def.h.
| #define UART5_LCRH_R (*((volatile unsigned long *)0x4001102C)) |
Definition at line 455 of file cortex-m4-def.h.
| #define UART5_LCTL_R (*((volatile unsigned long *)0x40011090)) |
Definition at line 463 of file cortex-m4-def.h.
| #define UART5_LSS_R (*((volatile unsigned long *)0x40011094)) |
Definition at line 464 of file cortex-m4-def.h.
| #define UART5_LTIM_R (*((volatile unsigned long *)0x40011098)) |
Definition at line 465 of file cortex-m4-def.h.
| #define UART5_MIS_R (*((volatile unsigned long *)0x40011040)) |
Definition at line 460 of file cortex-m4-def.h.
| #define UART5_PP_R (*((volatile unsigned long *)0x40011FC0)) |
Definition at line 468 of file cortex-m4-def.h.
| #define UART5_RIS_R (*((volatile unsigned long *)0x4001103C)) |
Definition at line 459 of file cortex-m4-def.h.
| #define UART5_RSR_R (*((volatile unsigned long *)0x40011004)) |
Definition at line 449 of file cortex-m4-def.h.
| #define UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4)) |
Definition at line 494 of file cortex-m4-def.h.
| #define UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8)) |
Definition at line 495 of file cortex-m4-def.h.
| #define UART6_CC_R (*((volatile unsigned long *)0x40012FC8)) |
Definition at line 497 of file cortex-m4-def.h.
| #define UART6_CTL_R (*((volatile unsigned long *)0x40012030)) |
Definition at line 484 of file cortex-m4-def.h.
| #define UART6_DMACTL_R (*((volatile unsigned long *)0x40012048)) |
Definition at line 490 of file cortex-m4-def.h.
| #define UART6_DR_R (*((volatile unsigned long *)0x40012000)) |
Definition at line 476 of file cortex-m4-def.h.
| #define UART6_ECR_R (*((volatile unsigned long *)0x40012004)) |
Definition at line 478 of file cortex-m4-def.h.
| #define UART6_FBRD_R (*((volatile unsigned long *)0x40012028)) |
Definition at line 482 of file cortex-m4-def.h.
| #define UART6_FR_R (*((volatile unsigned long *)0x40012018)) |
Definition at line 479 of file cortex-m4-def.h.
| #define UART6_IBRD_R (*((volatile unsigned long *)0x40012024)) |
Definition at line 481 of file cortex-m4-def.h.
| #define UART6_ICR_R (*((volatile unsigned long *)0x40012044)) |
Definition at line 489 of file cortex-m4-def.h.
| #define UART6_IFLS_R (*((volatile unsigned long *)0x40012034)) |
Definition at line 485 of file cortex-m4-def.h.
| #define UART6_ILPR_R (*((volatile unsigned long *)0x40012020)) |
Definition at line 480 of file cortex-m4-def.h.
| #define UART6_IM_R (*((volatile unsigned long *)0x40012038)) |
Definition at line 486 of file cortex-m4-def.h.
| #define UART6_LCRH_R (*((volatile unsigned long *)0x4001202C)) |
Definition at line 483 of file cortex-m4-def.h.
| #define UART6_LCTL_R (*((volatile unsigned long *)0x40012090)) |
Definition at line 491 of file cortex-m4-def.h.
| #define UART6_LSS_R (*((volatile unsigned long *)0x40012094)) |
Definition at line 492 of file cortex-m4-def.h.
| #define UART6_LTIM_R (*((volatile unsigned long *)0x40012098)) |
Definition at line 493 of file cortex-m4-def.h.
| #define UART6_MIS_R (*((volatile unsigned long *)0x40012040)) |
Definition at line 488 of file cortex-m4-def.h.
| #define UART6_PP_R (*((volatile unsigned long *)0x40012FC0)) |
Definition at line 496 of file cortex-m4-def.h.
| #define UART6_RIS_R (*((volatile unsigned long *)0x4001203C)) |
Definition at line 487 of file cortex-m4-def.h.
| #define UART6_RSR_R (*((volatile unsigned long *)0x40012004)) |
Definition at line 477 of file cortex-m4-def.h.
| #define UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4)) |
Definition at line 522 of file cortex-m4-def.h.
| #define UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8)) |
Definition at line 523 of file cortex-m4-def.h.
| #define UART7_CC_R (*((volatile unsigned long *)0x40013FC8)) |
Definition at line 525 of file cortex-m4-def.h.
| #define UART7_CTL_R (*((volatile unsigned long *)0x40013030)) |
Definition at line 512 of file cortex-m4-def.h.
| #define UART7_DMACTL_R (*((volatile unsigned long *)0x40013048)) |
Definition at line 518 of file cortex-m4-def.h.
| #define UART7_DR_R (*((volatile unsigned long *)0x40013000)) |
Definition at line 504 of file cortex-m4-def.h.
| #define UART7_ECR_R (*((volatile unsigned long *)0x40013004)) |
Definition at line 506 of file cortex-m4-def.h.
| #define UART7_FBRD_R (*((volatile unsigned long *)0x40013028)) |
Definition at line 510 of file cortex-m4-def.h.
| #define UART7_FR_R (*((volatile unsigned long *)0x40013018)) |
Definition at line 507 of file cortex-m4-def.h.
| #define UART7_IBRD_R (*((volatile unsigned long *)0x40013024)) |
Definition at line 509 of file cortex-m4-def.h.
| #define UART7_ICR_R (*((volatile unsigned long *)0x40013044)) |
Definition at line 517 of file cortex-m4-def.h.
| #define UART7_IFLS_R (*((volatile unsigned long *)0x40013034)) |
Definition at line 513 of file cortex-m4-def.h.
| #define UART7_ILPR_R (*((volatile unsigned long *)0x40013020)) |
Definition at line 508 of file cortex-m4-def.h.
| #define UART7_IM_R (*((volatile unsigned long *)0x40013038)) |
Definition at line 514 of file cortex-m4-def.h.
| #define UART7_LCRH_R (*((volatile unsigned long *)0x4001302C)) |
Definition at line 511 of file cortex-m4-def.h.
| #define UART7_LCTL_R (*((volatile unsigned long *)0x40013090)) |
Definition at line 519 of file cortex-m4-def.h.
| #define UART7_LSS_R (*((volatile unsigned long *)0x40013094)) |
Definition at line 520 of file cortex-m4-def.h.
| #define UART7_LTIM_R (*((volatile unsigned long *)0x40013098)) |
Definition at line 521 of file cortex-m4-def.h.
| #define UART7_MIS_R (*((volatile unsigned long *)0x40013040)) |
Definition at line 516 of file cortex-m4-def.h.
| #define UART7_PP_R (*((volatile unsigned long *)0x40013FC0)) |
Definition at line 524 of file cortex-m4-def.h.
| #define UART7_RIS_R (*((volatile unsigned long *)0x4001303C)) |
Definition at line 515 of file cortex-m4-def.h.
| #define UART7_RSR_R (*((volatile unsigned long *)0x40013004)) |
Definition at line 505 of file cortex-m4-def.h.
| #define UART_9BITADDR_9BITEN 0x00008000 |
Definition at line 2660 of file cortex-m4-def.h.
| #define UART_9BITADDR_ADDR_M 0x000000FF |
Definition at line 2661 of file cortex-m4-def.h.
| #define UART_9BITADDR_ADDR_S 0 |
Definition at line 2662 of file cortex-m4-def.h.
| #define UART_9BITAMASK_MASK_M 0x000000FF |
Definition at line 2670 of file cortex-m4-def.h.
| #define UART_9BITAMASK_MASK_S 0 |
Definition at line 2671 of file cortex-m4-def.h.
| #define UART_CC_CS_M 0x0000000F |
Definition at line 2686 of file cortex-m4-def.h.
| #define UART_CC_CS_PIOSC 0x00000005 |
Definition at line 2688 of file cortex-m4-def.h.
| #define UART_CC_CS_SYSCLK 0x00000000 |
Definition at line 2687 of file cortex-m4-def.h.
| #define UART_CTL_EOT 0x00000010 |
Definition at line 2488 of file cortex-m4-def.h.
| #define UART_CTL_HSE 0x00000020 |
Definition at line 2487 of file cortex-m4-def.h.
| #define UART_CTL_LBE 0x00000080 |
Definition at line 2485 of file cortex-m4-def.h.
| #define UART_CTL_LIN 0x00000040 |
Definition at line 2486 of file cortex-m4-def.h.
| #define UART_CTL_RXE 0x00000200 |
Definition at line 2483 of file cortex-m4-def.h.
| #define UART_CTL_SIREN 0x00000002 |
Definition at line 2491 of file cortex-m4-def.h.
| #define UART_CTL_SIRLP 0x00000004 |
Definition at line 2490 of file cortex-m4-def.h.
| #define UART_CTL_SMART 0x00000008 |
Definition at line 2489 of file cortex-m4-def.h.
| #define UART_CTL_TXE 0x00000100 |
Definition at line 2484 of file cortex-m4-def.h.
| #define UART_CTL_UARTEN 0x00000001 |
Definition at line 2492 of file cortex-m4-def.h.
| #define UART_DMACTL_DMAERR 0x00000004 |
Definition at line 2621 of file cortex-m4-def.h.
| #define UART_DMACTL_RXDMAE 0x00000001 |
Definition at line 2623 of file cortex-m4-def.h.
| #define UART_DMACTL_TXDMAE 0x00000002 |
Definition at line 2622 of file cortex-m4-def.h.
| #define UART_DR_BE 0x00000400 |
Definition at line 2401 of file cortex-m4-def.h.
| #define UART_DR_DATA_M 0x000000FF |
Definition at line 2404 of file cortex-m4-def.h.
| #define UART_DR_DATA_S 0 |
Definition at line 2405 of file cortex-m4-def.h.
| #define UART_DR_FE 0x00000100 |
Definition at line 2403 of file cortex-m4-def.h.
| #define UART_DR_OE 0x00000800 |
Definition at line 2400 of file cortex-m4-def.h.
| #define UART_DR_PE 0x00000200 |
Definition at line 2402 of file cortex-m4-def.h.
| #define UART_ECR_DATA_M 0x000000FF |
Definition at line 2422 of file cortex-m4-def.h.
| #define UART_ECR_DATA_S 0 |
Definition at line 2423 of file cortex-m4-def.h.
| #define UART_FBRD_DIVFRAC_M 0x0000003F |
Definition at line 2458 of file cortex-m4-def.h.
| #define UART_FBRD_DIVFRAC_S 0 |
Definition at line 2459 of file cortex-m4-def.h.
| #define UART_FR_BUSY 0x00000008 |
Definition at line 2434 of file cortex-m4-def.h.
| #define UART_FR_CTS 0x00000001 |
Definition at line 2435 of file cortex-m4-def.h.
| #define UART_FR_RXFE 0x00000010 |
Definition at line 2433 of file cortex-m4-def.h.
| #define UART_FR_RXFF 0x00000040 |
Definition at line 2431 of file cortex-m4-def.h.
| #define UART_FR_TXFE 0x00000080 |
Definition at line 2430 of file cortex-m4-def.h.
| #define UART_FR_TXFF 0x00000020 |
Definition at line 2432 of file cortex-m4-def.h.
| #define UART_IBRD_DIVINT_M 0x0000FFFF |
Definition at line 2450 of file cortex-m4-def.h.
| #define UART_IBRD_DIVINT_S 0 |
Definition at line 2451 of file cortex-m4-def.h.
| #define UART_ICR_9BITIC 0x00001000 |
Definition at line 2605 of file cortex-m4-def.h.
| #define UART_ICR_BEIC 0x00000200 |
Definition at line 2607 of file cortex-m4-def.h.
| #define UART_ICR_CTSMIC 0x00000002 |
Definition at line 2613 of file cortex-m4-def.h.
| #define UART_ICR_FEIC 0x00000080 |
Definition at line 2609 of file cortex-m4-def.h.
| #define UART_ICR_LME1IC 0x00004000 |
Definition at line 2602 of file cortex-m4-def.h.
| #define UART_ICR_LME5IC 0x00008000 |
Definition at line 2601 of file cortex-m4-def.h.
| #define UART_ICR_LMSBIC 0x00002000 |
Definition at line 2603 of file cortex-m4-def.h.
| #define UART_ICR_OEIC 0x00000400 |
Definition at line 2606 of file cortex-m4-def.h.
| #define UART_ICR_PEIC 0x00000100 |
Definition at line 2608 of file cortex-m4-def.h.
| #define UART_ICR_RTIC 0x00000040 |
Definition at line 2610 of file cortex-m4-def.h.
| #define UART_ICR_RXIC 0x00000010 |
Definition at line 2612 of file cortex-m4-def.h.
| #define UART_ICR_TXIC 0x00000020 |
Definition at line 2611 of file cortex-m4-def.h.
| #define UART_IFLS_RX1_8 0x00000000 |
Definition at line 2501 of file cortex-m4-def.h.
| #define UART_IFLS_RX2_8 0x00000008 |
Definition at line 2502 of file cortex-m4-def.h.
| #define UART_IFLS_RX4_8 0x00000010 |
Definition at line 2503 of file cortex-m4-def.h.
| #define UART_IFLS_RX6_8 0x00000018 |
Definition at line 2504 of file cortex-m4-def.h.
| #define UART_IFLS_RX7_8 0x00000020 |
Definition at line 2505 of file cortex-m4-def.h.
| #define UART_IFLS_RX_M 0x00000038 |
Definition at line 2499 of file cortex-m4-def.h.
| #define UART_IFLS_TX1_8 0x00000000 |
Definition at line 2508 of file cortex-m4-def.h.
| #define UART_IFLS_TX2_8 0x00000001 |
Definition at line 2509 of file cortex-m4-def.h.
| #define UART_IFLS_TX4_8 0x00000002 |
Definition at line 2510 of file cortex-m4-def.h.
| #define UART_IFLS_TX6_8 0x00000003 |
Definition at line 2511 of file cortex-m4-def.h.
| #define UART_IFLS_TX7_8 0x00000004 |
Definition at line 2512 of file cortex-m4-def.h.
| #define UART_IFLS_TX_M 0x00000007 |
Definition at line 2506 of file cortex-m4-def.h.
| #define UART_ILPR_ILPDVSR_M 0x000000FF |
Definition at line 2442 of file cortex-m4-def.h.
| #define UART_ILPR_ILPDVSR_S 0 |
Definition at line 2443 of file cortex-m4-def.h.
| #define UART_IM_9BITIM 0x00001000 |
Definition at line 2523 of file cortex-m4-def.h.
| #define UART_IM_BEIM 0x00000200 |
Definition at line 2526 of file cortex-m4-def.h.
| #define UART_IM_CTSMIM 0x00000002 |
Definition at line 2534 of file cortex-m4-def.h.
| #define UART_IM_FEIM 0x00000080 |
Definition at line 2528 of file cortex-m4-def.h.
| #define UART_IM_LME1IM 0x00004000 |
Definition at line 2520 of file cortex-m4-def.h.
| #define UART_IM_LME5IM 0x00008000 |
Definition at line 2519 of file cortex-m4-def.h.
| #define UART_IM_LMSBIM 0x00002000 |
Definition at line 2521 of file cortex-m4-def.h.
| #define UART_IM_OEIM 0x00000400 |
Definition at line 2524 of file cortex-m4-def.h.
| #define UART_IM_PEIM 0x00000100 |
Definition at line 2527 of file cortex-m4-def.h.
| #define UART_IM_RTIM 0x00000040 |
Definition at line 2530 of file cortex-m4-def.h.
| #define UART_IM_RXIM 0x00000010 |
Definition at line 2533 of file cortex-m4-def.h.
| #define UART_IM_TXIM 0x00000020 |
Definition at line 2532 of file cortex-m4-def.h.
| #define UART_LCRH_BRK 0x00000001 |
Definition at line 2476 of file cortex-m4-def.h.
| #define UART_LCRH_EPS 0x00000004 |
Definition at line 2474 of file cortex-m4-def.h.
| #define UART_LCRH_FEN 0x00000010 |
Definition at line 2472 of file cortex-m4-def.h.
| #define UART_LCRH_PEN 0x00000002 |
Definition at line 2475 of file cortex-m4-def.h.
| #define UART_LCRH_SPS 0x00000080 |
Definition at line 2466 of file cortex-m4-def.h.
| #define UART_LCRH_STP2 0x00000008 |
Definition at line 2473 of file cortex-m4-def.h.
| #define UART_LCRH_WLEN_5 0x00000000 |
Definition at line 2468 of file cortex-m4-def.h.
| #define UART_LCRH_WLEN_6 0x00000020 |
Definition at line 2469 of file cortex-m4-def.h.
| #define UART_LCRH_WLEN_7 0x00000040 |
Definition at line 2470 of file cortex-m4-def.h.
| #define UART_LCRH_WLEN_8 0x00000060 |
Definition at line 2471 of file cortex-m4-def.h.
| #define UART_LCRH_WLEN_M 0x00000060 |
Definition at line 2467 of file cortex-m4-def.h.
| #define UART_LCTL_BLEN_13T 0x00000000 |
Definition at line 2631 of file cortex-m4-def.h.
| #define UART_LCTL_BLEN_14T 0x00000010 |
Definition at line 2633 of file cortex-m4-def.h.
| #define UART_LCTL_BLEN_15T 0x00000020 |
Definition at line 2634 of file cortex-m4-def.h.
| #define UART_LCTL_BLEN_16T 0x00000030 |
Definition at line 2635 of file cortex-m4-def.h.
| #define UART_LCTL_BLEN_M 0x00000030 |
Definition at line 2630 of file cortex-m4-def.h.
| #define UART_LCTL_MASTER 0x00000001 |
Definition at line 2636 of file cortex-m4-def.h.
| #define UART_LSS_TSS_M 0x0000FFFF |
Definition at line 2643 of file cortex-m4-def.h.
| #define UART_LSS_TSS_S 0 |
Definition at line 2644 of file cortex-m4-def.h.
| #define UART_LTIM_TIMER_M 0x0000FFFF |
Definition at line 2651 of file cortex-m4-def.h.
| #define UART_LTIM_TIMER_S 0 |
Definition at line 2652 of file cortex-m4-def.h.
| #define UART_MIS_9BITMIS 0x00001000 |
Definition at line 2577 of file cortex-m4-def.h.
| #define UART_MIS_BEMIS 0x00000200 |
Definition at line 2581 of file cortex-m4-def.h.
| #define UART_MIS_CTSMIS 0x00000002 |
Definition at line 2593 of file cortex-m4-def.h.
| #define UART_MIS_FEMIS 0x00000080 |
Definition at line 2585 of file cortex-m4-def.h.
| #define UART_MIS_LME1MIS 0x00004000 |
Definition at line 2573 of file cortex-m4-def.h.
| #define UART_MIS_LME5MIS 0x00008000 |
Definition at line 2571 of file cortex-m4-def.h.
| #define UART_MIS_LMSBMIS 0x00002000 |
Definition at line 2575 of file cortex-m4-def.h.
| #define UART_MIS_OEMIS 0x00000400 |
Definition at line 2579 of file cortex-m4-def.h.
| #define UART_MIS_PEMIS 0x00000100 |
Definition at line 2583 of file cortex-m4-def.h.
| #define UART_MIS_RTMIS 0x00000040 |
Definition at line 2587 of file cortex-m4-def.h.
| #define UART_MIS_RXMIS 0x00000010 |
Definition at line 2591 of file cortex-m4-def.h.
| #define UART_MIS_TXMIS 0x00000020 |
Definition at line 2589 of file cortex-m4-def.h.
| #define UART_PP_NB 0x00000002 |
Definition at line 2678 of file cortex-m4-def.h.
| #define UART_PP_SC 0x00000001 |
Definition at line 2679 of file cortex-m4-def.h.
| #define UART_RIS_9BITRIS 0x00001000 |
Definition at line 2548 of file cortex-m4-def.h.
| #define UART_RIS_BERIS 0x00000200 |
Definition at line 2551 of file cortex-m4-def.h.
| #define UART_RIS_CTSRIS 0x00000002 |
Definition at line 2563 of file cortex-m4-def.h.
| #define UART_RIS_FERIS 0x00000080 |
Definition at line 2555 of file cortex-m4-def.h.
| #define UART_RIS_LME1RIS 0x00004000 |
Definition at line 2544 of file cortex-m4-def.h.
| #define UART_RIS_LME5RIS 0x00008000 |
Definition at line 2542 of file cortex-m4-def.h.
| #define UART_RIS_LMSBRIS 0x00002000 |
Definition at line 2546 of file cortex-m4-def.h.
| #define UART_RIS_OERIS 0x00000400 |
Definition at line 2549 of file cortex-m4-def.h.
| #define UART_RIS_PERIS 0x00000100 |
Definition at line 2553 of file cortex-m4-def.h.
| #define UART_RIS_RTRIS 0x00000040 |
Definition at line 2557 of file cortex-m4-def.h.
| #define UART_RIS_RXRIS 0x00000010 |
Definition at line 2561 of file cortex-m4-def.h.
| #define UART_RIS_TXRIS 0x00000020 |
Definition at line 2559 of file cortex-m4-def.h.
| #define UART_RSR_BE 0x00000004 |
Definition at line 2413 of file cortex-m4-def.h.
| #define UART_RSR_FE 0x00000001 |
Definition at line 2415 of file cortex-m4-def.h.
| #define UART_RSR_OE 0x00000008 |
Definition at line 2412 of file cortex-m4-def.h.
| #define UART_RSR_PE 0x00000002 |
Definition at line 2414 of file cortex-m4-def.h.
| #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF |
Definition at line 8338 of file cortex-m4-def.h.
| #define UDMA_ALTBASE_ADDR_S 0 |
Definition at line 8340 of file cortex-m4-def.h.
| #define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C)) |
Definition at line 1822 of file cortex-m4-def.h.
| #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF |
Definition at line 8414 of file cortex-m4-def.h.
| #define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034)) |
Definition at line 1832 of file cortex-m4-def.h.
| #define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030)) |
Definition at line 1831 of file cortex-m4-def.h.
| #define UDMA_ALTSET_SET_M 0xFFFFFFFF |
Definition at line 8407 of file cortex-m4-def.h.
| #define UDMA_CFG_MASTEN 0x00000001 |
Definition at line 8323 of file cortex-m4-def.h.
| #define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004)) |
Definition at line 1820 of file cortex-m4-def.h.
| #define UDMA_CHASGN_M 0xFFFFFFFF |
Definition at line 8442 of file cortex-m4-def.h.
| #define UDMA_CHASGN_PRIMARY 0x00000000 |
Definition at line 8443 of file cortex-m4-def.h.
| #define UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500)) |
Definition at line 1836 of file cortex-m4-def.h.
| #define UDMA_CHASGN_SECONDARY 0x00000001 |
Definition at line 8445 of file cortex-m4-def.h.
| #define UDMA_CHCTL 0x00000008 |
Definition at line 1852 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_1 0x00000000 |
Definition at line 8583 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 |
Definition at line 8593 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 |
Definition at line 8590 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_16 0x00010000 |
Definition at line 8587 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_2 0x00004000 |
Definition at line 8584 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_256 0x00020000 |
Definition at line 8591 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_32 0x00014000 |
Definition at line 8588 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_4 0x00008000 |
Definition at line 8585 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_512 0x00024000 |
Definition at line 8592 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_64 0x00018000 |
Definition at line 8589 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 |
Definition at line 8586 of file cortex-m4-def.h.
| #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 |
Definition at line 8582 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTINC_16 0x40000000 |
Definition at line 8566 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTINC_32 0x80000000 |
Definition at line 8567 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTINC_8 0x00000000 |
Definition at line 8565 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTINC_M 0xC0000000 |
Definition at line 8564 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 |
Definition at line 8568 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTSIZE_16 0x10000000 |
Definition at line 8571 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTSIZE_32 0x20000000 |
Definition at line 8572 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTSIZE_8 0x00000000 |
Definition at line 8570 of file cortex-m4-def.h.
| #define UDMA_CHCTL_DSTSIZE_M 0x30000000 |
Definition at line 8569 of file cortex-m4-def.h.
| #define UDMA_CHCTL_NXTUSEBURST 0x00000008 |
Definition at line 8595 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCINC_16 0x04000000 |
Definition at line 8575 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCINC_32 0x08000000 |
Definition at line 8576 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCINC_8 0x00000000 |
Definition at line 8574 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCINC_M 0x0C000000 |
Definition at line 8573 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 |
Definition at line 8577 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCSIZE_16 0x01000000 |
Definition at line 8580 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCSIZE_32 0x02000000 |
Definition at line 8581 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCSIZE_8 0x00000000 |
Definition at line 8579 of file cortex-m4-def.h.
| #define UDMA_CHCTL_SRCSIZE_M 0x03000000 |
Definition at line 8578 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 |
Definition at line 8601 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 |
Definition at line 8599 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_M 0x00000007 |
Definition at line 8596 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 |
Definition at line 8605 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 |
Definition at line 8607 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 |
Definition at line 8609 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 |
Definition at line 8611 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 |
Definition at line 8603 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERMODE_STOP 0x00000000 |
Definition at line 8597 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 |
Definition at line 8594 of file cortex-m4-def.h.
| #define UDMA_CHCTL_XFERSIZE_S 4 |
Definition at line 8614 of file cortex-m4-def.h.
| #define UDMA_CHIS_M 0xFFFFFFFF |
Definition at line 8453 of file cortex-m4-def.h.
| #define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504)) |
Definition at line 1837 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH0SEL_M 0x0000000F |
Definition at line 8467 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH0SEL_S 0 |
Definition at line 8475 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH1SEL_M 0x000000F0 |
Definition at line 8466 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH1SEL_S 4 |
Definition at line 8474 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH2SEL_M 0x00000F00 |
Definition at line 8465 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH2SEL_S 8 |
Definition at line 8473 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH3SEL_M 0x0000F000 |
Definition at line 8464 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH3SEL_S 12 |
Definition at line 8472 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH4SEL_M 0x000F0000 |
Definition at line 8463 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH4SEL_S 16 |
Definition at line 8471 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH5SEL_M 0x00F00000 |
Definition at line 8462 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH5SEL_S 20 |
Definition at line 8470 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH6SEL_M 0x0F000000 |
Definition at line 8461 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH6SEL_S 24 |
Definition at line 8469 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH7SEL_M 0xF0000000 |
Definition at line 8460 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_CH7SEL_S 28 |
Definition at line 8468 of file cortex-m4-def.h.
| #define UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510)) |
Definition at line 1838 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH10SEL_M 0x00000F00 |
Definition at line 8487 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH10SEL_S 8 |
Definition at line 8495 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH11SEL_M 0x0000F000 |
Definition at line 8486 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH11SEL_S 12 |
Definition at line 8494 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH12SEL_M 0x000F0000 |
Definition at line 8485 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH12SEL_S 16 |
Definition at line 8493 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH13SEL_M 0x00F00000 |
Definition at line 8484 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH13SEL_S 20 |
Definition at line 8492 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH14SEL_M 0x0F000000 |
Definition at line 8483 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH14SEL_S 24 |
Definition at line 8491 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH15SEL_M 0xF0000000 |
Definition at line 8482 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH15SEL_S 28 |
Definition at line 8490 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH8SEL_M 0x0000000F |
Definition at line 8489 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH8SEL_S 0 |
Definition at line 8497 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH9SEL_M 0x000000F0 |
Definition at line 8488 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_CH9SEL_S 4 |
Definition at line 8496 of file cortex-m4-def.h.
| #define UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514)) |
Definition at line 1839 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH16SEL_M 0x0000000F |
Definition at line 8511 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH16SEL_S 0 |
Definition at line 8519 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH17SEL_M 0x000000F0 |
Definition at line 8510 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH17SEL_S 4 |
Definition at line 8518 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH18SEL_M 0x00000F00 |
Definition at line 8509 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH18SEL_S 8 |
Definition at line 8517 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH19SEL_M 0x0000F000 |
Definition at line 8508 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH19SEL_S 12 |
Definition at line 8516 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH20SEL_M 0x000F0000 |
Definition at line 8507 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH20SEL_S 16 |
Definition at line 8515 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH21SEL_M 0x00F00000 |
Definition at line 8506 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH21SEL_S 20 |
Definition at line 8514 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH22SEL_M 0x0F000000 |
Definition at line 8505 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH22SEL_S 24 |
Definition at line 8513 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH23SEL_M 0xF0000000 |
Definition at line 8504 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_CH23SEL_S 28 |
Definition at line 8512 of file cortex-m4-def.h.
| #define UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518)) |
Definition at line 1840 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH24SEL_M 0x0000000F |
Definition at line 8533 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH24SEL_S 0 |
Definition at line 8541 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH25SEL_M 0x000000F0 |
Definition at line 8532 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH25SEL_S 4 |
Definition at line 8540 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH26SEL_M 0x00000F00 |
Definition at line 8531 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH26SEL_S 8 |
Definition at line 8539 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH27SEL_M 0x0000F000 |
Definition at line 8530 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH27SEL_S 12 |
Definition at line 8538 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH28SEL_M 0x000F0000 |
Definition at line 8529 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH28SEL_S 16 |
Definition at line 8537 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH29SEL_M 0x00F00000 |
Definition at line 8528 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH29SEL_S 20 |
Definition at line 8536 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH30SEL_M 0x0F000000 |
Definition at line 8527 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH30SEL_S 24 |
Definition at line 8535 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH31SEL_M 0xF0000000 |
Definition at line 8526 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_CH31SEL_S 28 |
Definition at line 8534 of file cortex-m4-def.h.
| #define UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C)) |
Definition at line 1841 of file cortex-m4-def.h.
| #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 |
Definition at line 8330 of file cortex-m4-def.h.
| #define UDMA_CTLBASE_ADDR_S 10 |
Definition at line 8331 of file cortex-m4-def.h.
| #define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008)) |
Definition at line 1821 of file cortex-m4-def.h.
| #define UDMA_DSTENDP 0x00000004 |
Definition at line 1850 of file cortex-m4-def.h.
| #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF |
Definition at line 8556 of file cortex-m4-def.h.
| #define UDMA_DSTENDP_ADDR_S 0 |
Definition at line 8557 of file cortex-m4-def.h.
| #define UDMA_ENACLR_CLR_M 0xFFFFFFFF |
Definition at line 8400 of file cortex-m4-def.h.
| #define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C)) |
Definition at line 1830 of file cortex-m4-def.h.
| #define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028)) |
Definition at line 1829 of file cortex-m4-def.h.
| #define UDMA_ENASET_SET_M 0xFFFFFFFF |
Definition at line 8393 of file cortex-m4-def.h.
| #define UDMA_ERRCLR_ERRCLR 0x00000001 |
Definition at line 8435 of file cortex-m4-def.h.
| #define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C)) |
Definition at line 1835 of file cortex-m4-def.h.
| #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF |
Definition at line 8428 of file cortex-m4-def.h.
| #define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C)) |
Definition at line 1834 of file cortex-m4-def.h.
| #define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038)) |
Definition at line 1833 of file cortex-m4-def.h.
| #define UDMA_PRIOSET_SET_M 0xFFFFFFFF |
Definition at line 8421 of file cortex-m4-def.h.
| #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF |
Definition at line 8386 of file cortex-m4-def.h.
| #define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024)) |
Definition at line 1828 of file cortex-m4-def.h.
| #define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020)) |
Definition at line 1827 of file cortex-m4-def.h.
| #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF |
Definition at line 8378 of file cortex-m4-def.h.
| #define UDMA_SRCENDP 0x00000000 |
Definition at line 1848 of file cortex-m4-def.h.
| #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF |
Definition at line 8548 of file cortex-m4-def.h.
| #define UDMA_SRCENDP_ADDR_S 0 |
Definition at line 8549 of file cortex-m4-def.h.
| #define UDMA_STAT_DMACHANS_M 0x001F0000 |
Definition at line 8297 of file cortex-m4-def.h.
| #define UDMA_STAT_DMACHANS_S 16 |
Definition at line 8316 of file cortex-m4-def.h.
| #define UDMA_STAT_MASTEN 0x00000001 |
Definition at line 8315 of file cortex-m4-def.h.
| #define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000)) |
Definition at line 1819 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_DONE 0x00000090 |
Definition at line 8313 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_IDLE 0x00000000 |
Definition at line 8299 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_M 0x000000F0 |
Definition at line 8298 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_RD_CTRL 0x00000010 |
Definition at line 8300 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_RD_DSTENDP 0x00000030 |
Definition at line 8303 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_RD_SRCDAT 0x00000040 |
Definition at line 8305 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_RD_SRCENDP 0x00000020 |
Definition at line 8301 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_STALL 0x00000080 |
Definition at line 8312 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_UNDEF 0x000000A0 |
Definition at line 8314 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_WAIT 0x00000060 |
Definition at line 8309 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_WR_CTRL 0x00000070 |
Definition at line 8311 of file cortex-m4-def.h.
| #define UDMA_STAT_STATE_WR_DSTDAT 0x00000050 |
Definition at line 8307 of file cortex-m4-def.h.
| #define UDMA_SWREQ_M 0xFFFFFFFF |
Definition at line 8354 of file cortex-m4-def.h.
| #define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014)) |
Definition at line 1824 of file cortex-m4-def.h.
| #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF |
Definition at line 8370 of file cortex-m4-def.h.
| #define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C)) |
Definition at line 1826 of file cortex-m4-def.h.
| #define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018)) |
Definition at line 1825 of file cortex-m4-def.h.
| #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF |
Definition at line 8362 of file cortex-m4-def.h.
| #define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010)) |
Definition at line 1823 of file cortex-m4-def.h.
| #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF |
Definition at line 8347 of file cortex-m4-def.h.
| #define USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A)) |
Definition at line 1325 of file cortex-m4-def.h.
| #define USB0_COUNT0_R (*((volatile unsigned char *)0x40050108)) |
Definition at line 1330 of file cortex-m4-def.h.
| #define USB0_CSRH0_R (*((volatile unsigned char *)0x40050103)) |
Definition at line 1329 of file cortex-m4-def.h.
| #define USB0_CSRL0_R (*((volatile unsigned char *)0x40050102)) |
Definition at line 1328 of file cortex-m4-def.h.
| #define USB0_DMASEL_R (*((volatile unsigned long *)0x40050450)) |
Definition at line 1385 of file cortex-m4-def.h.
| #define USB0_DRIM_R (*((volatile unsigned long *)0x40050414)) |
Definition at line 1383 of file cortex-m4-def.h.
| #define USB0_DRISC_R (*((volatile unsigned long *)0x40050418)) |
Definition at line 1384 of file cortex-m4-def.h.
| #define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410)) |
Definition at line 1382 of file cortex-m4-def.h.
| #define USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E)) |
Definition at line 1311 of file cortex-m4-def.h.
| #define USB0_FADDR_R (*((volatile unsigned char *)0x40050000)) |
Definition at line 1302 of file cortex-m4-def.h.
| #define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020)) |
Definition at line 1313 of file cortex-m4-def.h.
| #define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024)) |
Definition at line 1314 of file cortex-m4-def.h.
| #define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028)) |
Definition at line 1315 of file cortex-m4-def.h.
| #define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C)) |
Definition at line 1316 of file cortex-m4-def.h.
| #define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030)) |
Definition at line 1317 of file cortex-m4-def.h.
| #define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034)) |
Definition at line 1318 of file cortex-m4-def.h.
| #define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038)) |
Definition at line 1319 of file cortex-m4-def.h.
| #define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C)) |
Definition at line 1320 of file cortex-m4-def.h.
| #define USB0_FRAME_R (*((volatile unsigned short *)0x4005000C)) |
Definition at line 1310 of file cortex-m4-def.h.
| #define USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D)) |
Definition at line 1326 of file cortex-m4-def.h.
| #define USB0_IE_R (*((volatile unsigned char *)0x4005000B)) |
Definition at line 1309 of file cortex-m4-def.h.
| #define USB0_IS_R (*((volatile unsigned char *)0x4005000A)) |
Definition at line 1308 of file cortex-m4-def.h.
| #define USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E)) |
Definition at line 1327 of file cortex-m4-def.h.
| #define USB0_POWER_R (*((volatile unsigned char *)0x40050001)) |
Definition at line 1303 of file cortex-m4-def.h.
| #define USB0_PP_R (*((volatile unsigned long *)0x40050FC0)) |
Definition at line 1386 of file cortex-m4-def.h.
| #define USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118)) |
Definition at line 1337 of file cortex-m4-def.h.
| #define USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128)) |
Definition at line 1344 of file cortex-m4-def.h.
| #define USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138)) |
Definition at line 1351 of file cortex-m4-def.h.
| #define USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148)) |
Definition at line 1358 of file cortex-m4-def.h.
| #define USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158)) |
Definition at line 1365 of file cortex-m4-def.h.
| #define USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168)) |
Definition at line 1372 of file cortex-m4-def.h.
| #define USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178)) |
Definition at line 1379 of file cortex-m4-def.h.
| #define USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117)) |
Definition at line 1336 of file cortex-m4-def.h.
| #define USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127)) |
Definition at line 1343 of file cortex-m4-def.h.
| #define USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137)) |
Definition at line 1350 of file cortex-m4-def.h.
| #define USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147)) |
Definition at line 1357 of file cortex-m4-def.h.
| #define USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157)) |
Definition at line 1364 of file cortex-m4-def.h.
| #define USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167)) |
Definition at line 1371 of file cortex-m4-def.h.
| #define USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177)) |
Definition at line 1378 of file cortex-m4-def.h.
| #define USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116)) |
Definition at line 1335 of file cortex-m4-def.h.
| #define USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126)) |
Definition at line 1342 of file cortex-m4-def.h.
| #define USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136)) |
Definition at line 1349 of file cortex-m4-def.h.
| #define USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146)) |
Definition at line 1356 of file cortex-m4-def.h.
| #define USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156)) |
Definition at line 1363 of file cortex-m4-def.h.
| #define USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166)) |
Definition at line 1370 of file cortex-m4-def.h.
| #define USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176)) |
Definition at line 1377 of file cortex-m4-def.h.
| #define USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340)) |
Definition at line 1380 of file cortex-m4-def.h.
| #define USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066)) |
Definition at line 1324 of file cortex-m4-def.h.
| #define USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063)) |
Definition at line 1322 of file cortex-m4-def.h.
| #define USB0_RXIE_R (*((volatile unsigned short *)0x40050008)) |
Definition at line 1307 of file cortex-m4-def.h.
| #define USB0_RXIS_R (*((volatile unsigned short *)0x40050004)) |
Definition at line 1305 of file cortex-m4-def.h.
| #define USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114)) |
Definition at line 1334 of file cortex-m4-def.h.
| #define USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124)) |
Definition at line 1341 of file cortex-m4-def.h.
| #define USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134)) |
Definition at line 1348 of file cortex-m4-def.h.
| #define USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144)) |
Definition at line 1355 of file cortex-m4-def.h.
| #define USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154)) |
Definition at line 1362 of file cortex-m4-def.h.
| #define USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164)) |
Definition at line 1369 of file cortex-m4-def.h.
| #define USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174)) |
Definition at line 1376 of file cortex-m4-def.h.
| #define USB0_TEST_R (*((volatile unsigned char *)0x4005000F)) |
Definition at line 1312 of file cortex-m4-def.h.
| #define USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113)) |
Definition at line 1333 of file cortex-m4-def.h.
| #define USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123)) |
Definition at line 1340 of file cortex-m4-def.h.
| #define USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133)) |
Definition at line 1347 of file cortex-m4-def.h.
| #define USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143)) |
Definition at line 1354 of file cortex-m4-def.h.
| #define USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153)) |
Definition at line 1361 of file cortex-m4-def.h.
| #define USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163)) |
Definition at line 1368 of file cortex-m4-def.h.
| #define USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173)) |
Definition at line 1375 of file cortex-m4-def.h.
| #define USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112)) |
Definition at line 1332 of file cortex-m4-def.h.
| #define USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122)) |
Definition at line 1339 of file cortex-m4-def.h.
| #define USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132)) |
Definition at line 1346 of file cortex-m4-def.h.
| #define USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142)) |
Definition at line 1353 of file cortex-m4-def.h.
| #define USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152)) |
Definition at line 1360 of file cortex-m4-def.h.
| #define USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162)) |
Definition at line 1367 of file cortex-m4-def.h.
| #define USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172)) |
Definition at line 1374 of file cortex-m4-def.h.
| #define USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342)) |
Definition at line 1381 of file cortex-m4-def.h.
| #define USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064)) |
Definition at line 1323 of file cortex-m4-def.h.
| #define USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062)) |
Definition at line 1321 of file cortex-m4-def.h.
| #define USB0_TXIE_R (*((volatile unsigned short *)0x40050006)) |
Definition at line 1306 of file cortex-m4-def.h.
| #define USB0_TXIS_R (*((volatile unsigned short *)0x40050002)) |
Definition at line 1304 of file cortex-m4-def.h.
| #define USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110)) |
Definition at line 1331 of file cortex-m4-def.h.
| #define USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120)) |
Definition at line 1338 of file cortex-m4-def.h.
| #define USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130)) |
Definition at line 1345 of file cortex-m4-def.h.
| #define USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140)) |
Definition at line 1352 of file cortex-m4-def.h.
| #define USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150)) |
Definition at line 1359 of file cortex-m4-def.h.
| #define USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160)) |
Definition at line 1366 of file cortex-m4-def.h.
| #define USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170)) |
Definition at line 1373 of file cortex-m4-def.h.
| #define USB_CONTIM_WTCON_M 0x000000F0 |
Definition at line 4973 of file cortex-m4-def.h.
| #define USB_CONTIM_WTCON_S 4 |
Definition at line 4975 of file cortex-m4-def.h.
| #define USB_CONTIM_WTID_M 0x0000000F |
Definition at line 4974 of file cortex-m4-def.h.
| #define USB_CONTIM_WTID_S 0 |
Definition at line 4976 of file cortex-m4-def.h.
| #define USB_COUNT0_COUNT_M 0x0000007F |
Definition at line 5020 of file cortex-m4-def.h.
| #define USB_COUNT0_COUNT_S 0 |
Definition at line 5021 of file cortex-m4-def.h.
| #define USB_CSRH0_FLUSH 0x00000001 |
Definition at line 5013 of file cortex-m4-def.h.
| #define USB_CSRL0_DATAEND 0x00000008 |
Definition at line 5003 of file cortex-m4-def.h.
| #define USB_CSRL0_RXRDY 0x00000001 |
Definition at line 5006 of file cortex-m4-def.h.
| #define USB_CSRL0_RXRDYC 0x00000040 |
Definition at line 5000 of file cortex-m4-def.h.
| #define USB_CSRL0_SETEND 0x00000010 |
Definition at line 5002 of file cortex-m4-def.h.
| #define USB_CSRL0_SETENDC 0x00000080 |
Definition at line 4999 of file cortex-m4-def.h.
| #define USB_CSRL0_STALL 0x00000020 |
Definition at line 5001 of file cortex-m4-def.h.
| #define USB_CSRL0_STALLED 0x00000004 |
Definition at line 5004 of file cortex-m4-def.h.
| #define USB_CSRL0_TXRDY 0x00000002 |
Definition at line 5005 of file cortex-m4-def.h.
| #define USB_DMASEL_DMAARX_M 0x0000000F |
Definition at line 5622 of file cortex-m4-def.h.
| #define USB_DMASEL_DMAARX_S 0 |
Definition at line 5628 of file cortex-m4-def.h.
| #define USB_DMASEL_DMAATX_M 0x000000F0 |
Definition at line 5621 of file cortex-m4-def.h.
| #define USB_DMASEL_DMAATX_S 4 |
Definition at line 5627 of file cortex-m4-def.h.
| #define USB_DMASEL_DMABRX_M 0x00000F00 |
Definition at line 5620 of file cortex-m4-def.h.
| #define USB_DMASEL_DMABRX_S 8 |
Definition at line 5626 of file cortex-m4-def.h.
| #define USB_DMASEL_DMABTX_M 0x0000F000 |
Definition at line 5619 of file cortex-m4-def.h.
| #define USB_DMASEL_DMABTX_S 12 |
Definition at line 5625 of file cortex-m4-def.h.
| #define USB_DMASEL_DMACRX_M 0x000F0000 |
Definition at line 5618 of file cortex-m4-def.h.
| #define USB_DMASEL_DMACRX_S 16 |
Definition at line 5624 of file cortex-m4-def.h.
| #define USB_DMASEL_DMACTX_M 0x00F00000 |
Definition at line 5617 of file cortex-m4-def.h.
| #define USB_DMASEL_DMACTX_S 20 |
Definition at line 5623 of file cortex-m4-def.h.
| #define USB_DRIM_RESUME 0x00000001 |
Definition at line 5602 of file cortex-m4-def.h.
| #define USB_DRISC_RESUME 0x00000001 |
Definition at line 5609 of file cortex-m4-def.h.
| #define USB_DRRIS_RESUME 0x00000001 |
Definition at line 5595 of file cortex-m4-def.h.
| #define USB_EPIDX_EPIDX_M 0x0000000F |
Definition at line 4841 of file cortex-m4-def.h.
| #define USB_EPIDX_EPIDX_S 0 |
Definition at line 4842 of file cortex-m4-def.h.
| #define USB_FADDR_M 0x0000007F |
Definition at line 4736 of file cortex-m4-def.h.
| #define USB_FADDR_S 0 |
Definition at line 4737 of file cortex-m4-def.h.
| #define USB_FIFO0_EPDATA_M 0xFFFFFFFF |
Definition at line 4857 of file cortex-m4-def.h.
| #define USB_FIFO0_EPDATA_S 0 |
Definition at line 4858 of file cortex-m4-def.h.
| #define USB_FIFO1_EPDATA_M 0xFFFFFFFF |
Definition at line 4865 of file cortex-m4-def.h.
| #define USB_FIFO1_EPDATA_S 0 |
Definition at line 4866 of file cortex-m4-def.h.
| #define USB_FIFO2_EPDATA_M 0xFFFFFFFF |
Definition at line 4873 of file cortex-m4-def.h.
| #define USB_FIFO2_EPDATA_S 0 |
Definition at line 4874 of file cortex-m4-def.h.
| #define USB_FIFO3_EPDATA_M 0xFFFFFFFF |
Definition at line 4881 of file cortex-m4-def.h.
| #define USB_FIFO3_EPDATA_S 0 |
Definition at line 4882 of file cortex-m4-def.h.
| #define USB_FIFO4_EPDATA_M 0xFFFFFFFF |
Definition at line 4889 of file cortex-m4-def.h.
| #define USB_FIFO4_EPDATA_S 0 |
Definition at line 4890 of file cortex-m4-def.h.
| #define USB_FIFO5_EPDATA_M 0xFFFFFFFF |
Definition at line 4897 of file cortex-m4-def.h.
| #define USB_FIFO5_EPDATA_S 0 |
Definition at line 4898 of file cortex-m4-def.h.
| #define USB_FIFO6_EPDATA_M 0xFFFFFFFF |
Definition at line 4905 of file cortex-m4-def.h.
| #define USB_FIFO6_EPDATA_S 0 |
Definition at line 4906 of file cortex-m4-def.h.
| #define USB_FIFO7_EPDATA_M 0xFFFFFFFF |
Definition at line 4913 of file cortex-m4-def.h.
| #define USB_FIFO7_EPDATA_S 0 |
Definition at line 4914 of file cortex-m4-def.h.
| #define USB_FRAME_M 0x000007FF |
Definition at line 4833 of file cortex-m4-def.h.
| #define USB_FRAME_S 0 |
Definition at line 4834 of file cortex-m4-def.h.
| #define USB_FSEOF_FSEOFG_M 0x000000FF |
Definition at line 4983 of file cortex-m4-def.h.
| #define USB_FSEOF_FSEOFG_S 0 |
Definition at line 4984 of file cortex-m4-def.h.
| #define USB_IE_DISCON 0x00000020 |
Definition at line 4822 of file cortex-m4-def.h.
| #define USB_IE_RESET 0x00000004 |
Definition at line 4824 of file cortex-m4-def.h.
| #define USB_IE_RESUME 0x00000002 |
Definition at line 4825 of file cortex-m4-def.h.
| #define USB_IE_SOF 0x00000008 |
Definition at line 4823 of file cortex-m4-def.h.
| #define USB_IE_SUSPND 0x00000001 |
Definition at line 4826 of file cortex-m4-def.h.
| #define USB_IS_DISCON 0x00000020 |
Definition at line 4811 of file cortex-m4-def.h.
| #define USB_IS_RESET 0x00000004 |
Definition at line 4813 of file cortex-m4-def.h.
| #define USB_IS_RESUME 0x00000002 |
Definition at line 4814 of file cortex-m4-def.h.
| #define USB_IS_SOF 0x00000008 |
Definition at line 4812 of file cortex-m4-def.h.
| #define USB_IS_SUSPEND 0x00000001 |
Definition at line 4815 of file cortex-m4-def.h.
| #define USB_LSEOF_LSEOFG_M 0x000000FF |
Definition at line 4991 of file cortex-m4-def.h.
| #define USB_LSEOF_LSEOFG_S 0 |
Definition at line 4992 of file cortex-m4-def.h.
| #define USB_POWER_ISOUP 0x00000080 |
Definition at line 4744 of file cortex-m4-def.h.
| #define USB_POWER_PWRDNPHY 0x00000001 |
Definition at line 4749 of file cortex-m4-def.h.
| #define USB_POWER_RESET 0x00000008 |
Definition at line 4746 of file cortex-m4-def.h.
| #define USB_POWER_RESUME 0x00000004 |
Definition at line 4747 of file cortex-m4-def.h.
| #define USB_POWER_SOFTCONN 0x00000040 |
Definition at line 4745 of file cortex-m4-def.h.
| #define USB_POWER_SUSPEND 0x00000002 |
Definition at line 4748 of file cortex-m4-def.h.
| #define USB_PP_ECNT_M 0x0000FF00 |
Definition at line 5635 of file cortex-m4-def.h.
| #define USB_PP_ECNT_S 8 |
Definition at line 5644 of file cortex-m4-def.h.
| #define USB_PP_PHY 0x00000010 |
Definition at line 5640 of file cortex-m4-def.h.
| #define USB_PP_TYPE_0 0x00000000 |
Definition at line 5642 of file cortex-m4-def.h.
| #define USB_PP_TYPE_M 0x0000000F |
Definition at line 5641 of file cortex-m4-def.h.
| #define USB_PP_USB_DEVICE 0x00000040 |
Definition at line 5637 of file cortex-m4-def.h.
| #define USB_PP_USB_HOSTDEVICE 0x00000080 |
Definition at line 5638 of file cortex-m4-def.h.
| #define USB_PP_USB_M 0x000000C0 |
Definition at line 5636 of file cortex-m4-def.h.
| #define USB_PP_USB_OTG 0x000000C0 |
Definition at line 5639 of file cortex-m4-def.h.
| #define USB_RXCOUNT1_COUNT_M 0x00001FFF |
Definition at line 5095 of file cortex-m4-def.h.
| #define USB_RXCOUNT1_COUNT_S 0 |
Definition at line 5096 of file cortex-m4-def.h.
| #define USB_RXCOUNT2_COUNT_M 0x00001FFF |
Definition at line 5170 of file cortex-m4-def.h.
| #define USB_RXCOUNT2_COUNT_S 0 |
Definition at line 5171 of file cortex-m4-def.h.
| #define USB_RXCOUNT3_COUNT_M 0x00001FFF |
Definition at line 5245 of file cortex-m4-def.h.
| #define USB_RXCOUNT3_COUNT_S 0 |
Definition at line 5246 of file cortex-m4-def.h.
| #define USB_RXCOUNT4_COUNT_M 0x00001FFF |
Definition at line 5320 of file cortex-m4-def.h.
| #define USB_RXCOUNT4_COUNT_S 0 |
Definition at line 5321 of file cortex-m4-def.h.
| #define USB_RXCOUNT5_COUNT_M 0x00001FFF |
Definition at line 5395 of file cortex-m4-def.h.
| #define USB_RXCOUNT5_COUNT_S 0 |
Definition at line 5396 of file cortex-m4-def.h.
| #define USB_RXCOUNT6_COUNT_M 0x00001FFF |
Definition at line 5470 of file cortex-m4-def.h.
| #define USB_RXCOUNT6_COUNT_S 0 |
Definition at line 5471 of file cortex-m4-def.h.
| #define USB_RXCOUNT7_COUNT_M 0x00001FFF |
Definition at line 5545 of file cortex-m4-def.h.
| #define USB_RXCOUNT7_COUNT_S 0 |
Definition at line 5546 of file cortex-m4-def.h.
| #define USB_RXCSRH1_AUTOCL 0x00000080 |
Definition at line 5083 of file cortex-m4-def.h.
| #define USB_RXCSRH1_DISNYET 0x00000010 |
Definition at line 5086 of file cortex-m4-def.h.
| #define USB_RXCSRH1_DMAEN 0x00000020 |
Definition at line 5085 of file cortex-m4-def.h.
| #define USB_RXCSRH1_DMAMOD 0x00000008 |
Definition at line 5088 of file cortex-m4-def.h.
| #define USB_RXCSRH1_ISO 0x00000040 |
Definition at line 5084 of file cortex-m4-def.h.
| #define USB_RXCSRH1_PIDERR 0x00000010 |
Definition at line 5087 of file cortex-m4-def.h.
| #define USB_RXCSRH2_AUTOCL 0x00000080 |
Definition at line 5158 of file cortex-m4-def.h.
| #define USB_RXCSRH2_DISNYET 0x00000010 |
Definition at line 5161 of file cortex-m4-def.h.
| #define USB_RXCSRH2_DMAEN 0x00000020 |
Definition at line 5160 of file cortex-m4-def.h.
| #define USB_RXCSRH2_DMAMOD 0x00000008 |
Definition at line 5163 of file cortex-m4-def.h.
| #define USB_RXCSRH2_ISO 0x00000040 |
Definition at line 5159 of file cortex-m4-def.h.
| #define USB_RXCSRH2_PIDERR 0x00000010 |
Definition at line 5162 of file cortex-m4-def.h.
| #define USB_RXCSRH3_AUTOCL 0x00000080 |
Definition at line 5233 of file cortex-m4-def.h.
| #define USB_RXCSRH3_DISNYET 0x00000010 |
Definition at line 5236 of file cortex-m4-def.h.
| #define USB_RXCSRH3_DMAEN 0x00000020 |
Definition at line 5235 of file cortex-m4-def.h.
| #define USB_RXCSRH3_DMAMOD 0x00000008 |
Definition at line 5238 of file cortex-m4-def.h.
| #define USB_RXCSRH3_ISO 0x00000040 |
Definition at line 5234 of file cortex-m4-def.h.
| #define USB_RXCSRH3_PIDERR 0x00000010 |
Definition at line 5237 of file cortex-m4-def.h.
| #define USB_RXCSRH4_AUTOCL 0x00000080 |
Definition at line 5308 of file cortex-m4-def.h.
| #define USB_RXCSRH4_DISNYET 0x00000010 |
Definition at line 5311 of file cortex-m4-def.h.
| #define USB_RXCSRH4_DMAEN 0x00000020 |
Definition at line 5310 of file cortex-m4-def.h.
| #define USB_RXCSRH4_DMAMOD 0x00000008 |
Definition at line 5313 of file cortex-m4-def.h.
| #define USB_RXCSRH4_ISO 0x00000040 |
Definition at line 5309 of file cortex-m4-def.h.
| #define USB_RXCSRH4_PIDERR 0x00000010 |
Definition at line 5312 of file cortex-m4-def.h.
| #define USB_RXCSRH5_AUTOCL 0x00000080 |
Definition at line 5383 of file cortex-m4-def.h.
| #define USB_RXCSRH5_DISNYET 0x00000010 |
Definition at line 5386 of file cortex-m4-def.h.
| #define USB_RXCSRH5_DMAEN 0x00000020 |
Definition at line 5385 of file cortex-m4-def.h.
| #define USB_RXCSRH5_DMAMOD 0x00000008 |
Definition at line 5388 of file cortex-m4-def.h.
| #define USB_RXCSRH5_ISO 0x00000040 |
Definition at line 5384 of file cortex-m4-def.h.
| #define USB_RXCSRH5_PIDERR 0x00000010 |
Definition at line 5387 of file cortex-m4-def.h.
| #define USB_RXCSRH6_AUTOCL 0x00000080 |
Definition at line 5458 of file cortex-m4-def.h.
| #define USB_RXCSRH6_DISNYET 0x00000010 |
Definition at line 5461 of file cortex-m4-def.h.
| #define USB_RXCSRH6_DMAEN 0x00000020 |
Definition at line 5460 of file cortex-m4-def.h.
| #define USB_RXCSRH6_DMAMOD 0x00000008 |
Definition at line 5463 of file cortex-m4-def.h.
| #define USB_RXCSRH6_ISO 0x00000040 |
Definition at line 5459 of file cortex-m4-def.h.
| #define USB_RXCSRH6_PIDERR 0x00000010 |
Definition at line 5462 of file cortex-m4-def.h.
| #define USB_RXCSRH7_AUTOCL 0x00000080 |
Definition at line 5533 of file cortex-m4-def.h.
| #define USB_RXCSRH7_DISNYET 0x00000010 |
Definition at line 5537 of file cortex-m4-def.h.
| #define USB_RXCSRH7_DMAEN 0x00000020 |
Definition at line 5535 of file cortex-m4-def.h.
| #define USB_RXCSRH7_DMAMOD 0x00000008 |
Definition at line 5538 of file cortex-m4-def.h.
| #define USB_RXCSRH7_ISO 0x00000040 |
Definition at line 5534 of file cortex-m4-def.h.
| #define USB_RXCSRH7_PIDERR 0x00000010 |
Definition at line 5536 of file cortex-m4-def.h.
| #define USB_RXCSRL1_CLRDT 0x00000080 |
Definition at line 5069 of file cortex-m4-def.h.
| #define USB_RXCSRL1_DATAERR 0x00000008 |
Definition at line 5073 of file cortex-m4-def.h.
| #define USB_RXCSRL1_FLUSH 0x00000010 |
Definition at line 5072 of file cortex-m4-def.h.
| #define USB_RXCSRL1_FULL 0x00000002 |
Definition at line 5075 of file cortex-m4-def.h.
| #define USB_RXCSRL1_OVER 0x00000004 |
Definition at line 5074 of file cortex-m4-def.h.
| #define USB_RXCSRL1_RXRDY 0x00000001 |
Definition at line 5076 of file cortex-m4-def.h.
| #define USB_RXCSRL1_STALL 0x00000020 |
Definition at line 5071 of file cortex-m4-def.h.
| #define USB_RXCSRL1_STALLED 0x00000040 |
Definition at line 5070 of file cortex-m4-def.h.
| #define USB_RXCSRL2_CLRDT 0x00000080 |
Definition at line 5144 of file cortex-m4-def.h.
| #define USB_RXCSRL2_DATAERR 0x00000008 |
Definition at line 5148 of file cortex-m4-def.h.
| #define USB_RXCSRL2_FLUSH 0x00000010 |
Definition at line 5147 of file cortex-m4-def.h.
| #define USB_RXCSRL2_FULL 0x00000002 |
Definition at line 5150 of file cortex-m4-def.h.
| #define USB_RXCSRL2_OVER 0x00000004 |
Definition at line 5149 of file cortex-m4-def.h.
| #define USB_RXCSRL2_RXRDY 0x00000001 |
Definition at line 5151 of file cortex-m4-def.h.
| #define USB_RXCSRL2_STALL 0x00000020 |
Definition at line 5146 of file cortex-m4-def.h.
| #define USB_RXCSRL2_STALLED 0x00000040 |
Definition at line 5145 of file cortex-m4-def.h.
| #define USB_RXCSRL3_CLRDT 0x00000080 |
Definition at line 5219 of file cortex-m4-def.h.
| #define USB_RXCSRL3_DATAERR 0x00000008 |
Definition at line 5223 of file cortex-m4-def.h.
| #define USB_RXCSRL3_FLUSH 0x00000010 |
Definition at line 5222 of file cortex-m4-def.h.
| #define USB_RXCSRL3_FULL 0x00000002 |
Definition at line 5225 of file cortex-m4-def.h.
| #define USB_RXCSRL3_OVER 0x00000004 |
Definition at line 5224 of file cortex-m4-def.h.
| #define USB_RXCSRL3_RXRDY 0x00000001 |
Definition at line 5226 of file cortex-m4-def.h.
| #define USB_RXCSRL3_STALL 0x00000020 |
Definition at line 5221 of file cortex-m4-def.h.
| #define USB_RXCSRL3_STALLED 0x00000040 |
Definition at line 5220 of file cortex-m4-def.h.
| #define USB_RXCSRL4_CLRDT 0x00000080 |
Definition at line 5294 of file cortex-m4-def.h.
| #define USB_RXCSRL4_DATAERR 0x00000008 |
Definition at line 5298 of file cortex-m4-def.h.
| #define USB_RXCSRL4_FLUSH 0x00000010 |
Definition at line 5297 of file cortex-m4-def.h.
| #define USB_RXCSRL4_FULL 0x00000002 |
Definition at line 5300 of file cortex-m4-def.h.
| #define USB_RXCSRL4_OVER 0x00000004 |
Definition at line 5299 of file cortex-m4-def.h.
| #define USB_RXCSRL4_RXRDY 0x00000001 |
Definition at line 5301 of file cortex-m4-def.h.
| #define USB_RXCSRL4_STALL 0x00000020 |
Definition at line 5296 of file cortex-m4-def.h.
| #define USB_RXCSRL4_STALLED 0x00000040 |
Definition at line 5295 of file cortex-m4-def.h.
| #define USB_RXCSRL5_CLRDT 0x00000080 |
Definition at line 5369 of file cortex-m4-def.h.
| #define USB_RXCSRL5_DATAERR 0x00000008 |
Definition at line 5373 of file cortex-m4-def.h.
| #define USB_RXCSRL5_FLUSH 0x00000010 |
Definition at line 5372 of file cortex-m4-def.h.
| #define USB_RXCSRL5_FULL 0x00000002 |
Definition at line 5375 of file cortex-m4-def.h.
| #define USB_RXCSRL5_OVER 0x00000004 |
Definition at line 5374 of file cortex-m4-def.h.
| #define USB_RXCSRL5_RXRDY 0x00000001 |
Definition at line 5376 of file cortex-m4-def.h.
| #define USB_RXCSRL5_STALL 0x00000020 |
Definition at line 5371 of file cortex-m4-def.h.
| #define USB_RXCSRL5_STALLED 0x00000040 |
Definition at line 5370 of file cortex-m4-def.h.
| #define USB_RXCSRL6_CLRDT 0x00000080 |
Definition at line 5444 of file cortex-m4-def.h.
| #define USB_RXCSRL6_DATAERR 0x00000008 |
Definition at line 5448 of file cortex-m4-def.h.
| #define USB_RXCSRL6_FLUSH 0x00000010 |
Definition at line 5447 of file cortex-m4-def.h.
| #define USB_RXCSRL6_FULL 0x00000002 |
Definition at line 5450 of file cortex-m4-def.h.
| #define USB_RXCSRL6_OVER 0x00000004 |
Definition at line 5449 of file cortex-m4-def.h.
| #define USB_RXCSRL6_RXRDY 0x00000001 |
Definition at line 5451 of file cortex-m4-def.h.
| #define USB_RXCSRL6_STALL 0x00000020 |
Definition at line 5446 of file cortex-m4-def.h.
| #define USB_RXCSRL6_STALLED 0x00000040 |
Definition at line 5445 of file cortex-m4-def.h.
| #define USB_RXCSRL7_CLRDT 0x00000080 |
Definition at line 5519 of file cortex-m4-def.h.
| #define USB_RXCSRL7_DATAERR 0x00000008 |
Definition at line 5523 of file cortex-m4-def.h.
| #define USB_RXCSRL7_FLUSH 0x00000010 |
Definition at line 5522 of file cortex-m4-def.h.
| #define USB_RXCSRL7_FULL 0x00000002 |
Definition at line 5525 of file cortex-m4-def.h.
| #define USB_RXCSRL7_OVER 0x00000004 |
Definition at line 5524 of file cortex-m4-def.h.
| #define USB_RXCSRL7_RXRDY 0x00000001 |
Definition at line 5526 of file cortex-m4-def.h.
| #define USB_RXCSRL7_STALL 0x00000020 |
Definition at line 5521 of file cortex-m4-def.h.
| #define USB_RXCSRL7_STALLED 0x00000040 |
Definition at line 5520 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP1 0x00000002 |
Definition at line 5566 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP2 0x00000004 |
Definition at line 5564 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP3 0x00000008 |
Definition at line 5562 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP4 0x00000010 |
Definition at line 5560 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP5 0x00000020 |
Definition at line 5558 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP6 0x00000040 |
Definition at line 5556 of file cortex-m4-def.h.
| #define USB_RXDPKTBUFDIS_EP7 0x00000080 |
Definition at line 5554 of file cortex-m4-def.h.
| #define USB_RXFIFOADD_ADDR_M 0x000001FF |
Definition at line 4965 of file cortex-m4-def.h.
| #define USB_RXFIFOADD_ADDR_S 0 |
Definition at line 4966 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_DPB 0x00000010 |
Definition at line 4938 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_1024 0x00000007 |
Definition at line 4947 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_128 0x00000004 |
Definition at line 4944 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_16 0x00000001 |
Definition at line 4941 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_2048 0x00000008 |
Definition at line 4948 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_256 0x00000005 |
Definition at line 4945 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_32 0x00000002 |
Definition at line 4942 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_512 0x00000006 |
Definition at line 4946 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_64 0x00000003 |
Definition at line 4943 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_8 0x00000000 |
Definition at line 4940 of file cortex-m4-def.h.
| #define USB_RXFIFOSZ_SIZE_M 0x0000000F |
Definition at line 4939 of file cortex-m4-def.h.
| #define USB_RXIE_EP1 0x00000002 |
Definition at line 4804 of file cortex-m4-def.h.
| #define USB_RXIE_EP2 0x00000004 |
Definition at line 4803 of file cortex-m4-def.h.
| #define USB_RXIE_EP3 0x00000008 |
Definition at line 4802 of file cortex-m4-def.h.
| #define USB_RXIE_EP4 0x00000010 |
Definition at line 4801 of file cortex-m4-def.h.
| #define USB_RXIE_EP5 0x00000020 |
Definition at line 4800 of file cortex-m4-def.h.
| #define USB_RXIE_EP6 0x00000040 |
Definition at line 4799 of file cortex-m4-def.h.
| #define USB_RXIE_EP7 0x00000080 |
Definition at line 4798 of file cortex-m4-def.h.
| #define USB_RXIS_EP1 0x00000002 |
Definition at line 4776 of file cortex-m4-def.h.
| #define USB_RXIS_EP2 0x00000004 |
Definition at line 4775 of file cortex-m4-def.h.
| #define USB_RXIS_EP3 0x00000008 |
Definition at line 4774 of file cortex-m4-def.h.
| #define USB_RXIS_EP4 0x00000010 |
Definition at line 4773 of file cortex-m4-def.h.
| #define USB_RXIS_EP5 0x00000020 |
Definition at line 4772 of file cortex-m4-def.h.
| #define USB_RXIS_EP6 0x00000040 |
Definition at line 4771 of file cortex-m4-def.h.
| #define USB_RXIS_EP7 0x00000080 |
Definition at line 4770 of file cortex-m4-def.h.
| #define USB_RXMAXP1_MAXLOAD_M 0x000007FF |
Definition at line 5061 of file cortex-m4-def.h.
| #define USB_RXMAXP1_MAXLOAD_S 0 |
Definition at line 5062 of file cortex-m4-def.h.
| #define USB_RXMAXP2_MAXLOAD_M 0x000007FF |
Definition at line 5136 of file cortex-m4-def.h.
| #define USB_RXMAXP2_MAXLOAD_S 0 |
Definition at line 5137 of file cortex-m4-def.h.
| #define USB_RXMAXP3_MAXLOAD_M 0x000007FF |
Definition at line 5211 of file cortex-m4-def.h.
| #define USB_RXMAXP3_MAXLOAD_S 0 |
Definition at line 5212 of file cortex-m4-def.h.
| #define USB_RXMAXP4_MAXLOAD_M 0x000007FF |
Definition at line 5286 of file cortex-m4-def.h.
| #define USB_RXMAXP4_MAXLOAD_S 0 |
Definition at line 5287 of file cortex-m4-def.h.
| #define USB_RXMAXP5_MAXLOAD_M 0x000007FF |
Definition at line 5361 of file cortex-m4-def.h.
| #define USB_RXMAXP5_MAXLOAD_S 0 |
Definition at line 5362 of file cortex-m4-def.h.
| #define USB_RXMAXP6_MAXLOAD_M 0x000007FF |
Definition at line 5436 of file cortex-m4-def.h.
| #define USB_RXMAXP6_MAXLOAD_S 0 |
Definition at line 5437 of file cortex-m4-def.h.
| #define USB_RXMAXP7_MAXLOAD_M 0x000007FF |
Definition at line 5511 of file cortex-m4-def.h.
| #define USB_RXMAXP7_MAXLOAD_S 0 |
Definition at line 5512 of file cortex-m4-def.h.
| #define USB_TEST_FIFOACC 0x00000040 |
Definition at line 4849 of file cortex-m4-def.h.
| #define USB_TEST_FORCEFS 0x00000020 |
Definition at line 4850 of file cortex-m4-def.h.
| #define USB_TXCSRH1_AUTOSET 0x00000080 |
Definition at line 5049 of file cortex-m4-def.h.
| #define USB_TXCSRH1_DMAEN 0x00000010 |
Definition at line 5052 of file cortex-m4-def.h.
| #define USB_TXCSRH1_DMAMOD 0x00000004 |
Definition at line 5054 of file cortex-m4-def.h.
| #define USB_TXCSRH1_FDT 0x00000008 |
Definition at line 5053 of file cortex-m4-def.h.
| #define USB_TXCSRH1_ISO 0x00000040 |
Definition at line 5050 of file cortex-m4-def.h.
| #define USB_TXCSRH1_MODE 0x00000020 |
Definition at line 5051 of file cortex-m4-def.h.
| #define USB_TXCSRH2_AUTOSET 0x00000080 |
Definition at line 5124 of file cortex-m4-def.h.
| #define USB_TXCSRH2_DMAEN 0x00000010 |
Definition at line 5127 of file cortex-m4-def.h.
| #define USB_TXCSRH2_DMAMOD 0x00000004 |
Definition at line 5129 of file cortex-m4-def.h.
| #define USB_TXCSRH2_FDT 0x00000008 |
Definition at line 5128 of file cortex-m4-def.h.
| #define USB_TXCSRH2_ISO 0x00000040 |
Definition at line 5125 of file cortex-m4-def.h.
| #define USB_TXCSRH2_MODE 0x00000020 |
Definition at line 5126 of file cortex-m4-def.h.
| #define USB_TXCSRH3_AUTOSET 0x00000080 |
Definition at line 5199 of file cortex-m4-def.h.
| #define USB_TXCSRH3_DMAEN 0x00000010 |
Definition at line 5202 of file cortex-m4-def.h.
| #define USB_TXCSRH3_DMAMOD 0x00000004 |
Definition at line 5204 of file cortex-m4-def.h.
| #define USB_TXCSRH3_FDT 0x00000008 |
Definition at line 5203 of file cortex-m4-def.h.
| #define USB_TXCSRH3_ISO 0x00000040 |
Definition at line 5200 of file cortex-m4-def.h.
| #define USB_TXCSRH3_MODE 0x00000020 |
Definition at line 5201 of file cortex-m4-def.h.
| #define USB_TXCSRH4_AUTOSET 0x00000080 |
Definition at line 5274 of file cortex-m4-def.h.
| #define USB_TXCSRH4_DMAEN 0x00000010 |
Definition at line 5277 of file cortex-m4-def.h.
| #define USB_TXCSRH4_DMAMOD 0x00000004 |
Definition at line 5279 of file cortex-m4-def.h.
| #define USB_TXCSRH4_FDT 0x00000008 |
Definition at line 5278 of file cortex-m4-def.h.
| #define USB_TXCSRH4_ISO 0x00000040 |
Definition at line 5275 of file cortex-m4-def.h.
| #define USB_TXCSRH4_MODE 0x00000020 |
Definition at line 5276 of file cortex-m4-def.h.
| #define USB_TXCSRH5_AUTOSET 0x00000080 |
Definition at line 5349 of file cortex-m4-def.h.
| #define USB_TXCSRH5_DMAEN 0x00000010 |
Definition at line 5352 of file cortex-m4-def.h.
| #define USB_TXCSRH5_DMAMOD 0x00000004 |
Definition at line 5354 of file cortex-m4-def.h.
| #define USB_TXCSRH5_FDT 0x00000008 |
Definition at line 5353 of file cortex-m4-def.h.
| #define USB_TXCSRH5_ISO 0x00000040 |
Definition at line 5350 of file cortex-m4-def.h.
| #define USB_TXCSRH5_MODE 0x00000020 |
Definition at line 5351 of file cortex-m4-def.h.
| #define USB_TXCSRH6_AUTOSET 0x00000080 |
Definition at line 5424 of file cortex-m4-def.h.
| #define USB_TXCSRH6_DMAEN 0x00000010 |
Definition at line 5427 of file cortex-m4-def.h.
| #define USB_TXCSRH6_DMAMOD 0x00000004 |
Definition at line 5429 of file cortex-m4-def.h.
| #define USB_TXCSRH6_FDT 0x00000008 |
Definition at line 5428 of file cortex-m4-def.h.
| #define USB_TXCSRH6_ISO 0x00000040 |
Definition at line 5425 of file cortex-m4-def.h.
| #define USB_TXCSRH6_MODE 0x00000020 |
Definition at line 5426 of file cortex-m4-def.h.
| #define USB_TXCSRH7_AUTOSET 0x00000080 |
Definition at line 5499 of file cortex-m4-def.h.
| #define USB_TXCSRH7_DMAEN 0x00000010 |
Definition at line 5502 of file cortex-m4-def.h.
| #define USB_TXCSRH7_DMAMOD 0x00000004 |
Definition at line 5504 of file cortex-m4-def.h.
| #define USB_TXCSRH7_FDT 0x00000008 |
Definition at line 5503 of file cortex-m4-def.h.
| #define USB_TXCSRH7_ISO 0x00000040 |
Definition at line 5500 of file cortex-m4-def.h.
| #define USB_TXCSRH7_MODE 0x00000020 |
Definition at line 5501 of file cortex-m4-def.h.
| #define USB_TXCSRL1_CLRDT 0x00000040 |
Definition at line 5036 of file cortex-m4-def.h.
| #define USB_TXCSRL1_FIFONE 0x00000002 |
Definition at line 5041 of file cortex-m4-def.h.
| #define USB_TXCSRL1_FLUSH 0x00000008 |
Definition at line 5039 of file cortex-m4-def.h.
| #define USB_TXCSRL1_STALL 0x00000010 |
Definition at line 5038 of file cortex-m4-def.h.
| #define USB_TXCSRL1_STALLED 0x00000020 |
Definition at line 5037 of file cortex-m4-def.h.
| #define USB_TXCSRL1_TXRDY 0x00000001 |
Definition at line 5042 of file cortex-m4-def.h.
| #define USB_TXCSRL1_UNDRN 0x00000004 |
Definition at line 5040 of file cortex-m4-def.h.
| #define USB_TXCSRL2_CLRDT 0x00000040 |
Definition at line 5111 of file cortex-m4-def.h.
| #define USB_TXCSRL2_FIFONE 0x00000002 |
Definition at line 5116 of file cortex-m4-def.h.
| #define USB_TXCSRL2_FLUSH 0x00000008 |
Definition at line 5114 of file cortex-m4-def.h.
| #define USB_TXCSRL2_STALL 0x00000010 |
Definition at line 5113 of file cortex-m4-def.h.
| #define USB_TXCSRL2_STALLED 0x00000020 |
Definition at line 5112 of file cortex-m4-def.h.
| #define USB_TXCSRL2_TXRDY 0x00000001 |
Definition at line 5117 of file cortex-m4-def.h.
| #define USB_TXCSRL2_UNDRN 0x00000004 |
Definition at line 5115 of file cortex-m4-def.h.
| #define USB_TXCSRL3_CLRDT 0x00000040 |
Definition at line 5186 of file cortex-m4-def.h.
| #define USB_TXCSRL3_FIFONE 0x00000002 |
Definition at line 5191 of file cortex-m4-def.h.
| #define USB_TXCSRL3_FLUSH 0x00000008 |
Definition at line 5189 of file cortex-m4-def.h.
| #define USB_TXCSRL3_STALL 0x00000010 |
Definition at line 5188 of file cortex-m4-def.h.
| #define USB_TXCSRL3_STALLED 0x00000020 |
Definition at line 5187 of file cortex-m4-def.h.
| #define USB_TXCSRL3_TXRDY 0x00000001 |
Definition at line 5192 of file cortex-m4-def.h.
| #define USB_TXCSRL3_UNDRN 0x00000004 |
Definition at line 5190 of file cortex-m4-def.h.
| #define USB_TXCSRL4_CLRDT 0x00000040 |
Definition at line 5261 of file cortex-m4-def.h.
| #define USB_TXCSRL4_FIFONE 0x00000002 |
Definition at line 5266 of file cortex-m4-def.h.
| #define USB_TXCSRL4_FLUSH 0x00000008 |
Definition at line 5264 of file cortex-m4-def.h.
| #define USB_TXCSRL4_STALL 0x00000010 |
Definition at line 5263 of file cortex-m4-def.h.
| #define USB_TXCSRL4_STALLED 0x00000020 |
Definition at line 5262 of file cortex-m4-def.h.
| #define USB_TXCSRL4_TXRDY 0x00000001 |
Definition at line 5267 of file cortex-m4-def.h.
| #define USB_TXCSRL4_UNDRN 0x00000004 |
Definition at line 5265 of file cortex-m4-def.h.
| #define USB_TXCSRL5_CLRDT 0x00000040 |
Definition at line 5336 of file cortex-m4-def.h.
| #define USB_TXCSRL5_FIFONE 0x00000002 |
Definition at line 5341 of file cortex-m4-def.h.
| #define USB_TXCSRL5_FLUSH 0x00000008 |
Definition at line 5339 of file cortex-m4-def.h.
| #define USB_TXCSRL5_STALL 0x00000010 |
Definition at line 5338 of file cortex-m4-def.h.
| #define USB_TXCSRL5_STALLED 0x00000020 |
Definition at line 5337 of file cortex-m4-def.h.
| #define USB_TXCSRL5_TXRDY 0x00000001 |
Definition at line 5342 of file cortex-m4-def.h.
| #define USB_TXCSRL5_UNDRN 0x00000004 |
Definition at line 5340 of file cortex-m4-def.h.
| #define USB_TXCSRL6_CLRDT 0x00000040 |
Definition at line 5411 of file cortex-m4-def.h.
| #define USB_TXCSRL6_FIFONE 0x00000002 |
Definition at line 5416 of file cortex-m4-def.h.
| #define USB_TXCSRL6_FLUSH 0x00000008 |
Definition at line 5414 of file cortex-m4-def.h.
| #define USB_TXCSRL6_STALL 0x00000010 |
Definition at line 5413 of file cortex-m4-def.h.
| #define USB_TXCSRL6_STALLED 0x00000020 |
Definition at line 5412 of file cortex-m4-def.h.
| #define USB_TXCSRL6_TXRDY 0x00000001 |
Definition at line 5417 of file cortex-m4-def.h.
| #define USB_TXCSRL6_UNDRN 0x00000004 |
Definition at line 5415 of file cortex-m4-def.h.
| #define USB_TXCSRL7_CLRDT 0x00000040 |
Definition at line 5486 of file cortex-m4-def.h.
| #define USB_TXCSRL7_FIFONE 0x00000002 |
Definition at line 5491 of file cortex-m4-def.h.
| #define USB_TXCSRL7_FLUSH 0x00000008 |
Definition at line 5489 of file cortex-m4-def.h.
| #define USB_TXCSRL7_STALL 0x00000010 |
Definition at line 5488 of file cortex-m4-def.h.
| #define USB_TXCSRL7_STALLED 0x00000020 |
Definition at line 5487 of file cortex-m4-def.h.
| #define USB_TXCSRL7_TXRDY 0x00000001 |
Definition at line 5492 of file cortex-m4-def.h.
| #define USB_TXCSRL7_UNDRN 0x00000004 |
Definition at line 5490 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP1 0x00000002 |
Definition at line 5587 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP2 0x00000004 |
Definition at line 5585 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP3 0x00000008 |
Definition at line 5583 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP4 0x00000010 |
Definition at line 5581 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP5 0x00000020 |
Definition at line 5579 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP6 0x00000040 |
Definition at line 5577 of file cortex-m4-def.h.
| #define USB_TXDPKTBUFDIS_EP7 0x00000080 |
Definition at line 5575 of file cortex-m4-def.h.
| #define USB_TXFIFOADD_ADDR_M 0x000001FF |
Definition at line 4956 of file cortex-m4-def.h.
| #define USB_TXFIFOADD_ADDR_S 0 |
Definition at line 4957 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_DPB 0x00000010 |
Definition at line 4921 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_1024 0x00000007 |
Definition at line 4930 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_128 0x00000004 |
Definition at line 4927 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_16 0x00000001 |
Definition at line 4924 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_2048 0x00000008 |
Definition at line 4931 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_256 0x00000005 |
Definition at line 4928 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_32 0x00000002 |
Definition at line 4925 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_512 0x00000006 |
Definition at line 4929 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_64 0x00000003 |
Definition at line 4926 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_8 0x00000000 |
Definition at line 4923 of file cortex-m4-def.h.
| #define USB_TXFIFOSZ_SIZE_M 0x0000000F |
Definition at line 4922 of file cortex-m4-def.h.
| #define USB_TXIE_EP0 0x00000001 |
Definition at line 4790 of file cortex-m4-def.h.
| #define USB_TXIE_EP1 0x00000002 |
Definition at line 4789 of file cortex-m4-def.h.
| #define USB_TXIE_EP2 0x00000004 |
Definition at line 4788 of file cortex-m4-def.h.
| #define USB_TXIE_EP3 0x00000008 |
Definition at line 4787 of file cortex-m4-def.h.
| #define USB_TXIE_EP4 0x00000010 |
Definition at line 4786 of file cortex-m4-def.h.
| #define USB_TXIE_EP5 0x00000020 |
Definition at line 4785 of file cortex-m4-def.h.
| #define USB_TXIE_EP6 0x00000040 |
Definition at line 4784 of file cortex-m4-def.h.
| #define USB_TXIE_EP7 0x00000080 |
Definition at line 4783 of file cortex-m4-def.h.
| #define USB_TXIS_EP0 0x00000001 |
Definition at line 4763 of file cortex-m4-def.h.
| #define USB_TXIS_EP1 0x00000002 |
Definition at line 4762 of file cortex-m4-def.h.
| #define USB_TXIS_EP2 0x00000004 |
Definition at line 4761 of file cortex-m4-def.h.
| #define USB_TXIS_EP3 0x00000008 |
Definition at line 4760 of file cortex-m4-def.h.
| #define USB_TXIS_EP4 0x00000010 |
Definition at line 4759 of file cortex-m4-def.h.
| #define USB_TXIS_EP5 0x00000020 |
Definition at line 4758 of file cortex-m4-def.h.
| #define USB_TXIS_EP6 0x00000040 |
Definition at line 4757 of file cortex-m4-def.h.
| #define USB_TXIS_EP7 0x00000080 |
Definition at line 4756 of file cortex-m4-def.h.
| #define USB_TXMAXP1_MAXLOAD_M 0x000007FF |
Definition at line 5028 of file cortex-m4-def.h.
| #define USB_TXMAXP1_MAXLOAD_S 0 |
Definition at line 5029 of file cortex-m4-def.h.
| #define USB_TXMAXP2_MAXLOAD_M 0x000007FF |
Definition at line 5103 of file cortex-m4-def.h.
| #define USB_TXMAXP2_MAXLOAD_S 0 |
Definition at line 5104 of file cortex-m4-def.h.
| #define USB_TXMAXP3_MAXLOAD_M 0x000007FF |
Definition at line 5178 of file cortex-m4-def.h.
| #define USB_TXMAXP3_MAXLOAD_S 0 |
Definition at line 5179 of file cortex-m4-def.h.
| #define USB_TXMAXP4_MAXLOAD_M 0x000007FF |
Definition at line 5253 of file cortex-m4-def.h.
| #define USB_TXMAXP4_MAXLOAD_S 0 |
Definition at line 5254 of file cortex-m4-def.h.
| #define USB_TXMAXP5_MAXLOAD_M 0x000007FF |
Definition at line 5328 of file cortex-m4-def.h.
| #define USB_TXMAXP5_MAXLOAD_S 0 |
Definition at line 5329 of file cortex-m4-def.h.
| #define USB_TXMAXP6_MAXLOAD_M 0x000007FF |
Definition at line 5403 of file cortex-m4-def.h.
| #define USB_TXMAXP6_MAXLOAD_S 0 |
Definition at line 5404 of file cortex-m4-def.h.
| #define USB_TXMAXP7_MAXLOAD_M 0x000007FF |
Definition at line 5478 of file cortex-m4-def.h.
| #define USB_TXMAXP7_MAXLOAD_S 0 |
Definition at line 5479 of file cortex-m4-def.h.
| #define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008)) |
Definition at line 55 of file cortex-m4-def.h.
| #define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C)) |
Definition at line 56 of file cortex-m4-def.h.
| #define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000)) |
Definition at line 53 of file cortex-m4-def.h.
| #define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00)) |
Definition at line 60 of file cortex-m4-def.h.
| #define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014)) |
Definition at line 58 of file cortex-m4-def.h.
| #define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010)) |
Definition at line 57 of file cortex-m4-def.h.
| #define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418)) |
Definition at line 59 of file cortex-m4-def.h.
| #define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004)) |
Definition at line 54 of file cortex-m4-def.h.
| #define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008)) |
Definition at line 69 of file cortex-m4-def.h.
| #define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C)) |
Definition at line 70 of file cortex-m4-def.h.
| #define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000)) |
Definition at line 67 of file cortex-m4-def.h.
| #define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00)) |
Definition at line 74 of file cortex-m4-def.h.
| #define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014)) |
Definition at line 72 of file cortex-m4-def.h.
| #define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010)) |
Definition at line 71 of file cortex-m4-def.h.
| #define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418)) |
Definition at line 73 of file cortex-m4-def.h.
| #define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004)) |
Definition at line 68 of file cortex-m4-def.h.
| #define WDT_CTL_INTEN 0x00000001 |
Definition at line 1985 of file cortex-m4-def.h.
| #define WDT_CTL_INTTYPE 0x00000004 |
Definition at line 1983 of file cortex-m4-def.h.
| #define WDT_CTL_RESEN 0x00000002 |
Definition at line 1984 of file cortex-m4-def.h.
| #define WDT_CTL_WRC 0x80000000 |
Definition at line 1982 of file cortex-m4-def.h.
| #define WDT_ICR_M 0xFFFFFFFF |
Definition at line 1992 of file cortex-m4-def.h.
| #define WDT_ICR_S 0 |
Definition at line 1993 of file cortex-m4-def.h.
| #define WDT_LOAD_M 0xFFFFFFFF |
Definition at line 1966 of file cortex-m4-def.h.
| #define WDT_LOAD_S 0 |
Definition at line 1967 of file cortex-m4-def.h.
| #define WDT_LOCK_LOCKED 0x00000001 |
Definition at line 2023 of file cortex-m4-def.h.
| #define WDT_LOCK_M 0xFFFFFFFF |
Definition at line 2021 of file cortex-m4-def.h.
| #define WDT_LOCK_UNLOCKED 0x00000000 |
Definition at line 2022 of file cortex-m4-def.h.
| #define WDT_MIS_WDTMIS 0x00000001 |
Definition at line 2007 of file cortex-m4-def.h.
| #define WDT_RIS_WDTRIS 0x00000001 |
Definition at line 2000 of file cortex-m4-def.h.
| #define WDT_TEST_STALL 0x00000100 |
Definition at line 2014 of file cortex-m4-def.h.
| #define WDT_VALUE_M 0xFFFFFFFF |
Definition at line 1974 of file cortex-m4-def.h.
| #define WDT_VALUE_S 0 |
Definition at line 1975 of file cortex-m4-def.h.
| #define WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000)) |
Definition at line 922 of file cortex-m4-def.h.
| #define WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C)) |
Definition at line 925 of file cortex-m4-def.h.
| #define WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024)) |
Definition at line 930 of file cortex-m4-def.h.
| #define WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018)) |
Definition at line 927 of file cortex-m4-def.h.
| #define WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020)) |
Definition at line 929 of file cortex-m4-def.h.
| #define WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0)) |
Definition at line 948 of file cortex-m4-def.h.
| #define WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C)) |
Definition at line 928 of file cortex-m4-def.h.
| #define WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058)) |
Definition at line 943 of file cortex-m4-def.h.
| #define WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010)) |
Definition at line 926 of file cortex-m4-def.h.
| #define WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028)) |
Definition at line 931 of file cortex-m4-def.h.
| #define WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030)) |
Definition at line 933 of file cortex-m4-def.h.
| #define WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004)) |
Definition at line 923 of file cortex-m4-def.h.
| #define WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040)) |
Definition at line 937 of file cortex-m4-def.h.
| #define WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038)) |
Definition at line 935 of file cortex-m4-def.h.
| #define WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C)) |
Definition at line 944 of file cortex-m4-def.h.
| #define WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064)) |
Definition at line 946 of file cortex-m4-def.h.
| #define WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048)) |
Definition at line 939 of file cortex-m4-def.h.
| #define WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050)) |
Definition at line 941 of file cortex-m4-def.h.
| #define WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C)) |
Definition at line 932 of file cortex-m4-def.h.
| #define WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034)) |
Definition at line 934 of file cortex-m4-def.h.
| #define WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008)) |
Definition at line 924 of file cortex-m4-def.h.
| #define WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044)) |
Definition at line 938 of file cortex-m4-def.h.
| #define WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C)) |
Definition at line 936 of file cortex-m4-def.h.
| #define WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060)) |
Definition at line 945 of file cortex-m4-def.h.
| #define WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068)) |
Definition at line 947 of file cortex-m4-def.h.
| #define WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C)) |
Definition at line 940 of file cortex-m4-def.h.
| #define WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054)) |
Definition at line 942 of file cortex-m4-def.h.
| #define WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000)) |
Definition at line 955 of file cortex-m4-def.h.
| #define WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C)) |
Definition at line 958 of file cortex-m4-def.h.
| #define WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024)) |
Definition at line 963 of file cortex-m4-def.h.
| #define WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018)) |
Definition at line 960 of file cortex-m4-def.h.
| #define WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020)) |
Definition at line 962 of file cortex-m4-def.h.
| #define WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0)) |
Definition at line 981 of file cortex-m4-def.h.
| #define WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C)) |
Definition at line 961 of file cortex-m4-def.h.
| #define WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058)) |
Definition at line 976 of file cortex-m4-def.h.
| #define WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010)) |
Definition at line 959 of file cortex-m4-def.h.
| #define WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028)) |
Definition at line 964 of file cortex-m4-def.h.
| #define WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030)) |
Definition at line 966 of file cortex-m4-def.h.
| #define WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004)) |
Definition at line 956 of file cortex-m4-def.h.
| #define WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040)) |
Definition at line 970 of file cortex-m4-def.h.
| #define WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038)) |
Definition at line 968 of file cortex-m4-def.h.
| #define WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C)) |
Definition at line 977 of file cortex-m4-def.h.
| #define WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064)) |
Definition at line 979 of file cortex-m4-def.h.
| #define WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048)) |
Definition at line 972 of file cortex-m4-def.h.
| #define WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050)) |
Definition at line 974 of file cortex-m4-def.h.
| #define WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C)) |
Definition at line 965 of file cortex-m4-def.h.
| #define WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034)) |
Definition at line 967 of file cortex-m4-def.h.
| #define WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008)) |
Definition at line 957 of file cortex-m4-def.h.
| #define WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044)) |
Definition at line 971 of file cortex-m4-def.h.
| #define WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C)) |
Definition at line 969 of file cortex-m4-def.h.
| #define WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060)) |
Definition at line 978 of file cortex-m4-def.h.
| #define WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068)) |
Definition at line 980 of file cortex-m4-def.h.
| #define WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C)) |
Definition at line 973 of file cortex-m4-def.h.
| #define WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054)) |
Definition at line 975 of file cortex-m4-def.h.
| #define WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000)) |
Definition at line 1170 of file cortex-m4-def.h.
| #define WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C)) |
Definition at line 1173 of file cortex-m4-def.h.
| #define WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024)) |
Definition at line 1178 of file cortex-m4-def.h.
| #define WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018)) |
Definition at line 1175 of file cortex-m4-def.h.
| #define WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020)) |
Definition at line 1177 of file cortex-m4-def.h.
| #define WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0)) |
Definition at line 1196 of file cortex-m4-def.h.
| #define WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C)) |
Definition at line 1176 of file cortex-m4-def.h.
| #define WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058)) |
Definition at line 1191 of file cortex-m4-def.h.
| #define WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010)) |
Definition at line 1174 of file cortex-m4-def.h.
| #define WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028)) |
Definition at line 1179 of file cortex-m4-def.h.
| #define WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030)) |
Definition at line 1181 of file cortex-m4-def.h.
| #define WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004)) |
Definition at line 1171 of file cortex-m4-def.h.
| #define WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040)) |
Definition at line 1185 of file cortex-m4-def.h.
| #define WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038)) |
Definition at line 1183 of file cortex-m4-def.h.
| #define WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C)) |
Definition at line 1192 of file cortex-m4-def.h.
| #define WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064)) |
Definition at line 1194 of file cortex-m4-def.h.
| #define WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048)) |
Definition at line 1187 of file cortex-m4-def.h.
| #define WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050)) |
Definition at line 1189 of file cortex-m4-def.h.
| #define WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C)) |
Definition at line 1180 of file cortex-m4-def.h.
| #define WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034)) |
Definition at line 1182 of file cortex-m4-def.h.
| #define WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008)) |
Definition at line 1172 of file cortex-m4-def.h.
| #define WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044)) |
Definition at line 1186 of file cortex-m4-def.h.
| #define WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C)) |
Definition at line 1184 of file cortex-m4-def.h.
| #define WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060)) |
Definition at line 1193 of file cortex-m4-def.h.
| #define WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068)) |
Definition at line 1195 of file cortex-m4-def.h.
| #define WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C)) |
Definition at line 1188 of file cortex-m4-def.h.
| #define WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054)) |
Definition at line 1190 of file cortex-m4-def.h.
| #define WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000)) |
Definition at line 1203 of file cortex-m4-def.h.
| #define WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C)) |
Definition at line 1206 of file cortex-m4-def.h.
| #define WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024)) |
Definition at line 1211 of file cortex-m4-def.h.
| #define WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018)) |
Definition at line 1208 of file cortex-m4-def.h.
| #define WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020)) |
Definition at line 1210 of file cortex-m4-def.h.
| #define WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0)) |
Definition at line 1229 of file cortex-m4-def.h.
| #define WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C)) |
Definition at line 1209 of file cortex-m4-def.h.
| #define WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058)) |
Definition at line 1224 of file cortex-m4-def.h.
| #define WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010)) |
Definition at line 1207 of file cortex-m4-def.h.
| #define WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028)) |
Definition at line 1212 of file cortex-m4-def.h.
| #define WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030)) |
Definition at line 1214 of file cortex-m4-def.h.
| #define WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004)) |
Definition at line 1204 of file cortex-m4-def.h.
| #define WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040)) |
Definition at line 1218 of file cortex-m4-def.h.
| #define WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038)) |
Definition at line 1216 of file cortex-m4-def.h.
| #define WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C)) |
Definition at line 1225 of file cortex-m4-def.h.
| #define WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064)) |
Definition at line 1227 of file cortex-m4-def.h.
| #define WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048)) |
Definition at line 1220 of file cortex-m4-def.h.
| #define WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050)) |
Definition at line 1222 of file cortex-m4-def.h.
| #define WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C)) |
Definition at line 1213 of file cortex-m4-def.h.
| #define WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034)) |
Definition at line 1215 of file cortex-m4-def.h.
| #define WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008)) |
Definition at line 1205 of file cortex-m4-def.h.
| #define WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044)) |
Definition at line 1219 of file cortex-m4-def.h.
| #define WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C)) |
Definition at line 1217 of file cortex-m4-def.h.
| #define WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060)) |
Definition at line 1226 of file cortex-m4-def.h.
| #define WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068)) |
Definition at line 1228 of file cortex-m4-def.h.
| #define WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C)) |
Definition at line 1221 of file cortex-m4-def.h.
| #define WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054)) |
Definition at line 1223 of file cortex-m4-def.h.
| #define WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000)) |
Definition at line 1236 of file cortex-m4-def.h.
| #define WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C)) |
Definition at line 1239 of file cortex-m4-def.h.
| #define WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024)) |
Definition at line 1244 of file cortex-m4-def.h.
| #define WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018)) |
Definition at line 1241 of file cortex-m4-def.h.
| #define WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020)) |
Definition at line 1243 of file cortex-m4-def.h.
| #define WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0)) |
Definition at line 1262 of file cortex-m4-def.h.
| #define WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C)) |
Definition at line 1242 of file cortex-m4-def.h.
| #define WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058)) |
Definition at line 1257 of file cortex-m4-def.h.
| #define WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010)) |
Definition at line 1240 of file cortex-m4-def.h.
| #define WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028)) |
Definition at line 1245 of file cortex-m4-def.h.
| #define WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030)) |
Definition at line 1247 of file cortex-m4-def.h.
| #define WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004)) |
Definition at line 1237 of file cortex-m4-def.h.
| #define WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040)) |
Definition at line 1251 of file cortex-m4-def.h.
| #define WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038)) |
Definition at line 1249 of file cortex-m4-def.h.
| #define WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C)) |
Definition at line 1258 of file cortex-m4-def.h.
| #define WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064)) |
Definition at line 1260 of file cortex-m4-def.h.
| #define WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048)) |
Definition at line 1253 of file cortex-m4-def.h.
| #define WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050)) |
Definition at line 1255 of file cortex-m4-def.h.
| #define WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C)) |
Definition at line 1246 of file cortex-m4-def.h.
| #define WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034)) |
Definition at line 1248 of file cortex-m4-def.h.
| #define WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008)) |
Definition at line 1238 of file cortex-m4-def.h.
| #define WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044)) |
Definition at line 1252 of file cortex-m4-def.h.
| #define WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C)) |
Definition at line 1250 of file cortex-m4-def.h.
| #define WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060)) |
Definition at line 1259 of file cortex-m4-def.h.
| #define WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068)) |
Definition at line 1261 of file cortex-m4-def.h.
| #define WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C)) |
Definition at line 1254 of file cortex-m4-def.h.
| #define WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054)) |
Definition at line 1256 of file cortex-m4-def.h.
| #define WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000)) |
Definition at line 1269 of file cortex-m4-def.h.
| #define WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C)) |
Definition at line 1272 of file cortex-m4-def.h.
| #define WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024)) |
Definition at line 1277 of file cortex-m4-def.h.
| #define WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018)) |
Definition at line 1274 of file cortex-m4-def.h.
| #define WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020)) |
Definition at line 1276 of file cortex-m4-def.h.
| #define WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0)) |
Definition at line 1295 of file cortex-m4-def.h.
| #define WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C)) |
Definition at line 1275 of file cortex-m4-def.h.
| #define WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058)) |
Definition at line 1290 of file cortex-m4-def.h.
| #define WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010)) |
Definition at line 1273 of file cortex-m4-def.h.
| #define WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028)) |
Definition at line 1278 of file cortex-m4-def.h.
| #define WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030)) |
Definition at line 1280 of file cortex-m4-def.h.
| #define WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004)) |
Definition at line 1270 of file cortex-m4-def.h.
| #define WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040)) |
Definition at line 1284 of file cortex-m4-def.h.
| #define WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038)) |
Definition at line 1282 of file cortex-m4-def.h.
| #define WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C)) |
Definition at line 1291 of file cortex-m4-def.h.
| #define WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064)) |
Definition at line 1293 of file cortex-m4-def.h.
| #define WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048)) |
Definition at line 1286 of file cortex-m4-def.h.
| #define WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050)) |
Definition at line 1288 of file cortex-m4-def.h.
| #define WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C)) |
Definition at line 1279 of file cortex-m4-def.h.
| #define WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034)) |
Definition at line 1281 of file cortex-m4-def.h.
| #define WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008)) |
Definition at line 1271 of file cortex-m4-def.h.
| #define WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044)) |
Definition at line 1285 of file cortex-m4-def.h.
| #define WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C)) |
Definition at line 1283 of file cortex-m4-def.h.
| #define WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060)) |
Definition at line 1292 of file cortex-m4-def.h.
| #define WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068)) |
Definition at line 1294 of file cortex-m4-def.h.
| #define WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C)) |
Definition at line 1287 of file cortex-m4-def.h.
| #define WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054)) |
Definition at line 1289 of file cortex-m4-def.h.
1.8.14